CN115840486A - Curvature compensation band gap reference circuit - Google Patents
Curvature compensation band gap reference circuit Download PDFInfo
- Publication number
- CN115840486A CN115840486A CN202211261025.8A CN202211261025A CN115840486A CN 115840486 A CN115840486 A CN 115840486A CN 202211261025 A CN202211261025 A CN 202211261025A CN 115840486 A CN115840486 A CN 115840486A
- Authority
- CN
- China
- Prior art keywords
- pmos
- tube
- electrode
- drain electrode
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Amplifiers (AREA)
Abstract
The invention discloses a curvature compensation band gap reference circuit, which comprises a starting circuit, a reference circuit and a control circuit, wherein the starting circuit is used for enabling the circuit to be separated from a zero state point and enter a working state; the first-order temperature compensation band gap reference unit is used for generating positive temperature coefficient current and negative temperature coefficient current and summing the positive temperature coefficient current and the negative temperature coefficient current so as to eliminate a temperature-related first-order term in band gap reference voltage; and the second-order temperature compensation band-gap reference unit is used for generating a compensation current to eliminate the second term of the band-gap reference voltage. The curvature compensation band gap reference circuit provided by the invention can eliminate the temperature-related primary term and secondary term in the output reference voltage, reduce the temperature drift coefficient, enhance the stability of the circuit through a negative feedback structure, and obtain higher power supply rejection ratio and good temperature characteristic in a wider temperature range.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a curvature compensation band gap reference circuit.
Background
The band-gap reference circuit is a basic module in the field of analog integrated circuit design, and is used for providing a reference voltage which changes little along with external factors for the whole circuit, wherein the voltage has good temperature stability and higher power supply rejection ratio, namely changes little along with temperature and power supply voltage.
The traditional band-gap reference circuit utilizes a bipolar junction transistor BJT and an operational amplifier clamping technology to obtain a path of current IPTAT positively correlated with temperature and a path of current ICTAT negatively correlated with temperature, and then the current IPTAT and the current ICTAT are added and multiplied by a resistor to obtain reference voltage. The first order of the temperature coefficient is eliminated by the scheme.
However, the temperature characteristic curve is compensated only in the first order by the above method, and the obtained reference voltage still contains high-order terms related to temperature, so the temperature characteristic curve presents a parabolic shape with a quadratic term being dominant, and the temperature coefficient obtained by calculating the reference voltage still generally has tens or tens, and generally, the requirement of high stability in high-precision analog integrated circuit design is difficult to meet.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a curvature compensation bandgap reference circuit. The technical problem to be solved by the invention is realized by the following technical scheme:
a curvature compensated bandgap reference circuit comprising:
the starting circuit is used for enabling the circuit to be separated from a zero state point and enter a working state;
the first-order temperature compensation band gap reference unit is used for generating positive temperature coefficient current and negative temperature coefficient current and summing the positive temperature coefficient current and the negative temperature coefficient current so as to eliminate a temperature-related first-order term in band gap reference voltage;
and the second-order temperature compensation band-gap reference unit is used for generating a compensation current to eliminate the second term of the band-gap reference voltage.
In one embodiment of the present invention, the start-up circuit includes a PMOS transistor PM1, a PMOS transistor PM2, an NMOS transistor NM1, and an NMOS transistor NM2; wherein the content of the first and second substances,
the source electrode of the PMOS pipe PM1 is connected with a power supply voltage VDD end, and the grid electrode and the drain electrode of the PMOS pipe PM1 are connected and are commonly connected with the source electrode of the PMOS pipe PM 2;
the grid electrode and the drain electrode of the PMOS tube PM2, the drain electrode of the NMOS tube NM1 and the grid electrode of the NMOS tube NM2 are connected;
the grid electrode of the NMOS tube NM1 is connected with a band-gap reference output voltage vref;
the source electrode of the NMOS tube NM1 and the source electrode of the NMOS tube NM2 are both connected with a common ground end;
and the drain electrode of the NMOS tube NM2 is used as the output end of the starting circuit and is connected with the input end of the first-order temperature compensation band gap reference unit.
In an embodiment of the invention, the first-order temperature compensation bandgap reference unit includes a PMOS transistor PM3, a PMOS transistor PM4, a PMOS transistor PM5, an operational amplifier OPA1, a resistor R0, a resistor R1, a resistor R2, a resistor R3, a PNP transistor Q1, and a PNP transistor Q2; wherein the content of the first and second substances,
the grid electrode of the PMOS tube PM3, the grid electrode of the PMOS tube PM4 and the grid electrode of the PMOS tube PM5 are connected and then serve as the input end of the first-order temperature compensation band gap reference unit to be connected with the output end of the starting circuit;
the source electrode of the PMOS pipe PM3, the source electrode of the PMOS pipe PM4 and the source electrode of the PMOS pipe PM5 are connected with a power supply voltage VDD end;
the drain of the PMOS transistor PM3 is connected to the positive input end VIP of the operational amplifier OPA1, one end of the resistor R1, and the emitter of the PNP transistor Q1;
the drain electrode of the PMOS tube PM4 is connected with the negative input end VIN of the operational amplifier OPA1, one end of the resistor R0 and one end of the resistor R2;
the other end of the resistor R0 is connected with an emitting electrode of the PNP transistor Q2;
an output end VOUT of the operational amplifier OPA1 is connected to a grid electrode of the PMOS pipe PM3, a grid electrode of the PMOS pipe PM4 and a grid electrode of the PMOS pipe PM 5;
the other end of the resistor R1, the base electrode and the collector electrode of the PNP type transistor Q2 and the other end of the resistor R2 are all connected to a common ground end;
the drain electrode of the PMOS tube PM5 is connected with a common ground end through the resistor R3, and the drain electrode of the PMOS tube PM5 is used as the output end of the first-order temperature compensation band gap reference unit and is connected with the input end of the second-order temperature compensation band gap reference unit;
and the drain electrode of the PMOS pipe PM5 is also used as the output end of the band-gap reference circuit to output band-gap reference voltage vref.
In one embodiment of the invention, the operational amplifier OPA1 comprises a PMOS tube PM2-1, a PMOS tube PM2-2, a PMOS tube PM2-3, a PMOS tube PM2-4, a PMOS tube PM2-5, a PMOS tube PM2-6, an NMOS tube NM2-1, an NMOS tube NM2-2, an NMOS tube NM2-3, an NMOS tube NM2-4, an NMOS tube NM2-5, a capacitor C2-1, a resistor R2-1 and a resistor R2-2; wherein, the first and the second end of the pipe are connected with each other,
the source electrode of the PMOS tube PM2-1, the source electrode of the PMOS tube PM2-2, the source electrode of the PMOS tube PM2-3 and the source electrode of the PMOS tube PM2-6 are all connected with a power supply voltage VDD end;
the drain electrode of the PMOS tube PM2-1, the drain electrode and the grid electrode of the NMOS tube NM2-1 and the grid electrode of the NMOS tube NM2-2 are connected;
the grid electrode of the PMOS tube PM2-1, the grid electrode and the drain electrode of the PMOS tube PM2-2, the drain electrode of the NMOS tube NM2-2, the grid electrode of the PMOS tube PM2-3 and the grid electrode of the PMOS tube PM2-6 are connected;
the source electrode of the NMOS tube NM2-2 is connected with a common ground end through the resistor R2-1;
the drain electrode of the PMOS pipe PM2-3 is connected with the source electrode of the PMOS pipe PM2-4 and the source electrode of the PMOS pipe PM 2-5;
the drain electrode of the PMOS tube PM2-4, the drain electrode and the grid electrode of the NMOS tube NM2-3 and the grid electrode of the NMOS tube NM2-4 are connected;
the grid electrode of the PMOS tube PM2-4 is used as a negative input end VIN of the operational amplifier OPA 1;
the drain electrode of the PMOS tube PM2-5 is connected with the drain electrode of the NMOS tube NM2-4, one end of the capacitor C2-1 and the grid electrode of the NMOS tube NM 2-5;
the other end of the capacitor C2-1 is connected with the drain electrode of the NMOS tube NM2-5 through the resistor R2-2;
the grid electrode of the PMOS pipe PM2-5 is used as the positive input end VIP of the operational amplifier OPA 1;
the drain electrode of the PMOS tube PM2-6 is connected with the drain electrode of the NMOS tube NM2-5 and is used as the output end VOUT of the operational amplifier OPA 1;
the source electrode of the NMOS tube NM2-1, the source electrode of the NMOS tube NM2-3, the source electrode of the NMOS tube NM2-4 and the source electrode of the NMOS tube NM2-5 are all connected to a common ground end.
In an embodiment of the present invention, the PMOS transistor PM3, the PMOS transistor PM4, and the PMOS transistor PM5 are equal in size.
In one embodiment of the invention, the second-order temperature compensation bandgap reference unit comprises a PMOS transistor PM6, an operational amplifier OPA2, an NMOS transistor NM3, a capacitor C1, a resistor R4 and a resistor R5; wherein the content of the first and second substances,
the source electrode of the PMOS pipe PM6 is connected with a power supply voltage VDD end, the grid electrode of the PMOS pipe PM6 is connected with the output end VOUT of the operational amplifier OPA2, and the drain electrode of the PMOS pipe PM6 is connected with the positive input end VIP of the operational amplifier OPA 2;
the negative input end VIN of the operational amplifier OPA2 is connected with the drain electrode of the NMOS tube NM3 and is used as the input end of the second-order temperature compensation band gap reference unit to be connected with the output end of the first-order temperature compensation band gap reference unit;
the capacitor C1 is connected between the drain electrode and the grid electrode of the NMOS tube NM 3;
the drain electrode of the NMOS tube NM3 is connected with a common ground end;
the resistor R4 and the resistor R5 are connected between the drain electrode of the PMOS pipe PM6 and the common ground end in series;
the grid electrode of the NMOS tube NM3 is also connected with the common end of the resistor R4 and the resistor R5.
In one embodiment of the invention, the operational amplifier OPA2 comprises a PMOS tube PM2-1, a PMOS tube PM2-2, a PMOS tube PM2-3, a PMOS tube PM2-4, a PMOS tube PM2-5, a PMOS tube PM2-6, an NMOS tube NM2-1, an NMOS tube NM2-2, an NMOS tube NM2-3, an NMOS tube NM2-4, an NMOS tube NM2-5, a capacitor C2-1, a resistor R2-1 and a resistor R2-2; wherein the content of the first and second substances,
the source electrode of the PMOS tube PM2-1, the source electrode of the PMOS tube PM2-2, the source electrode of the PMOS tube PM2-3 and the source electrode of the PMOS tube PM2-6 are all connected with a power supply voltage VDD end;
the drain electrode of the PMOS tube PM2-1, the drain electrode and the grid electrode of the NMOS tube NM2-1 and the grid electrode of the NMOS tube NM2-2 are connected;
the grid electrode of the PMOS tube PM2-1, the grid electrode and the drain electrode of the PMOS tube PM2-2, the drain electrode of the NMOS tube NM2-2, the grid electrode of the PMOS tube PM2-3 and the grid electrode of the PMOS tube PM2-6 are connected;
the source electrode of the NMOS tube NM2-2 is connected with a common ground end through the resistor R2-1;
the drain electrode of the PMOS pipe PM2-3 is connected with the source electrode of the PMOS pipe PM2-4 and the source electrode of the PMOS pipe PM 2-5;
the drain electrode of the PMOS tube PM2-4, the drain electrode and the grid electrode of the NMOS tube NM2-3 and the grid electrode of the NMOS tube NM2-4 are connected;
the grid electrode of the PMOS tube PM2-4 is used as a negative input end VIN of the operational amplifier OPA 2;
the drain electrode of the PMOS tube PM2-5 is connected with the drain electrode of the NMOS tube NM2-4, one end of the capacitor C2-1 and the grid electrode of the NMOS tube NM 2-5;
the other end of the capacitor C2-1 is connected with the drain electrode of the NMOS tube NM2-5 through the resistor R2-2;
the grid electrode of the PMOS pipe PM2-5 is used as the positive input end VIP of the operational amplifier OPA 2;
the drain electrode of the PMOS tube PM2-6 is connected with the drain electrode of the NMOS tube NM2-5 and is used as the output end VOUT of the operational amplifier OPA 2;
the source electrode of the NMOS tube NM2-1, the source electrode of the NMOS tube NM2-3, the source electrode of the NMOS tube NM2-4 and the source electrode of the NMOS tube NM2-5 are all connected to a common ground end.
The invention has the beneficial effects that:
1. according to the curvature compensation band gap reference circuit provided by the invention, a first-order temperature compensation band gap reference unit is utilized to generate band gap reference voltage without a primary term related to temperature, and a second-order temperature compensation band gap reference unit is utilized to generate compensation current to eliminate a secondary term related to temperature in the reference voltage, so that a lower temperature drift coefficient is obtained;
2. the second-order temperature compensation band gap reference unit in the curvature compensation band gap reference circuit simultaneously forms a negative feedback structure, when the band gap reference voltage vref is greatly changed due to external factors, the band gap reference voltage vref can be kept stable through the negative feedback structure, and a lower temperature drift coefficient and a higher power supply rejection ratio are further obtained.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic structural diagram of a curvature compensated bandgap reference circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an operational amplifier according to an embodiment of the present invention;
FIG. 3 is a graph of the results of a test of the bandgap reference voltage output by a curvature compensated bandgap reference circuit as a function of temperature, according to an embodiment of the present invention;
fig. 4 is a test result graph of the power supply rejection ratio of the curvature compensated bandgap reference circuit varying with frequency according to the embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a curvature (second order) compensation bandgap reference circuit according to an embodiment of the present invention, which includes:
the starting circuit 1 is used for enabling the circuit to be separated from a zero state point and enter a working state;
the first-order temperature compensation band gap reference unit 2 is used for generating positive temperature coefficient current and negative temperature coefficient current and summing the positive temperature coefficient current and the negative temperature coefficient current so as to eliminate a first-order term related to temperature in band gap reference voltage;
and the second-order temperature compensation band-gap reference unit 3 is used for generating compensation current to eliminate the second term of the band-gap reference voltage.
Specifically, in this embodiment, the start-up circuit 1 includes a PMOS transistor PM1, a PMOS transistor PM2, an NMOS transistor NM1, and an NMOS transistor NM2; wherein the content of the first and second substances,
the source electrode of the PMOS pipe PM1 is connected with a power voltage VDD end, and the grid electrode and the drain electrode of the PMOS pipe PM1 are connected and are commonly connected with the source electrode of the PMOS pipe PM 2;
the grid electrode and the drain electrode of the PMOS tube PM2, the drain electrode of the NMOS tube NM1 and the grid electrode of the NMOS tube NM2 are connected;
the grid of the NMOS tube NM1 is connected with a band-gap reference output voltage vref;
the source electrode of the NMOS tube NM1 and the source electrode of the NMOS tube NM2 are both connected with a common ground end;
the drain electrode of the NMOS tube NM2 is used as the output end of the starting circuit 1 and is connected with the input end of the first-order temperature compensation band gap reference unit 2.
Further, please refer to fig. 1, wherein the first-order temperature compensation bandgap reference unit 2 includes a PMOS transistor PM3, a PMOS transistor PM4, a PMOS transistor PM5, an operational amplifier OPA1, a resistor R0, a resistor R1, a resistor R2, a resistor R3, a PNP transistor Q1, and a PNP transistor Q2; wherein the content of the first and second substances,
the grid electrode of the PMOS tube PM3, the grid electrode of the PMOS tube PM4 and the grid electrode of the PMOS tube PM5 are connected and then serve as the input end of the first-order temperature compensation band gap reference unit 2 to be connected with the output end of the starting circuit 1;
the source electrode of the PMOS pipe PM3, the source electrode of the PMOS pipe PM4 and the source electrode of the PMOS pipe PM5 are connected with a power voltage VDD end;
the drain electrode of the PMOS pipe PM3 is connected with the positive input end VIP of the operational amplifier OPA1, one end of the resistor R1 and the emitter electrode of the PNP type transistor Q1;
the drain electrode of the PMOS tube PM4 is connected with the negative input end VIN of the operational amplifier OPA1, one end of the resistor R0 and one end of the resistor R2;
the other end of the resistor R0 is connected with an emitting electrode of the PNP transistor Q2;
an output end VOUT of the operational amplifier OPA1 is connected to a grid electrode of the PMOS pipe PM3, a grid electrode of the PMOS pipe PM4 and a grid electrode of the PMOS pipe PM 5;
the other end of the resistor R1, the base electrode and the collector electrode of the PNP type transistor Q2 and the other end of the resistor R2 are connected to a common ground end;
the drain electrode of the PMOS tube PM5 is connected with the common ground end through a resistor R3, and the drain electrode of the PMOS tube PM5 serving as the output end of the first-order temperature compensation band gap reference unit 2 is connected with the input end of the second-order temperature compensation band gap reference unit 3;
the drain electrode of the PMOS pipe PM5 is also used as the output end of the band gap reference circuit to output the band gap reference voltage vref.
In this embodiment, the operational amplifier OPA1 adopts a two-stage amplification structure, which can obtain a higher gain, a better clamping effect, and a higher power supply rejection ratio.
For example, the present embodiment can realize the operational amplifier OPA1 in the first-order temperature-compensated bandgap reference unit 2 using the operational amplifier structure shown in fig. 2. Specifically, it includes: PMOS pipe PM2-1, PMOS pipe PM2-2, PMOS pipe PM2-3, PMOS pipe PM2-4, PMOS pipe PM2-5, PMOS pipe PM2-6, NMOS pipe NM2-1, NMOS pipe NM2-2, NMOS pipe NM2-3, NMOS pipe NM2-4, NMOS pipe NM2-5, capacitance C2-1, resistance R2-1 and resistance R2-2; wherein the content of the first and second substances,
the source electrode of the PMOS tube PM2-1, the source electrode of the PMOS tube PM2-2, the source electrode of the PMOS tube PM2-3 and the source electrode of the PMOS tube PM2-6 are all connected with a power supply voltage VDD end;
the drain electrode of the PMOS tube PM2-1, the drain electrode and the grid electrode of the NMOS tube NM2-1 and the grid electrode of the NMOS tube NM2-2 are connected;
the grid electrode of the PMOS tube PM2-1, the grid electrode and the drain electrode of the PMOS tube PM2-2, the drain electrode of the NMOS tube NM2-2, the grid electrode of the PMOS tube PM2-3 and the grid electrode of the PMOS tube PM2-6 are connected;
the source electrode of the NMOS tube NM2-2 is connected with a common ground end through a resistor R2-1;
the drain electrode of the PMOS pipe PM2-3 is connected with the source electrode of the PMOS pipe PM2-4 and the source electrode of the PMOS pipe PM 2-5;
the drain electrode of the PMOS tube PM2-4, the drain electrode and the grid electrode of the NMOS tube NM2-3 and the grid electrode of the NMOS tube NM2-4 are connected;
the grid electrode of the PMOS pipe PM2-4 is used as the negative input end VIN of the operational amplifier OPA 1;
the drain electrode of the PMOS tube PM2-5 is connected with the drain electrode of the NMOS tube NM2-4, one end of the capacitor C2-1 and the grid electrode of the NMOS tube NM 2-5;
the other end of the capacitor C2-1 is connected with the drain electrode of the NMOS tube NM2-5 through a resistor R2-2;
the grid electrode of the PMOS pipe PM2-5 is used as the positive input end VIP of the operational amplifier OPA 1;
the drain electrode of the PMOS tube PM2-6 is connected with the drain electrode of the NMOS tube NM2-5 and is used as the output end VOUT of the operational amplifier OPA 1;
the source electrode of the NMOS tube NM2-1, the source electrode of the NMOS tube NM2-3, the source electrode of the NMOS tube NM2-4 and the source electrode of the NMOS tube NM2-5 are all connected to a common ground end.
Further, please refer to fig. 1, wherein the second-order temperature compensation bandgap reference unit 3 includes a PMOS transistor PM6, an operational amplifier OPA2, an NMOS transistor NM3, a capacitor C1, a resistor R4, and a resistor R5; wherein, the first and the second end of the pipe are connected with each other,
the source electrode of the PMOS tube PM6 is connected with a power supply voltage VDD end, the grid electrode of the PMOS tube PM6 is connected with the output end VOUT of the operational amplifier OPA2, and the drain electrode of the PMOS tube PM6 is connected with the positive input end VIP of the operational amplifier OPA 2;
the negative input end VIN of the operational amplifier OPA2 is connected with the drain electrode of the NMOS tube NM3, and is used as the input end of a second-order temperature compensation band gap reference unit (3) to be connected with the output end of the first-order temperature compensation band gap reference unit 2;
the capacitor C1 is connected between the drain electrode and the grid electrode of the NMOS tube NM 3;
the drain electrode of the NMOS tube NM3 is connected with a common ground end;
the resistor R4 and the resistor R5 are connected between the drain electrode of the PMOS pipe PM6 and the common ground end in series;
the grid electrode of the NMOS tube NM3 is also connected with the common end of the resistor R4 and the resistor R5.
In the embodiment, the operational amplifier OPA2 may have the same circuit structure as the operational amplifier OPA1, that is, the circuit structure shown in fig. 2, and in fig. 2, the gate of the PMOS transistor PM2-4 is used as the negative input terminal VIN of the operational amplifier OPA2, the gate of the PMOS transistor PM2-5 is used as the positive input terminal VIP of the operational amplifier OPA2, and the drain of the PMOS transistor PM2-6 is connected to the drain of the NMOS transistor NM2-5 and is used as the output terminal VOUT of the operational amplifier OPA 2.
The working principle of the curvature compensation band gap reference circuit provided by the embodiment is as follows:
in the starting circuit, when power is on, the grid voltage of the NMOS tube NM2 is changed into high potential, the grid potentials of the PMOS tube PM3 and the PMOS tube PM4 are pulled down, the first-order temperature compensation band gap reference unit starts to work, then the output reference voltage vref controls the NMOS tube NM1 to be opened, and therefore the grid potential of the NMOS tube NM2 is pulled down to turn off the NMOS tube NM2, and the starting process is completed.
In the first-order temperature compensation band gap reference unit, through the clamping action of an operational amplifier OPA1, the potentials of positive and negative input ends are equal, and the current flowing through a resistor R2 is negative temperature coefficient current ICTAT:
wherein, V be1 The base and emitter voltages of the PNP transistor Q1.
The current flowing through resistor R0 is a positive temperature coefficient current:
wherein, V be2 Is the base and emitter voltage, V, of a PNP transistor Q2 T Is a triode thermoelectric voltage, I 0 、NI 0 Collector currents, I, of PNP transistor Q1 and PNP transistor Q2 S1 、I S2 The saturation currents of the PNP transistor Q1 and the PNP transistor Q2 are respectively, and N is the ratio of the emitter areas of the PNP transistor Q2 and the PNP transistor Q1.
In this embodiment, the PMOS transistors PM3, PM4, and PM5 have the same size, so that the currents of the branches where the three PMOS transistors are located are the same, and are the sum of the positive temperature coefficient current and the negative temperature coefficient current, that is, the current does not contain the temperature-related first term.
In the second-order temperature compensation band-gap reference unit, the positive and negative input ends of the second-order temperature compensation band-gap reference unit are equal in potential through the clamping action of an operational amplifier OPA2, namely the potential of the positive input end of the second-order temperature compensation band-gap reference unit is equal to the potential of a band-gap reference output voltage vref, the NMOS tube NM3 works in a saturation region through adjusting the sizes of a resistor R4 and a resistor R5, and then the current I flowing through the NMOS tube NM3 1 Comprises the following steps:
wherein, mu N For NMOS tube carrier mobility, C ox Is the gate oxide capacitance per unit area, W is the width of NMOS tube NM3, L is the length of NMOS tube NM3, V TH Is the threshold voltage of the NMOS transistor NM 3.
Wherein the vref voltage formula is:
from this equation vref can be further expressed as:
wherein k is
I 0 Is a positive temperature coefficient current I PTAT And negative temperature coefficient current I CTAT The sum, containing a quadratic term related to temperature.
So that V can be utilized TH The temperature-dependent primary term relationship can eliminate the quadratic term relationship between vref and temperature in the above formula, so as to obtain a lower temperature drift coefficient.
In addition, the second-order temperature compensation band gap reference unit simultaneously forms a negative feedback loop, namely, the operational amplifier OPA2, the PMOS tube PM6, the resistor R4, the capacitor C1 and the NMOS tube NM3 form a negative feedback structure, so that the stability of the circuit can be improved, when the output band gap reference voltage vref is greatly changed due to temperature increase or other external factors, the current of the NMOS tube NM3 can be increased, the current flowing through the resistor R3 is drawn away, the output band gap reference voltage vref is reduced and kept stable, the temperature drift coefficient is further reduced, and the power supply rejection ratio is greatly improved.
In order to further verify the beneficial effects of the present invention, the present embodiment also tests the variation of the bandgap reference voltage with temperature and the variation of the power supply rejection ratio with frequency of the curvature compensated bandgap reference circuit, and the results are shown in fig. 3 and 4. Fig. 3 is a test result diagram of the variation of the bandgap reference voltage output by the curvature compensated bandgap reference circuit with temperature according to the embodiment of the present invention, which mainly shows the temperature characteristic curve of the output reference voltage within a wide temperature variation range (-40 ℃ to 160 ℃), and the result shows that the temperature drift coefficient of the curvature compensated bandgap reference circuit provided by the present invention can be as low as 00440000 ℃. In addition, as can be seen from fig. 3, the reference voltage is kept stable within-40 ℃ to 160 ℃, and the voltage is only changed by 10607uV, which shows that the bandgap reference voltage output by the invention can be kept stable within a wider temperature range.
Fig. 4 is a test result graph of the power supply rejection ratio of the curvature compensated bandgap reference circuit varying with frequency according to the embodiment of the present invention. As can be seen from fig. 4, at low frequencies, the power supply rejection ratio of the present invention is-77 dB, illustrating the higher power supply rejection ratio of the present invention.
In conclusion, the curvature compensation band gap reference circuit provided by the invention can eliminate the temperature-related primary term and secondary term in the output reference voltage, reduce the temperature drift coefficient, enhance the stability of the circuit through a negative feedback structure, and obtain higher power supply rejection ratio and good temperature characteristic in a wider temperature range.
In another embodiment of the present invention, the operational amplifier OPA2 in the second-order temperature compensation bandgap reference unit 3 may be replaced by a cascode negative feedback structure, which may also achieve a clamping effect, so as to obtain a voltage that is the same as the output reference voltage to control the gate of the NMOS transistor NM 3. The specific implementation process is not described in detail herein.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (7)
1. A curvature compensated bandgap reference circuit, comprising:
the starting circuit (1) is used for enabling the circuit to be separated from a zero state point and enter a working state;
the first-order temperature compensation band-gap reference unit (2) is used for generating positive temperature coefficient current and negative temperature coefficient current and summing the positive temperature coefficient current and the negative temperature coefficient current so as to eliminate a first-order term related to temperature in band-gap reference voltage;
a second order temperature compensated bandgap reference unit (3) for generating a compensation current to cancel the second term of the bandgap reference voltage.
2. The curvature compensation bandgap reference circuit according to claim 1, wherein the start-up circuit (1) comprises a PMOS transistor PM1, a PMOS transistor PM2, an NMOS transistor NM1 and an NMOS transistor NM2; wherein the content of the first and second substances,
the source electrode of the PMOS pipe PM1 is connected with a power supply voltage VDD end, and the grid electrode and the drain electrode of the PMOS pipe PM1 are connected and are commonly connected with the source electrode of the PMOS pipe PM 2;
the grid electrode and the drain electrode of the PMOS tube PM2, the drain electrode of the NMOS tube NM1 and the grid electrode of the NMOS tube NM2 are connected;
the grid of the NMOS tube NM1 is connected with a band-gap reference output voltage vref;
the source electrode of the NMOS tube NM1 and the source electrode of the NMOS tube NM2 are both connected with a common ground end;
and the drain electrode of the NMOS tube NM2 is used as the output end of the starting circuit (1) and is connected with the input end of the first-order temperature compensation band gap reference unit (2).
3. The curvature compensation bandgap reference circuit according to claim 1, wherein the first-order temperature compensation bandgap reference unit (2) comprises a PMOS transistor PM3, a PMOS transistor PM4, a PMOS transistor PM5, an operational amplifier OPA1, a resistor R0, a resistor R1, a resistor R2, a resistor R3, a PNP transistor Q1 and a PNP transistor Q2; wherein the content of the first and second substances,
the grid electrode of the PMOS tube PM3, the grid electrode of the PMOS tube PM4 and the grid electrode of the PMOS tube PM5 are connected and then serve as the input end of the first-order temperature compensation band gap reference unit (2) to be connected with the output end of the starting circuit (1);
the source electrode of the PMOS pipe PM3, the source electrode of the PMOS pipe PM4 and the source electrode of the PMOS pipe PM5 are connected with a power supply voltage VDD end;
the drain of the PMOS transistor PM3 is connected to the positive input end VIP of the operational amplifier OPA1, one end of the resistor R1, and the emitter of the PNP transistor Q1;
the drain electrode of the PMOS tube PM4 is connected with the negative input end VIN of the operational amplifier OPA1, one end of the resistor R0 and one end of the resistor R2;
the other end of the resistor R0 is connected with an emitting electrode of the PNP transistor Q2;
an output end VOUT of the operational amplifier OPA1 is connected to a grid electrode of the PMOS pipe PM3, a grid electrode of the PMOS pipe PM4 and a grid electrode of the PMOS pipe PM 5;
the other end of the resistor R1, the base electrode and the collector electrode of the PNP type transistor Q2 and the other end of the resistor R2 are all connected to a common ground end;
the drain electrode of the PMOS tube PM5 is connected with a common ground end through the resistor R3, and the drain electrode of the PMOS tube PM5 is used as the output end of the first-order temperature compensation band gap reference unit (2) and is connected with the input end of the second-order temperature compensation band gap reference unit (3);
and the drain electrode of the PMOS pipe PM5 is also used as the output end of the band gap reference circuit to output a band gap reference voltage vref.
4. The curvature compensation bandgap reference circuit according to claim 3, wherein the operational amplifier OPA1 comprises a PMOS transistor PM2-1, a PMOS transistor PM2-2, a PMOS transistor PM2-3, a PMOS transistor PM2-4, a PMOS transistor PM2-5, a PMOS transistor PM2-6, an NMOS transistor NM2-1, an NMOS transistor NM2-2, an NMOS transistor NM2-3, an NMOS transistor NM2-4, an NMOS transistor NM2-5, a capacitor C2-1, a resistor R2-1 and a resistor R2-2; wherein the content of the first and second substances,
the source electrode of the PMOS tube PM2-1, the source electrode of the PMOS tube PM2-2, the source electrode of the PMOS tube PM2-3 and the source electrode of the PMOS tube PM2-6 are all connected with a power supply voltage VDD end;
the drain electrode of the PMOS tube PM2-1, the drain electrode and the grid electrode of the NMOS tube NM2-1 and the grid electrode of the NMOS tube NM2-2 are connected;
the grid electrode of the PMOS tube PM2-1, the grid electrode and the drain electrode of the PMOS tube PM2-2, the drain electrode of the NMOS tube NM2-2, the grid electrode of the PMOS tube PM2-3 and the grid electrode of the PMOS tube PM2-6 are connected;
the source electrode of the NMOS tube NM2-2 is connected with a common ground end through the resistor R2-1;
the drain electrode of the PMOS pipe PM2-3 is connected with the source electrode of the PMOS pipe PM2-4 and the source electrode of the PMOS pipe PM 2-5;
the drain electrode of the PMOS tube PM2-4, the drain electrode and the grid electrode of the NMOS tube NM2-3 and the grid electrode of the NMOS tube NM2-4 are connected;
the grid electrode of the PMOS tube PM2-4 is used as a negative input end VIN of the operational amplifier OPA 1;
the drain electrode of the PMOS tube PM2-5 is connected with the drain electrode of the NMOS tube NM2-4, one end of the capacitor C2-1 and the grid electrode of the NMOS tube NM 2-5;
the other end of the capacitor C2-1 is connected with the drain electrode of the NMOS tube NM2-5 through the resistor R2-2;
the grid electrode of the PMOS pipe PM2-5 is used as the positive input end VIP of the operational amplifier OPA 1;
the drain electrode of the PMOS tube PM2-6 is connected with the drain electrode of the NMOS tube NM2-5 and is used as the output end VOUT of the operational amplifier OPA 1;
the source electrode of the NMOS tube NM2-1, the source electrode of the NMOS tube NM2-3, the source electrode of the NMOS tube NM2-4 and the source electrode of the NMOS tube NM2-5 are all connected to a common ground end.
5. The curvature compensated bandgap reference circuit of claim 3, wherein the PMOS transistors PM3, PM4 and PM5 are equal in size.
6. The curvature compensation bandgap reference circuit according to claim 1, wherein the second-order temperature compensation bandgap reference unit (3) comprises a PMOS transistor PM6, an operational amplifier OPA2, an NMOS transistor NM3, a capacitor C1, a resistor R4 and a resistor R5; wherein the content of the first and second substances,
the source electrode of the PMOS tube PM6 is connected with a power supply voltage VDD end, the grid electrode of the PMOS tube PM6 is connected with the output end VOUT of the operational amplifier OPA2, and the drain electrode of the PMOS tube PM6 is connected with the positive input end VIP of the operational amplifier OPA 2;
the negative input end VIN of the operational amplifier OPA2 is connected with the drain electrode of the NMOS tube NM3 and is used as the input end of the second-order temperature compensation band gap reference unit (3) to be connected with the output end of the first-order temperature compensation band gap reference unit (2);
the capacitor C1 is connected between the drain electrode and the grid electrode of the NMOS tube NM 3;
the drain electrode of the NMOS tube NM3 is connected with a common ground end;
the resistor R4 and the resistor R5 are connected between the drain electrode of the PMOS pipe PM6 and the common ground end in series;
the grid electrode of the NMOS tube NM3 is also connected with the common end of the resistor R4 and the resistor R5.
7. The curvature compensation bandgap reference circuit according to claim 6, wherein the operational amplifier OPA2 comprises a PMOS transistor PM2-1, a PMOS transistor PM2-2, a PMOS transistor PM2-3, a PMOS transistor PM2-4, a PMOS transistor PM2-5, a PMOS transistor PM2-6, an NMOS transistor NM2-1, an NMOS transistor NM2-2, an NMOS transistor NM2-3, an NMOS transistor NM2-4, an NMOS transistor NM2-5, a capacitor C2-1, a resistor R2-1 and a resistor R2-2; wherein the content of the first and second substances,
the source electrode of the PMOS tube PM2-1, the source electrode of the PMOS tube PM2-2, the source electrode of the PMOS tube PM2-3 and the source electrode of the PMOS tube PM2-6 are all connected with a power supply voltage VDD end;
the drain electrode of the PMOS tube PM2-1, the drain electrode and the grid electrode of the NMOS tube NM2-1 and the grid electrode of the NMOS tube NM2-2 are connected;
the grid electrode of the PMOS tube PM2-1, the grid electrode and the drain electrode of the PMOS tube PM2-2, the drain electrode of the NMOS tube NM2-2, the grid electrode of the PMOS tube PM2-3 and the grid electrode of the PMOS tube PM2-6 are connected;
the source electrode of the NMOS tube NM2-2 is connected with a common ground end through the resistor R2-1;
the drain electrode of the PMOS pipe PM2-3 is connected with the source electrode of the PMOS pipe PM2-4 and the source electrode of the PMOS pipe PM 2-5;
the drain electrode of the PMOS tube PM2-4, the drain electrode and the grid electrode of the NMOS tube NM2-3 and the grid electrode of the NMOS tube NM2-4 are connected;
the grid electrode of the PMOS tube PM2-4 is used as a negative input end VIN of the operational amplifier OPA 2;
the drain electrode of the PMOS tube PM2-5 is connected with the drain electrode of the NMOS tube NM2-4, one end of the capacitor C2-1 and the grid electrode of the NMOS tube NM 2-5;
the other end of the capacitor C2-1 is connected with the drain electrode of the NMOS tube NM2-5 through the resistor R2-2;
the grid electrode of the PMOS pipe PM2-5 is used as the positive input end VIP of the operational amplifier OPA 2;
the drain electrode of the PMOS tube PM2-6 is connected with the drain electrode of the NMOS tube NM2-5 and is used as the output end VOUT of the operational amplifier OPA 2;
the source electrode of the NMOS tube NM2-1, the source electrode of the NMOS tube NM2-3, the source electrode of the NMOS tube NM2-4 and the source electrode of the NMOS tube NM2-5 are all connected to a common ground end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211261025.8A CN115840486A (en) | 2022-10-14 | 2022-10-14 | Curvature compensation band gap reference circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211261025.8A CN115840486A (en) | 2022-10-14 | 2022-10-14 | Curvature compensation band gap reference circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115840486A true CN115840486A (en) | 2023-03-24 |
Family
ID=85575836
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211261025.8A Pending CN115840486A (en) | 2022-10-14 | 2022-10-14 | Curvature compensation band gap reference circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115840486A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116954296A (en) * | 2023-08-14 | 2023-10-27 | 无锡盛景微电子股份有限公司 | Low-power-consumption self-bias second-order compensation band-gap reference circuit |
-
2022
- 2022-10-14 CN CN202211261025.8A patent/CN115840486A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116954296A (en) * | 2023-08-14 | 2023-10-27 | 无锡盛景微电子股份有限公司 | Low-power-consumption self-bias second-order compensation band-gap reference circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10599176B1 (en) | Bandgap reference circuit and high-order temperature compensation method | |
| CN106959723B (en) | A kind of bandgap voltage reference of wide input range high PSRR | |
| CN110362144B (en) | Low-temperature drift high-power-supply rejection-ratio band-gap reference circuit based on exponential compensation | |
| CN100514249C (en) | Band-gap reference source produce device | |
| CN103309392B (en) | A kind of second-order temperature compensate without amplifier whole CMOS reference voltage source | |
| CN112859996B (en) | Low-voltage high-precision band-gap reference circuit | |
| CN112987836B (en) | High-performance band-gap reference circuit | |
| JP2008108009A (en) | Reference voltage generation circuit | |
| CN104007777B (en) | A kind of current source generator | |
| CN108052150B (en) | Band-gap reference voltage source with high-order curvature compensation | |
| CN113377147B (en) | Sub-threshold band-gap reference voltage source circuit | |
| CN111781983A (en) | High power supply rejection ratio sub-threshold MOSFET compensation band-gap reference voltage circuit | |
| CN111045470B (en) | Band-gap reference circuit with low offset voltage and high power supply rejection ratio | |
| CN115877907A (en) | Band-gap reference source circuit | |
| CN114489221B (en) | Band-gap reference voltage source circuit and band-gap reference voltage source | |
| CN115840486A (en) | Curvature compensation band gap reference circuit | |
| CN109343641B (en) | High-precision current reference circuit | |
| CN111796625B (en) | Ultra-low power consumption CMOS voltage reference circuit | |
| CN116880644A (en) | High-order curvature temperature compensation band gap reference circuit | |
| CN219016862U (en) | Exponential temperature compensation band-gap reference circuit without operational amplifier | |
| CN111752325A (en) | High-precision linear voltage stabilizing circuit | |
| CN114995573B (en) | Low dropout regulator modified by feedback network | |
| CN216792774U (en) | Low-power-supply-voltage reference circuit with low temperature drift coefficient | |
| CN212484194U (en) | CMOS voltage reference source | |
| CN112256078B (en) | Positive temperature coefficient current source and zero temperature coefficient current source |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |