CN109521829B - Voltage reference source circuit with full temperature Duan Gaojie temperature compensation - Google Patents
Voltage reference source circuit with full temperature Duan Gaojie temperature compensation Download PDFInfo
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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Abstract
The invention provides a voltage reference source circuit with full temperature Duan Gaojie temperature compensation, which is characterized by comprising a PTAT generating circuit module, a nonlinear negative temperature coefficient current generating circuit module, a proportional superposition output circuit module, a bias circuit module, a high-temperature section temperature compensation circuit module and a low-temperature section temperature compensation circuit module.
Description
Technical Field
The invention relates to the field of power supplies, in particular to a voltage reference source circuit with full-temperature Duan Gaojie temperature compensation.
Background
In recent years, consumer electronic markets continue to expand, and the power supply field of integrated circuits is also expanding at a rapid speed, and with the higher and higher requirements of product performance, the performance requirements of power supply ICs are also more and more severe. The precision and stability of the reference voltage source of the core module directly determine the precision of the whole system, the performance of the reference voltage source needs to be further improved in order to better adapt to the development of analog and digital-analog hybrid circuits, a stable reference source with small fluctuation along with temperature change is provided for the whole circuit, but in the prior art, the lower temperature coefficient is difficult to reach by only performing first-order compensation on a common reference.
Disclosure of Invention
In order to solve the technical problems, the invention provides the following technical scheme:
a voltage reference source circuit with full temperature Duan Gaojie temperature compensation comprises a PTAT generating circuit module, a nonlinear negative temperature coefficient current generating circuit module, a proportional superposition output circuit module, a bias circuit module, a high-temperature section temperature compensation circuit module and a low-temperature section temperature compensation circuit module.
In a further aspect of the present invention,
the PTAT generation circuit module comprises a 1 st resistor R1, a 1 st P type MOS tube M1, a 2 nd P type MOS tube M2, a 1 st NPN type triode, a 2 nd NPN type triode, a 3 rd NPN type triode, a 4 th NPN type triode, a 6 th NPN type triode and a 7 th NPN type triode;
the collector of the 1 st NPN type triode, the emitter of the 3 rd NPN type triode are connected with the base of the 2 nd NPN type triode, the base of the 1 st NPN type triode is connected with the collector of the 2 nd NPN type triode and the emitter of the 4 th NPN type triode, the emitter of the 1 st NPN type triode is grounded, one end of the 1 st resistor R1 is connected with the emitter of the 2 nd NPN type triode and the other end of the 1 st resistor R1 is grounded, the base of the 3 rd NPN type triode is connected with the collector electrode of the 3 rd NPN type triode, the base of the 4 th NPN type triode and the emitter of the 6 th NPN type triode, the collector of the 4 th NPN type triode is connected with the base of the 6 th NPN type triode, the drain of the 1 st NPN type MOS tube M1, the base of the 7 th NPN type triode is connected with the grid electrode of the 2 nd MOS tube M2, the grid electrode of the 1 st NPN type MOS tube M1 is connected with the bias voltage VB1, and the 7 th NPN type triode is connected with the grid electrode of the 2P type MOS tube M2.
In a further aspect of the present invention,
the nonlinear negative temperature coefficient current generation circuit module comprises a 5 th NPN triode and a 2 nd resistor R2;
the base of the 5NPN type triode is connected with the base of the 4NPN type triode, the collector of the 5NPN type triode is connected with the collector of the 4NPN type triode, one end of the 2 nd resistor R2 is connected with the other end of the emitter of the 5NPN type triode and is grounded.
In a further aspect of the present invention,
the proportional superposition output circuit module consists of a 3P type MOS tube M3, an 8NPN type triode Q8, a 3 rd resistor R3, a 4 th resistor R4 and a 5 th resistor R5;
the grid electrode of the 3 rd P type MOS tube M3 is connected with the grid electrode of the 2 nd P type MOS tube M2, the source electrode of the 3 rd P type MOS tube M3 is connected with a power supply, the emitter electrode of the 8 th NPN type triode Q8 is grounded, the base electrode of the 8 th NPN type triode Q8 is connected with the collector electrode of the 8 th NPN type triode Q8 and one end of the 5 th resistor R5, the other end of the 5 th resistor R5 is connected with one end of the 4 th resistor R4, one end of the 4 th resistor R4 is connected with one end of the 3 rd resistor R3, and the other end of the 3 rd resistor R3 is connected with the drain end of the 3 rd P type MOS tube M3.
In a further aspect of the present invention,
the bias circuit module consists of a 4P type MOS tube M4, a 5P type MOS tube M5, a 6P type MOS tube M6, a 16P type MOS tube M16, a 9NPN type triode Q9, a 10NPN type triode Q10, an 11NPN type triode Q11, a 6 th resistor R6, a 7 th resistor R7, an 8 th resistor R8, a 9 th resistor R9, a 10 th resistor R10 and an operational amplifier AMP;
the base of the 9 th NPN type triode Q9 is connected with the base of the 3 rd NPN type triode Q3, the emitter of the 9 th NPN type triode Q9 is connected with the collector of the 10 th NPN type triode Q10, the base of the 10 th NPN type triode Q10 is connected with the base of the 2 nd NPN type triode Q2, the emitter of the 10 th NPN type triode Q10 is connected with one end of the 6 th resistor R6, the other end of the 6 th resistor R6 is grounded with the emitter of the 11 th NPN type triode Q11, the drain of the 4 th P type MOS tube M4 is connected with the grid of the 4 th P type MOS tube M4, the grid of the 6 th P type MOS tube M6 and the collector of the 9 th NPN type triode Q9, the source of the 4 th P type MOS tube M4 is connected with the source of the 5 th P type MOS tube M5, the source of the 6 th P type MOS tube M6 is connected with a power supply in parallel, the drain electrode of the 5 th P type MOS tube M5 is connected with the positive input end of the operational amplifier AMP and one end of a 7 th resistor R7, the other end of the 7 th resistor R7 is connected with the collector electrode of an 11 th NPN type triode Q11 and the base electrode of the 11 th NPN type triode Q11, the drain electrode of the 6 th P type MOS tube M6 is connected with the source electrode of the 16 th P type MOS tube M16, the grid electrode of the 16 th P type MOS tube M16 is connected with the output end of the operational amplifier AMP, the drain electrode of the 16 th P type MOS tube M16 is connected with the negative input end of the operational amplifier AMP and one end of an 8 th resistor R8, and the two ends of the 9 th resistor R9 are respectively connected with an 8 th resistor R8 and a 10 th resistor R10.
In a further aspect of the present invention,
the high-temperature section temperature compensation circuit module comprises a 7P type MOS tube M7, an 8P type MOS tube M8, a 9P type MOS tube M9, a 13N type MOS tube M13 and a 14N type MOS tube M13, and the low-temperature section temperature compensation circuit module comprises a 10P type MOS tube M10, an 11P type MOS tube M11 and a 12P type MOS tube M12;
the grid electrode of the 7 th P type MOS tube M7 is connected with the grid electrode of the 6 th P type MOS tube M6 and the grid electrode of the 10 th P type MOS tube M10, the source electrode of the 7 th P type MOS tube M7 is connected with the source electrode of the 8 th P type MOS tube M8 and the source electrode of the 9 th P type MOS tube M9, the drain electrode of the 8 th P type MOS tube M8 is connected with the drain electrode of the 12 th P type MOS tube M12, the grid electrode of the 15 th N type MOS tube M15 and the drain electrode of the 15 th N type MOS tube M15, the drain electrode of the 9 th P type MOS tube M9 is connected with the drain electrode of the 13 th N type MOS tube M13, the grid electrode of the 13 th N type MOS tube M13 and the grid electrode of the 14 th N type MOS tube M14, the source electrode of the 13 th N type MOS tube M13 is connected with the source electrode of the 14 th N type MOS tube M14, the source electrode of the 15 th N type MOS tube M15 is connected with the ground, and the drain electrode of the 10 th P type MOS tube M10 is connected with the drain electrode of the 12 th P type MOS tube M12 and the drain electrode of the 11 th P type MOS tube M11.
The beneficial effects of adopting above-mentioned technical scheme are:
the reference voltage source provided by the invention compensates the reference by adopting a temperature compensation mode of various modes, so that the temperature coefficient of the output voltage is effectively reduced, the stability of the reference voltage is improved, and an accurate reference voltage source is provided for a high-precision circuit.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a full temperature Duan Gaojie compensated reference voltage source of the present invention;
FIG. 2 is a temperature characteristic of the reference voltage VREF1 after first-order compensation;
FIG. 3 is a temperature characteristic curve of the reference voltage VREF2 after the middle temperature Duan Gaojie compensation;
FIG. 4 is a graph showing the temperature characteristic of the reference voltage VREF after the compensation of the superimposed high and low temperature sections;
Detailed Description
As shown in fig. 1, the full-temperature-range high-order compensation reference source according to the present invention includes a conventional first-order temperature compensation, a medium-temperature Duan Gaojie temperature compensation, a high-temperature-section temperature compensation, and a low-temperature-section temperature compensation, where the circuit of fig. 1 is divided into 4 parts, i.e., a first-order temperature compensation circuit, a medium-temperature-section temperature compensation circuit, a bias voltage generating circuit, and a high-temperature-low-temperature compensation circuit, and these 4 parts are respectively described in the following analysis.
The first-order temperature compensation circuit comprises NPN type triodes Q1, Q2, Q3, Q4, Q6, Q7 and Q8, P type MOS tubes M1, M2 and M3, and resistors R1, R3, R4 and R5. The grid electrode of the P-type MOS transistor M1 is connected with a bias voltage VB1, the area of the NPN-type triode Q2 is n times that of the NPN-type triode Q4, and the area of the NPN-type triode Q1 is equal to that of the triode Q3.
NPN type triodes Q1, Q2, Q3 and Q4 and a resistor R1 generate IPTAT current I3, wherein the IPTAT current is as follows:p-type MOS tube M3 and PMOS tube M2 are connected into 1: m times of current mirror form, the mirror current of M3 branch is M x I3. Taking the collector voltage of the NPN triode Q8 as VBE8, R=R3+R4+R5, the voltage obtained by first-order temperature compensation is as follows: />The temperature characteristic curve after first-order compensation is shown in fig. 2, and shows a concave trend, VBE is a complex function related to temperature, and the temperature coefficient of VBE is not linear but is in a curve form characterized by a polynomial.
The complete expression vbe=vg0+vtln (EG) -VT (γ - α) lnT of the triode base emitter voltage VBE, where VG0 is the bandgap voltage of silicon, E, G is a temperature independent parameter, α is the coefficient of collector current variation with temperature, γ is the coefficient of mobility variation with temperature, and VTln contains the higher order nonlinear quantity of VBE versus temperature. The first-order temperature compensation only counteracts the first-order term in the expression, so that the higher-order term in the bandgap reference voltage cannot be compensated by the conventional linear compensation, and the nonlinear compensation of the reference voltage needs to be performed by introducing nonlinear quantity to further improve the temperature stability of the reference voltage.
The intermediate temperature Duan Gaojie compensation part in the invention adds a branch circuit comprising a triode Q5 and a resistor R2 on a first-order compensation circuit, so that the branch circuit generates a nonlinear negative temperature coefficient current I4. I4 =inl= (vbe3+vbe4-vbe5)/R2, where INL represents a nonlinear current with temperature change. The conditions for generating the nonlinear temperature coefficient current are as follows: reasonable operating points are set to enable the triode Q5 to operate at the edge of a saturation region. The amplification factor of an NPN transistor is not constant as is known from the characteristics of a transistor, and its value depends on the operating conditions of the transistor. When triode NPN works at saturationWhen the temperature is changed, the amplification factor of the temperature-sensitive material shows nonlinear change along with the change of the temperature. The generated current I4, i.e. INL is superimposed on the IPTAT current I3 and is superimposed on the branch where VREF is located through the mirror images of the PMOS tubes M2 and M3, and the first-order reference output voltage VFEF1 is compensated in a high order. The reference output voltage VREF2, to which the nonlinear current INL compensation is introduced, is: VREF2 = V BE 8+IPTAT×R+I NL X R. The reference output voltage VREF2 has a temperature characteristic varying with temperature as shown in fig. 3, and the temperature characteristic curve of vref2 has a sinusoidal-like trend.
The bias circuit portion of the present circuit is used to generate a temperature independent bias voltage. As shown in fig. 1, the P-type MOS transistors M5, M4, M6 are mirror transistors, the branch where the P-type MOS transistor M4 is located generates an IPTAT current, and a first-order voltage independent of temperature is generated as a positive input voltage of the operational amplifier AMP by overlapping the mirror image of the P-type MOS transistor M5 on the NPN transistor Q11 and the resistor R7. The negative input voltage of the operational amplifier AMP follows the positive input voltage to generate a first-order temperature-independent voltage value, and the voltage division of the resistors R8, R9, R10 generates first-order temperature-independent bias voltages Va and Vb. The bias circuit provides bias voltage for the high-low temperature section temperature compensation circuit.
The high-temperature section temperature compensation and low-temperature section temperature compensation part for the reference comprises P-type MOS transistors M7, M10, M8, M9, M11 and M12 and N-type MOS transistors M13, M14 and M15. The P-type MOS tube M8 is connected with bias voltage Vb, the P-type MOS tube M11 is connected with bias voltage Va, and the P-type MOS tube M9 and the P-type MOS tube M12 are connected with common bias voltage VB2 with negative temperature coefficient. The N-type MOS transistors M13 and M14 are current mirrors for mirroring the current generated by the P-type MOS transistor M9. By utilizing the characteristics, reasonable bias voltage is set, so that the P-type MOS transistors M9 and M11 work in a subthreshold region, and the function of the circuit is to generate low-temperature compensation current I1 and high-temperature compensation current I2.
The mechanism for realizing the high-order compensation with the reference temperature characteristic by utilizing the subthreshold region of the MOS tube is as follows: MOS transistor subthreshold region current expression working in subthreshold regionCan obtain MOS drain biased in subthreshold regionThe pole current ID is exponentially related to the variation law of VGS. In the invention, the current of the branch circuit where the PMOS tubes M7 and M10 are positioned has positive linear relation with temperature, the MOS tubes M9 and M12 are connected with bias voltages VB2 which have negative linear relation with temperature, and Va and VB are voltages which are not related with temperature. Vb (Vb)<VB2<Va, the P-type MOS tube M12 works in a saturation region, the P-type MOS tube M11 works in a critical point of a subthreshold region and a cut-off region, VB2 further decreases along with the temperature rise in a high-temperature section, the gate-source voltage VGS of the P-type MOS tube M11 linearly increases, and the current flowing through the P-type MOS tube M11 is exponentially increased along with the temperature reduction. The P-type MOS tube M8 works in a saturation region, the P-type MOS tube M9 works in a critical point of a subthreshold region and a cut-off region, VB2 becomes smaller along with temperature rise in a low-temperature section, the gate-source voltage VGS of the P-type MOS tube M9 linearly decreases, and then the current flowing through the PMOS tube M9 is shown to become exponentially larger along with the temperature rise.
Through the analysis, with reference to fig. 3, the current I1 realizes temperature compensation of the low-temperature Duan Jizhun voltage, and the current I2 realizes temperature compensation of the high-temperature section reference voltage. The low-temperature section compensation current I1 is connected between the reference output branch resistors R3 and R4 through the port IIN1, and the high-temperature section compensation current I2 is connected between the reference output branch resistors R4 and R5 through the port IIN 2. Both currents I1 and I2 are superimposed on the reference output circuit, and the output voltage vref=vref+i1× (r4+r5) +i2×r5. The final reference voltage temperature characteristic curve obtained by various compensation modes is shown in figure 4. The temperature characteristic curve of the final reference output voltage VREF can be well compensated in each temperature segment.
Although the invention has been described hereinabove with reference to certain embodiments, various modifications can be made and equivalents can be substituted for elements thereof without departing from the scope of the invention, and in particular, the features of the various embodiments missed by the present invention can be used in any combination, provided that there is no technical conflict, and the lack of description of such combinations in this invention is merely for the sake of brevity and economy of resources. Therefore, it is intended that the invention not be limited to the particular embodiments disclosed herein, but that the invention will include the claims appended hereto.
Claims (1)
1. The voltage reference source circuit with the full temperature Duan Gaojie temperature compensation is characterized by comprising a PTAT generating circuit module, a nonlinear negative temperature coefficient current generating circuit module, a proportional superposition output circuit module, a bias circuit module, a high-temperature section temperature compensation circuit module and a low-temperature section temperature compensation circuit module;
the PTAT generating circuit module comprises a 1 st resistor R1, a 1 st P th MOS transistor M1, a 2 nd P-type MOS transistor M2, a 1 st NPN type triode, a 2 nd NPN type triode, a 3 rd NPN type triode, a 4 th NPN type triode, a 6 th NPN type triode and a 7 th NPN type triode, wherein the collector of the 1 st NPN type triode and the emitter of the 3 rd NPN type triode are connected with the base of the 2 nd NPN type triode, the base of the 1 st NPN type triode is connected with the collector of the 2 nd NPN type triode and the emitter of the 4 th NPN type triode, the emitter of the 1 st NPN type triode is grounded, one end of the 1 st resistor R1 is connected with the other end of the emitter of the 2 nd NPN type triode, the base electrode of the 3NPN type triode is connected with the collector electrode of the 3NPN type triode, the base electrode of the 4NPN type triode and the emitter electrode of the 6NPN type triode, the collector electrode of the 4NPN type triode is connected with the emitter electrode of the 7NPN type triode, the collector electrode of the 6NPN type triode is connected with the base electrode of the 6NPN type triode, the drain electrode of the 1P type MOS tube M1 and the base electrode of the 7NPN type triode, the grid electrode of the 1P type MOS tube M1 is connected with the bias voltage VB1, and the collector electrode of the 7NPN type triode is connected with the drain electrode of the 2P type MOS tube M2 and the grid electrode of the 2P type MOS tube M2;
the nonlinear negative temperature coefficient current generation circuit module comprises a 5 th NPN triode and a 2 nd resistor R2; the base electrode of the 5NPN type triode is connected with the base electrode of the 4NPN type triode, the collector electrode of the 5NPN type triode is connected with the collector electrode of the 4NPN type triode, and one end of the 2 nd resistor R2 is connected with the other end of the emitter electrode of the 5NPN type triode and grounded;
the proportional superposition output circuit module consists of a 3 rd P th MOS tube M3, an 8 th NPN triode Q8, a 3 rd resistor R3, a 4 th resistor R4 and a 5 th resistor R5; the grid electrode of the 3P type MOS tube M3 is connected with the grid electrode of the 2 nd P type MOS tube M2, the source electrode of the 3 rd P type MOS tube M3 is connected with a power supply, the emitter electrode of the 8 th NPN type triode Q8 is grounded, the base electrode of the 8 th NPN type triode Q8 is connected with the collector electrode of the 8 th NPN type triode Q8 and one end of the 5 th resistor R5, the other end of the 5 th resistor R5 is connected with one end of the 4 th resistor R4, the other end of the 4 th resistor R4 is connected with one end of the 3 rd resistor R3, and the other end of the 3 rd resistor R3 is connected with the drain electrode of the 3 rd P type MOS tube M3;
the bias circuit module is composed of a 4 th P type MOS tube M4, a 5 th P type MOS tube M5, a 6 th P type MOS tube M6, a 16 th P type MOS tube M16, a 9 th NPN type triode Q9, a 10 th NPN type triode Q10, an 11 th NPN type triode Q11, a 6 th resistor R6, a 7 th resistor R7, an 8 th resistor R8, a 9 th resistor R9, a 10 th resistor R10 and an operational amplifier AMP; the base of the 9NPN type triode Q9 is connected with the base of the 3NPN type triode Q3, the emitter of the 9NPN type triode Q9 is connected with the collector of the 10NPN type triode Q10, the base of the 10NPN type triode Q10 is connected with the base of the 2NPN type triode Q2, the emitter of the 10NPN type triode Q10 is connected with one end of the 6 th resistor R6, the other end of the 6 th resistor R6 is grounded with the emitter of the 11 th NPN type triode Q11, the drain of the 4P type MOS tube M4 is connected with the grid of the 4 th P type MOS tube M4, the grid of the 6 th P type MOS tube M6 and the collector of the 9NPN type triode Q9, the source of the 4P type MOS tube M4 is connected with the source of the 5 th P type MOS tube M5 and the source of the 6 th P type MOS tube M6 and is connected with a power supply in parallel, the drain electrode of the 5 th P type MOS tube M5 is connected with the positive input end of the operational amplifier AMP and one end of a 7 th resistor R7, the other end of the 7 th resistor R7 is connected with the collector electrode of the 11 th NPN type triode Q11 and the base electrode of the 11 th NPN type triode Q11, the drain electrode of the 6 th P type MOS tube M6 is connected with the source electrode of the 16 th P type MOS tube M16, the grid electrode of the 16 th P type MOS tube M16 is connected with the output end of the operational amplifier AMP, the drain electrode of the 16 th P type MOS tube M16 is connected with the negative input end of the operational amplifier AMP and one end of an 8 th resistor R8, the other end of the 8 th resistor R8 is connected with one end of a 9 th resistor R9, the other end of the 9 th resistor R9 is connected with one end of a 10 th resistor R10, and the other end of the 10 th resistor R10 is grounded;
the high-temperature-section temperature compensation circuit module comprises a 7 th P type MOS tube M7, an 8 th P type MOS tube M8, a 9 th P type MOS tube M9, a 13 th N type MOS tube M13 and a 14 th N type MOS tube M14, and the low-temperature-section temperature compensation circuit module comprises a 10 th P type MOS tube M10, a 11 th P type MOS tube M11 and a 12 th P type MOS tube M12; the gate of the 7 th P type MOS tube M7 is connected with the gate of the 6 th P type MOS tube M6 and the gate of the 10 th P type MOS tube M10, the source of the 7 th P type MOS tube M7 is connected with the power supply, the drain of the 7 th P type MOS tube M7 is connected with the source of the 8 th P type MOS tube M8 and the source of the 9 th P type MOS tube M9, the drain of the 8 th P type MOS tube M8 is connected with the drain of the 12 th P type MOS tube M12, the gate of the 15 th N type MOS tube M15 and the drain of the 15 th N type MOS tube M15, the drain of the 9 th P type MOS tube M9 is connected with the drain of the 13 th N type MOS tube M13, the gate of the 13 th N type MOS tube M13 and the gate of the 14 th N type MOS tube M14, the source of the 13 th N type MOS tube M13 is connected with the source of the 14 th 5228 type MOS tube M14, the 15 type MOS tube M15 is connected with the ground of the 15 th MOS tube M35 type MOS tube M12, and the drain of the 10 th MOS tube M35 is connected with the drain of the 35 type MOS tube M12.
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| CN110187166B (en) * | 2019-06-26 | 2024-06-28 | 成都芯进电子有限公司 | Current sensor temperature compensation circuit for low-temperature drift |
| CN111427410B (en) * | 2020-04-22 | 2022-05-20 | 中国科学院微电子研究所 | Band gap reference circuit |
| CN114237339A (en) * | 2021-12-01 | 2022-03-25 | 重庆吉芯科技有限公司 | Band-gap reference voltage circuit and compensation method of band-gap reference voltage |
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