CN115357087B - Band gap reference circuit - Google Patents
Band gap reference circuit Download PDFInfo
- Publication number
- CN115357087B CN115357087B CN202211173768.XA CN202211173768A CN115357087B CN 115357087 B CN115357087 B CN 115357087B CN 202211173768 A CN202211173768 A CN 202211173768A CN 115357087 B CN115357087 B CN 115357087B
- Authority
- CN
- China
- Prior art keywords
- resistor
- current
- voltage
- bipolar transistor
- temperature coefficient
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 49
- 238000003786 synthesis reaction Methods 0.000 claims abstract description 49
- 238000001914 filtration Methods 0.000 claims abstract description 6
- 230000002194 synthesizing effect Effects 0.000 claims abstract description 5
- 239000011159 matrix material Substances 0.000 claims description 29
- 239000003990 capacitor Substances 0.000 claims description 19
- 238000006243 chemical reaction Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Amplifiers (AREA)
Abstract
The invention provides a band gap reference circuit, which comprises a dynamic matching current source, a zero temperature coefficient current synthesis circuit, a high-order curvature compensation circuit, a chopper operational amplifier, a notch filter and an output circuit, wherein the dynamic matching current source is used for periodically providing current for the zero temperature coefficient current synthesis circuit, the high-order curvature compensation circuit and the output circuit; the zero temperature coefficient current synthesis circuit is used for synthesizing zero temperature coefficient current and inputting the zero temperature coefficient current into the chopper operational amplifier; the high-order curvature compensation circuit is used for providing compensation current for the zero temperature coefficient current synthesis circuit; the chopper operational amplifier is used for detecting the voltage difference in the zero temperature coefficient current synthesis circuit; the notch filter is used for filtering jitter at the output end of the chopper operational amplifier; the output circuit realizes the conversion from current to voltage and outputs a reference voltage. The invention can eliminate various non-ideal mismatch in the reference circuit and realize the reference voltage output with high precision, low noise and low temperature coefficient.
Description
Technical Field
The invention belongs to the field of analog integrated circuits, and particularly relates to a band gap reference circuit.
Background
Bandgap reference circuits are widely used in a variety of analog circuits to provide a reference voltage that does not vary with temperature. The bandgap reference circuit can provide a reference voltage for the analog-to-digital converter, and can further generate a reference current to provide bias current for other analog circuits. The performance of the band gap reference circuit directly influences the precision of the analog-to-digital converter and the working state of other analog circuit modules, and is particularly important in the field of high-precision metering and monitoring, such as metering chips in the electric power field, sensor chips in the biomedical field and the like, and the band gap reference circuit with high precision, low noise and low temperature coefficient. To achieve good temperature performance, the bandgap reference circuit requires high order temperature compensation. The existing high-order temperature compensation scheme is realized by adopting resistors with different temperature coefficients, but good matching of the resistors with different types is difficult to realize; and secondly, the reference voltage is realized by adopting bipolar transistors biased at currents with different temperature coefficients, but the mismatch of the currents and the bipolar transistors can affect the temperature performance of the reference voltage.
Disclosure of Invention
The invention aims to: the invention aims to overcome at least one problem in the prior art and provides a band gap reference circuit with high precision, low noise and low temperature coefficient.
In order to achieve the above object, the present invention provides a bandgap reference circuit, including a dynamically matched current source, a zero temperature coefficient current synthesis circuit, a higher order curvature compensation circuit, a chopper operational amplifier, a notch filter, and an output circuit, where the dynamically matched current source is configured to periodically provide a first current, a second current, and a third current, the first current is an input of the zero temperature coefficient current synthesis circuit, the second current is an input of the higher order curvature compensation circuit, and the third current is an input of the output circuit;
the zero temperature coefficient current synthesis circuit is used for generating negative temperature coefficient current and positive temperature coefficient current, synthesizing the negative temperature coefficient current and the positive temperature coefficient current into zero temperature coefficient current, and inputting the voltage of the current synthesis point into the chopper operational amplifier;
the high-order curvature compensation circuit is used for providing compensation current for the zero temperature coefficient current synthesis circuit so as to compensate the high-order temperature characteristic of the zero temperature coefficient current;
the chopper operational amplifier is used for detecting the voltage difference in the zero temperature coefficient current synthesis circuit, eliminating the mismatch of differential input of the operational amplifier and reducing the flicker noise of an MOS tube in the operational amplifier, and the output end is connected with the input end of the notch filter;
the notch filter is used for filtering jitter at the output end of the chopper operational amplifier, and the output end is connected with the dynamic matching current source;
the output circuit is used for converting the third current into a reference voltage.
Further, the dynamic matching current sources comprise more than three groups of common-source and common-gate current sources, wherein the drains of the common-source tubes are connected to the sources of the corresponding common-gate tubes through a first dynamic matching switch matrix, the sources of all the common-source tubes are connected to a power supply VDD, and the gates of all the common-source tubes are connected to the output end of the notch filter; the grid electrodes of all the common grid tubes are connected to the same bias voltage VBP, and the drain electrodes respectively and periodically output a first current, a second current and a third current. The first dynamic matching switch matrix realizes the rotation of all common source tubes, and can eliminate the mismatch between current sources and reduce flicker noise. The traditional dynamic matching cascode current source places the switch matrix at the drain of the cascode tube to realize the integral rotation of the cascode current source of each branch. In the bandgap reference circuit, in order to save power consumption, each branch circuit adopts smaller current, and the resistances of the first resistor R1, the second resistor R2 and the eighth resistor Ro are larger, the drain impedance of the common-gate tube of the common-source common-gate current source is also larger, the drain of the common-gate tube is similar to a high-resistance point, and if the dynamic matching switch matrix is placed in the drain, the clock signal of the switch matrix easily causes crosstalk to the high-resistance point, so that larger burrs are caused, and the accuracy of output voltage is affected. According to the invention, the first dynamic matching switch matrix is arranged between the drain electrode of the common source tube and the source electrode of the common grid tube, and the source electrode impedance of the common grid tube is far smaller than the drain electrode impedance, so that the crosstalk of the first dynamic matching switch matrix to the node is small, burrs caused by rotation of the common source tube are also small, and the accuracy of output voltage is improved.
Further, the zero temperature coefficient current synthesis circuit comprises two paths, one path comprises a first resistor R1, a third resistor R3, a sixth resistor R6 and a first bipolar transistor Q1, and the other path comprises a second resistor R2, a seventh resistor R7 and a second bipolar transistor Q2; the voltage at the input end of the zero temperature coefficient current synthesis circuit is recorded as a first voltage VD, one end of a sixth resistor R6 and one end of a seventh resistor R7 are connected to the first voltage VD, the other end of the sixth resistor R6 and the seventh resistor R7 are respectively connected to the positive input end and the negative input end of the chopper operational amplifier, and the corresponding voltages are respectively recorded as a second voltage VX and a third voltage VY;
one end of the first resistor R1 is connected to the second voltage VX, and the other end of the first resistor R1 is grounded; one end of the second resistor R2 is connected to the third voltage VY, and the other end of the second resistor R2 is grounded; one end of the resistor R3 is connected to the second voltage VX, the other end of the resistor R3 is connected to the emitter of the first bipolar transistor Q1 through a second dynamic matching switch matrix, and the base electrode and the collector electrode of the first bipolar transistor Q1 are grounded; the third voltage VY is connected to the second bipolar transistor Q2 through a second dynamic matching switch matrix, and both the base and collector of the second bipolar transistor Q2 are grounded.
Further, the resistance values of the first resistor R1 and the second resistor R2 are the same, and the resistance value of the sixth resistor R6 and the seventh resistor R7 are the same; the second bipolar transistor Q2 comprises a unit bipolar transistor, the first bipolar transistor Q1 is formed by connecting N unit bipolar transistors in parallel, N represents the size ratio of the first bipolar transistor Q1 to the second bipolar transistor Q2, and N is more than or equal to 1;
the chopper operational amplifier, the notch filter, the cascode current source connected with the zero temperature coefficient current synthesis circuit in the dynamic matching current source and the zero temperature coefficient current synthesis circuit form a negative feedback loop together, so that the second voltage VX=the third voltage VY;
the resistance values of the first resistor R1, the second resistor R2 and the third resistor R3, and the size ratio N of the first bipolar transistor Q1 to the second bipolar transistor Q2 satisfy the following formula:
(1+R1/R3)*lnN＝17.2
since the first resistor R1 is connected between the second voltage VX and ground, the second resistor R2 is connected between the third voltage VY and ground, and the resistances of the first resistor R1 and the second resistor R2 are the same, so that the currents of the first resistor R1 and the second resistor R2 are the same, the currents of the first bipolar transistor Q1 and the second bipolar transistor Q2 are the same, and the currents of the sixth resistor R6 and the seventh resistor R7 are the same.
The difference between the collector voltages |vbe1| and |vbe2| of the first bipolar transistor Q1 and the second bipolar transistor Q2 is the voltage across the third resistor R3, which exhibits a positive temperature coefficient, such that the current of the third resistor R3 exhibits a positive temperature coefficient. The collector voltage |vbe2| of the second bipolar transistor Q2 is a negative temperature coefficient, and |vbe2|=vy, so that the currents of the first resistor R1 and the second resistor R2 are negative temperature coefficients. The current of the sixth resistor R6 is the sum of the current of the first resistor R1 and the current of the third resistor R3, i.e. the sum of the negative temperature coefficient current and the positive temperature coefficient current. At this time, the current of the sixth resistor R6 is zero temperature coefficient current.
Thus, the currents of the first bipolar transistor Q1 and the second bipolar transistor Q2 have positive temperature coefficients, the currents of the first resistor R1 and the second resistor R2 have negative temperature coefficients, and the currents of the sixth resistor R6 and the seventh resistor R7 have zero temperature coefficients.
Further, the high-order curvature compensation circuit comprises a fourth resistor R4, a fifth resistor R5 and a third bipolar transistor Q3, wherein a second current is respectively input to the fourth resistor R4, the fifth resistor R5 and the third bipolar transistor Q3, the voltage at the input end of the high-order curvature compensation circuit is recorded as a fourth voltage VZ, one ends of the fourth resistor R4 and the fifth resistor R5 are both connected to the fourth voltage VZ, and are also connected to the emitter of the third bipolar transistor Q3 through a second dynamic matching switch matrix, and the other ends of the fourth resistor R4 and the fifth resistor R5 are respectively connected to a third voltage VY and a second voltage VX; the third bipolar transistor Q3 is biased at zero temperature coefficient current, and the base electrode and the collector electrode of the third bipolar transistor Q3 are grounded; the third bipolar transistor Q3 comprises M unit bipolar transistors connected in parallel, wherein M represents the size ratio of the third bipolar transistor Q3 to the second bipolar transistor Q2, and M is more than or equal to 1. The high-order curvature compensation circuit provides a tiny current for the zero temperature coefficient current synthesis circuit so as to compensate the high-order curvature of the zero temperature coefficient current. The compensation of the high-order temperature characteristic of the zero temperature coefficient current is realized by utilizing the base emitter voltage |VBE3| of the third bipolar transistor Q3 biased at the zero temperature coefficient, and the temperature coefficient of the zero temperature coefficient current is further reduced.
Further, L groups of cascode current sources are connected to a zero temperature coefficient current synthesis circuit, J groups of cascode current sources are connected to a high-order curvature compensation circuit, K groups of cascode current sources are connected to an output circuit, wherein L is more than or equal to 1, K is more than or equal to 1,1 is less than or equal to J < L, namely, a first current comprises L paths, a second current comprises J paths, a third current comprises K paths, a first dynamic matching switch matrix comprises L+J+K paths, and rotation of all the cascode tubes is periodically realized;
the second dynamic matching switch matrix comprises N+1+M paths, each path is connected with a unit bipolar transistor, and rotation of each unit bipolar transistor is periodically realized.
The bipolar transistors in the zero temperature coefficient current synthesis circuit and the high-order curvature compensation circuit are dynamic matched bipolar transistors, the second dynamic matched switch matrix is used for realizing rotation of the bipolar transistors of each unit uniformly, and mismatch among the first bipolar transistor Q1, the second bipolar transistor Q2 and the third bipolar transistor Q3 is eliminated. The bipolar transistor in the high-order curvature compensation circuit is biased at zero temperature coefficient current, and high-order nonlinearity of the negative temperature coefficient current in the zero temperature coefficient current synthesis circuit is compensated. The amount of high-order nonlinearity is much smaller than the amount of linearity, so that the high-order nonlinearity has high matching requirements on the bipolar transistor in the high-order curvature compensation circuit and the bipolar transistor in the zero temperature coefficient current synthesis circuit. The bipolar transistor in the high-order curvature compensation circuit and the bipolar transistor in the zero temperature coefficient current synthesis circuit are rotated together, meanwhile, the matching performance among the first bipolar transistor Q1, the second bipolar transistor Q2 and the third bipolar transistor Q3 is guaranteed, and more ideal zero temperature coefficient reference voltage output is achieved.
Further, the output circuit includes an eighth resistor Ro and a filter capacitor Co, and records the output voltage as VREF, that is, a reference voltage value, the third current is input to the eighth resistor Ro and the filter capacitor Co respectively, one end of the eighth resistor Ro and one end of the filter capacitor Co are both connected to the output voltage VREF, and the other end is grounded, and the output circuit can realize the conversion from current to voltage and simultaneously provides the filter function; the output voltage VREF is expressed as:
VREF＝(2K/L)*(Ro/R1)*[|VBE2|+(R1/R3)*V T *lnN]
wherein V is T Is thermal voltage, i.e. V T =kt/q, k is boltzmann constant, T is kelvin temperature, q is electron charge.
Appropriate values for K, L and Ro/R1 may be selected based on the desired reference voltage values.
Further, the band gap reference circuit further comprises a miller compensation circuit, wherein the miller compensation circuit is used for compensating the phase margin of the negative feedback loop and comprises a first capacitor Cm and a ninth resistor Rm, one end of the first capacitor Cm is connected with the output end of the notch filter, and the other end of the first capacitor Cm is connected with one end of the ninth resistor Rm; the other end of the ninth resistor Rm is connected with the input end of the zero temperature coefficient current synthesis circuit.
Further, the sixth resistor R6 and the seventh resistor R7 are formed by connecting more than two unit resistors in series and parallel, so as to achieve good matching performance.
Further, the chopping operational amplifier comprises a first chopper CHOP1, a second chopper CHOP2, a seventh PMOS tube and a fourteenth PMOS tube: m7, M8, M9, M10, M11, M12, M13, M14, and first to fourth NMOS transistors: m15, M16, M17, M18, the positive input of the chopper operational amplifier being connected to the positive input of the first chopper CHOP1, the negative input of the chopper operational amplifier being connected to the negative input of the first chopper CHOP 1; the positive output end of the CHOP1 is connected to the grid electrode of the ninth PMOS tube M9, and the negative output end of the first chopper CHOP1 is connected to the grid electrode of the tenth PMOS tube M10; the source electrode of the ninth PMOS tube M9 and the source electrode of the tenth PMOS tube M10 are connected to the drain electrode of the eighth PMOS tube M8; the source electrode of the eighth PMOS tube M8 is connected to the drain electrode of the seventh PMOS tube M7, and the grid electrode is connected to the fifth voltage VP2; the grid electrode of the seventh PMOS tube M7 is connected to the sixth voltage VP1, and the source electrode is connected with a power supply; the drain electrode of the ninth PMOS tube M9 is connected to the drain electrode of the third NMOS tube M17 and the source electrode of the first NMOS tube M15, and the drain electrode of the tenth PMOS tube M10 is connected to the drain electrode of the fourth NMOS tube M18 and the source electrode of the second NMOS tube M16; the sources of the third NMOS tube M17 and the fourth NMOS tube M18 are grounded, and the gates are connected to the seventh voltage VN1; the gates of the first NMOS tube M15 and the second NMOS tube M16 are connected to an eighth voltage VN2; the drain electrode of the first NMOS tube M15 is connected to the drain electrode of the thirteenth PMOS tube M13 and the positive input end of the second chopper CHOP 2; the drain electrode of the second NMOSM16 is connected to the drain electrode of the fourteenth PMOS tube M14 and the negative input end of the second chopper CHOP 2; the grid electrodes of the thirteenth PMOS tube M13 and the fourteenth PMOS tube M14 are connected to the fifth voltage VP2, the source electrode of the thirteenth PMOS tube M13 is connected to the drain electrode of the eleventh PMOS tube M11, and the source electrode of the fourteenth PMOS tube M14 is connected to the drain electrode of the twelfth PMOS tube M12; the sources of the eleventh PMOS tube M11 and the twelfth PMOS tube M12 are connected with power sources, the grid electrodes are connected to the positive output end of the second chopper CHOP2, and the negative output end of the second chopper CHOP2 is the output end of the chopping operational amplifier.
The beneficial effects are that: the band gap reference circuit realizes high-order temperature compensation of reference output voltage, can eliminate various non-ideal mismatch in the reference circuit, has flexible and configurable output voltage value, and realizes high-precision, low-noise and low-temperature coefficient reference voltage output.
Drawings
The foregoing and/or other advantages of the invention will become more apparent from the following detailed description of the invention when taken in conjunction with the accompanying drawings and detailed description.
Fig. 1 is a block diagram of a bandgap reference circuit provided in an embodiment of the present application.
Fig. 2 is a detailed structural diagram of a bandgap reference circuit provided in an embodiment of the present application.
Fig. 3 is a block diagram of a chopper operational amplifier provided in an embodiment of the present application.
Fig. 4 is a block diagram of a dynamically matched switch matrix provided in an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The band gap reference circuit provided by the embodiment of the application can be applied to the field of high-precision metering monitoring, such as a metering chip applied to the electric power field, a sensor chip applied to the biomedical field and the like.
As shown in fig. 1, the present embodiment provides a bandgap reference circuit for implementing high-order temperature compensation, which includes a dynamically matched current source, a zero temperature coefficient current synthesis circuit, a high-order curvature compensation circuit, a chopper operational amplifier, a notch filter, a miller compensation circuit, and an output circuit, where the dynamically matched current source is configured to periodically provide a first current, a second current, and a third current, the first current is an input of the zero temperature coefficient current synthesis circuit, the second current is an input of the high-order curvature compensation circuit, and the third current is an input of the output circuit;
the zero temperature coefficient current synthesis circuit is used for generating negative temperature coefficient current and positive temperature coefficient current, synthesizing the negative temperature coefficient current and the positive temperature coefficient current into zero temperature coefficient current, and inputting the voltage of the current synthesis point into the chopper operational amplifier;
the high-order curvature compensation circuit is used for providing compensation current for the zero temperature coefficient current synthesis circuit so as to compensate the high-order temperature characteristic of the zero temperature coefficient current;
the chopper operational amplifier is used for detecting the voltage difference in the zero temperature coefficient current synthesis circuit, eliminating the mismatch of differential input of the operational amplifier and reducing the flicker noise of an MOS tube in the operational amplifier, and the output end is connected with the input end of the notch filter;
the notch filter is used for filtering jitter at the output end of the chopper operational amplifier, and the output end is connected with the dynamic matching current source;
the miller compensation circuit is used for compensating the phase margin of the negative feedback loop;
the output circuit is used for converting the third current into a reference voltage.
The bipolar transistors in the zero temperature coefficient current synthesis circuit and the high-order curvature compensation circuit are dynamic matched bipolar transistors. The dynamic matching current sources can eliminate mismatch among the current sources and reduce flicker noise; dynamically matching bipolar transistors eliminates mismatch between bipolar transistors; the zero temperature coefficient current synthesis circuit forms zero temperature coefficient current by using a resistor matched with the base emitter voltage of the bipolar transistor; the high-order curvature compensation circuit compensates for the high-order temperature characteristic of the band-gap reference voltage, and further reduces the temperature coefficient of the output reference voltage; the chopper operational amplifier can eliminate mismatch of differential input of the operational amplifier and reduce flicker noise of MOS tubes in the operational amplifier; the output circuit is composed of a resistor and a filter capacitor, realizes conversion from current to voltage, and outputs reference voltage. The embodiment can eliminate various non-ideal mismatch in the reference circuit and realize high-precision, low-noise and low-temperature coefficient reference voltage output.
As shown in fig. 2, in an embodiment of the present invention, a dynamic matching current source provides three current outputs to a zero temperature coefficient current synthesis circuit, a high-order curvature compensation circuit and an output circuit respectively, and the dynamic matching current source is composed of a plurality of groups of cascode current sources, wherein the drains of the cascode transistors are connected to the sources of the corresponding cascode transistors through a first dynamic matching switch matrix, the sources of all the cascode transistors are connected to a power supply VDD, and the gates are connected to the output end of a notch filter; the grid electrodes of all the common grid tubes are connected to the same bias voltage VBP, and the drain electrodes respectively and periodically output a first current, a second current and a third current. The first dynamic matching switch matrix realizes the rotation of all common source tubes, and can eliminate the mismatch between current sources and reduce flicker noise.
In this embodiment, the dynamically matched current source is composed of an l+j+k PMOS cascode current source and an l+j+k first dynamically matched switch matrix, where L is greater than or equal to 1, K is greater than or equal to 1,1 is less than or equal to J < L, where L is a zero temperature coefficient current combining circuit providing current, its cascode is m1_1, m1_2,..m1_l, and the cascode is m4_1, m4_2,..m4_l; the J path provides current for the high-order curvature compensation circuit, wherein a common source tube is M2_1, M2_2, & M2_J, and a common gate tube is M5_1, M5_2, & M5_J; the K paths provide current to the output circuit with the common source being m3_1, m3_2. All common source tubes m1_1, m1_2,..m1_l, m2_1, m2_2,..m2_j, m3_1, m3_2,..m3_k are the same size; all co-grid tubes m4_1, m4_2,..m4_l, m5_1, m5_2,..m5_j, m6_1, m6_2,..m6_k are the same size. The grid electrodes of the L+J+K common-source tubes are connected to the output VG of the notch filter, the source electrodes are connected with the power supply VDD, and the drain electrodes are connected with the source electrodes of the L+J+K common-gate tubes through the first dynamic matching switch matrix. The gates of the l+j+k cascode tubes are connected to the same bias voltage VBP, wherein m4_1, m4_2,..the drain of the m4_l tube is connected to the first voltage VD, m5_1, m5_2,..the drain of the m5_j tube is connected to the fourth voltage VZ, m6_1, m6_2,..the drain of the m6_k tube is connected to the output voltage VREF.
In this embodiment, the zero temperature coefficient current synthesizing circuit synthesizes the negative temperature coefficient current and the positive temperature coefficient current into the zero temperature coefficient current, and includes a first resistor R1, a second resistor R2, a third resistor R3, a sixth resistor R6, and a seventh resistor R7, a first bipolar transistor Q1 and a second bipolar transistor Q2. The resistance of the first resistor R1 is the same as that of the second resistor R2, and the resistance of the sixth resistor R6 is the same as that of the seventh resistor R7. One end of the sixth resistor R6 and the seventh resistor R7 are connected to the first voltage VD, and the other end is connected to the second voltage VX and the third voltage VY, respectively. One end of the first resistor R1 is connected to the second voltage VX, and the other end of the first resistor R1 is grounded; one end of the second resistor R2 is connected to the third voltage VY, and the other end is grounded. One end of the third resistor R3 is connected to the second voltage VX, the other end of the third resistor R3 is connected to the emitter of the first bipolar transistor Q1 through the second dynamic matching switch matrix, and the base electrode and the collector electrode of the first bipolar transistor Q1 are grounded; the third voltage VY is connected to the second bipolar transistor Q2 through a second dynamic matching switch matrix, and both the base and collector of the second bipolar transistor Q2 are grounded. The first bipolar transistor Q1 is formed by connecting N unit bipolar transistors in parallel, N is more than or equal to 1, and each unit bipolar transistor is identical to the second bipolar transistor Q2 in size; the second voltage VX is connected to the positive input of the chopper operational amplifier, the third voltage VY is connected to the negative input of the chopper operational amplifier, and the chopper operational amplifier, the notch filter, the miller compensation circuit, the common source tube M1, the common source tube M4, and the zero temperature coefficient current synthesis circuit together form a negative feedback loop, so that the second voltage vx=the third voltage VY, and thus the sixth resistor R6 and the seventh resistor R7 have the same current. The sixth resistor R6 and the seventh resistor R7 may be formed by connecting a plurality of unit resistors in series and parallel, so as to achieve good matching. The resistance of the first resistor R1 is the same as that of the second resistor R2, so that the current of the first resistor R1 is the same as that of the second resistor R2, and the current of the first bipolar transistor Q1 is the same as that of the second bipolar transistor Q2. The difference between the collector voltages |vbe1| and |vbe2| of the first bipolar transistor Q1 and the second bipolar transistor Q2 is the voltage across the third resistor R3, which exhibits a positive temperature coefficient, such that the current of the third resistor R3 exhibits a positive temperature coefficient. The collector voltage |vbe2| of the second bipolar transistor Q2 is a negative temperature coefficient, and |vbe2|=vy, so that the currents of the first resistor R1 and the second resistor R2 are negative temperature coefficients. The current of the sixth resistor R6 is the sum of the current of the first resistor R1 and the current of the third resistor R3, i.e. the sum of the negative temperature coefficient current and the positive temperature coefficient current. The resistance values of the first resistor R1, the second resistor R2 and the third resistor R3 and the size ratio N of the first bipolar transistor Q1 to the second bipolar transistor Q2 are selected to satisfy the formula:
(1+R1/R3)*lnN＝17.2
at this time, the current of the sixth resistor R6 is zero temperature coefficient current.
In this embodiment, the high-order curvature compensation circuit includes a fourth resistor R4, a fifth resistor R5 and a third bipolar transistor Q3, where the resistance values of the fourth resistor R4 and the fifth resistor R5 are the same, and a small current is provided for the zero temperature coefficient current synthesis circuit to compensate the high-order curvature of the zero temperature coefficient current. The third bipolar transistor Q3 is formed by connecting M unit bipolar transistors in parallel, M is larger than or equal to 1, each unit bipolar transistor has the same size as the second bipolar transistor Q2, the third bipolar transistor Q3 is biased at zero temperature coefficient current, the base electrode and the collector electrode of the third bipolar transistor Q3 are grounded, and the emitter electrode of the third bipolar transistor Q3 is connected to the voltage VZ. One ends of the resistor R4 and the resistor R5 are connected to the fourth voltage VZ, and the other ends of the fourth resistor R4 and the fifth resistor R5 are connected to the third voltage VY and the fourth voltage VX, respectively. The base emitter voltage |vbe3| of the third bipolar transistor Q3 implements compensation for the higher-order temperature characteristic of the zero temperature coefficient current, and further reduces the temperature coefficient of the zero temperature coefficient current.
In this embodiment, the first bipolar transistor Q1, the second bipolar transistor Q2, and the third bipolar transistor Q3 in the zero temperature coefficient current synthesis circuit and the high-order curvature compensation circuit are dynamically matched bipolar transistors, and the second dynamically matched switch matrix realizes the rotation of the bipolar transistors of each unit, so as to eliminate the mismatch among the first bipolar transistor Q1, the second bipolar transistor Q2, and the third bipolar transistor Q3.
In this embodiment, the first dynamic matching switch matrix and the second dynamic matching switch matrix are shown in fig. 4, in which the situation of 5 paths is shown, corresponding to 5 paths of input and 5 paths of output, each intersection point in the figure is a switch, the switches with the same number are turned on or off simultaneously, the switches control the switches with 5 numbers to be turned on sequentially, when a switch with a certain number is turned on, the switches with the other numbers are turned off, and the conduction time of the switches with each number is the same.
In this embodiment, as shown in fig. 3, the chopper operational amplifier includes a first chopper CHOP1, a second chopper CHOP2, and seventh to fourteenth PMOS transistors: m7, M8, M9, M10, M11, M12, M13, M14, and first to fourth NMOS transistors: m15, M16, M17, M18, the positive input of the chopper operational amplifier being connected to the positive input of the first chopper CHOP1, the negative input of the chopper operational amplifier being connected to the negative input of the first chopper CHOP 1; the positive output end of the CHOP1 is connected to the grid electrode of the ninth PMOS tube M9, and the negative output end of the first chopper CHOP1 is connected to the grid electrode of the tenth PMOS tube M10; the source electrode of the ninth PMOS tube M9 and the source electrode of the tenth PMOS tube M10 are connected to the drain electrode of the eighth PMOS tube M8; the source electrode of the eighth PMOS tube M8 is connected to the drain electrode of the seventh PMOS tube M7, and the grid electrode is connected to the fifth voltage VP2; the grid electrode of the seventh PMOS tube M7 is connected to the sixth voltage VP1, and the source electrode is connected with a power supply; the fifth voltage VP2 and the sixth voltage VP1 are bias voltages; the drain electrode of the ninth PMOS tube M9 is connected to the drain electrode of the third NMOS tube M17 and the source electrode of the first NMOS tube M15, and the drain electrode of the tenth PMOS tube M10 is connected to the drain electrode of the fourth NMOS tube M18 and the source electrode of the second NMOS tube M16; the sources of the third NMOS tube M17 and the fourth NMOS tube M18 are grounded, and the gates are connected to the seventh voltage VN1; the gates of the first NMOS tube M15 and the second NMOS tube M16 are connected to an eighth voltage VN2; the drain electrode of the first NMOS tube M15 is connected to the drain electrode of the thirteenth PMOS tube M13 and the positive input end of the second chopper CHOP 2; the drain electrode of the second NMOSM16 is connected to the drain electrode of the fourteenth PMOS tube M14 and the negative input end of the second chopper CHOP 2; the grid electrodes of the thirteenth PMOS tube M13 and the fourteenth PMOS tube M14 are connected to the fifth voltage VP2, the source electrode of the thirteenth PMOS tube M13 is connected to the drain electrode of the eleventh PMOS tube M11, and the source electrode of the fourteenth PMOS tube M14 is connected to the drain electrode of the twelfth PMOS tube M12; the sources of the eleventh PMOS tube M11 and the twelfth PMOS tube M12 are connected with power sources, the grid electrodes are connected to the positive output end of the second chopper CHOP2, and the negative output end of the second chopper CHOP2 is the output end of the chopping operational amplifier.
In the embodiment, the chopper operational amplifier detects the voltage difference in the zero temperature coefficient current synthesis circuit, and can eliminate the mismatch of the differential input of the operational amplifier and reduce the flicker noise of the MOS tube in the operational amplifier; the notch filter is used for filtering jitter at the output end of the chopper operational amplifier and can be realized by adopting a switch capacitor; the miller compensation circuit is used for compensating the phase margin of the negative feedback loop and comprises a first capacitor Cm and a ninth resistor Rm, wherein one end of the first capacitor Cm is connected with the output end of the notch filter, and the other end of the first capacitor Cm is connected with one end of the ninth resistor Rm; the other end of the ninth resistor Rm is connected with the input end of the zero temperature coefficient current synthesis circuit.
In this embodiment, the output circuit is composed of an eighth resistor Ro and a filter capacitor Co, so as to realize current-to-voltage conversion, and provide a filtering function, and the output voltage is VREF, that is, a reference voltage value. The eighth resistor Ro and the filter capacitor Co are connected in parallel, one end of each resistor Ro is grounded, and the other end of each resistor Ro is connected to the output voltage VREF. The dynamic matching current source provides L paths of current for the zero temperature coefficient current synthesis circuit and provides K paths of current for the output circuit, and the dynamic matching current source comprises:
VREF＝(2K/L)*(Ro/R1)*[|VBE2|+(R1/R3)*V T *lnN]
wherein V is T Is thermal voltage, i.e. V T =kt/q, k is boltzmann constant, T is kelvin temperature, q is electron charge. Appropriate values for K, L and Ro/R1 may be selected based on the desired reference voltage values.
The present invention provides a bandgap reference circuit, and the method and the way for implementing the technical scheme are numerous, the above description is only a specific implementation manner of the present invention, and it should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention. The components not explicitly described in this embodiment can be implemented by using the prior art.
Claims (8)
1. The band gap reference circuit is characterized by comprising a dynamic matching current source, a zero temperature coefficient current synthesis circuit, a high-order curvature compensation circuit, a chopper operational amplifier, a notch filter and an output circuit:
the dynamic matching current source is used for periodically providing a first current, a second current and a third current, wherein the first current is the input of the zero temperature coefficient current synthesis circuit, the second current is the input of the high-order curvature compensation circuit, and the third current is the input of the output circuit;
the zero temperature coefficient current synthesis circuit is used for generating negative temperature coefficient current and positive temperature coefficient current, synthesizing the negative temperature coefficient current and the positive temperature coefficient current into zero temperature coefficient current, and inputting the voltage of the current synthesis point into the chopper operational amplifier;
the high-order curvature compensation circuit is used for providing compensation current for the zero temperature coefficient current synthesis circuit so as to compensate the high-order temperature characteristic of the zero temperature coefficient current;
the chopper operational amplifier is used for detecting the voltage difference in the zero temperature coefficient current synthesis circuit, eliminating the mismatch of differential input of the operational amplifier and reducing the flicker noise of an MOS tube in the operational amplifier, and the output end is connected with the input end of the notch filter;
the notch filter is used for filtering jitter at the output end of the chopper operational amplifier, and the output end is connected with the dynamic matching current source;
the output circuit is used for converting the third current into a reference voltage;
the dynamic matching current sources comprise more than three groups of common-source and common-gate current sources, wherein the drain electrodes of the common-source tubes are connected to the source electrodes of the corresponding common-gate tubes through a first dynamic matching switch matrix, the source electrodes of all the common-source tubes are connected to a power supply VDD, and the grid electrodes are connected to the output end of the notch filter; the grid electrodes of all the common grid tubes are connected to the same bias voltage VBP, and the drain electrodes respectively and periodically output a first current, a second current and a third current;
the zero temperature coefficient current synthesis circuit comprises two paths, one path comprises a first resistor R1, a third resistor R3, a sixth resistor R6 and a first bipolar transistor Q1, and the other path comprises a second resistor R2, a seventh resistor R7 and a second bipolar transistor Q2;
the voltage at the input end of the zero temperature coefficient current synthesis circuit is recorded as a first voltage VD, one end of a sixth resistor R6 and one end of a seventh resistor R7 are connected to the first voltage VD, the other end of the sixth resistor R6 and the seventh resistor R7 are respectively connected to the positive input end and the negative input end of the chopper operational amplifier, and the corresponding voltages are respectively recorded as a second voltage VX and a third voltage VY;
one end of the first resistor R1 is connected to the second voltage VX, and the other end of the first resistor R1 is grounded; one end of the second resistor R2 is connected to the third voltage VY, and the other end of the second resistor R2 is grounded; one end of the resistor R3 is connected to the second voltage VX, the other end of the resistor R3 is connected to the emitter of the first bipolar transistor Q1 through a second dynamic matching switch matrix, and the base electrode and the collector electrode of the first bipolar transistor Q1 are grounded; the third voltage VY is connected to the second bipolar transistor Q2 through a second dynamic matching switch matrix, and the base electrode and the collector electrode of the second bipolar transistor Q2 are grounded;
the high-order curvature compensation circuit comprises a fourth resistor R4, a fifth resistor R5 and a third bipolar transistor Q3, wherein second current is respectively input to the fourth resistor R4, the fifth resistor R5 and the third bipolar transistor Q3, the voltage at the input end of the high-order curvature compensation circuit is recorded as fourth voltage VZ, one ends of the fourth resistor R4 and the fifth resistor R5 are both connected to the fourth voltage VZ and also connected to the emitter of the third bipolar transistor Q3 through a second dynamic matching switch matrix, and the other ends of the fourth resistor R4 and the fifth resistor R5 are respectively connected to third voltage VY and second voltage VX; the third bipolar transistor Q3 is biased at zero temperature coefficient current with its base and collector grounded.
2. A bandgap reference circuit according to claim 1, wherein said first resistor R1 and said second resistor R2 have the same resistance, and wherein said sixth resistor R6 and said seventh resistor R7 have the same resistance; the second bipolar transistor Q2 comprises a unit bipolar transistor, the first bipolar transistor Q1 is formed by connecting N unit bipolar transistors in parallel, N represents the size ratio of the first bipolar transistor Q1 to the second bipolar transistor Q2, and N is more than or equal to 1;
the chopper operational amplifier, the notch filter, the cascode current source connected with the zero temperature coefficient current synthesis circuit in the dynamic matching current source and the zero temperature coefficient current synthesis circuit form a negative feedback loop together, so that the second voltage VX=the third voltage VY;
the resistance values of the first resistor R1, the second resistor R2 and the third resistor R3, and the size ratio N of the first bipolar transistor Q1 to the second bipolar transistor Q2 satisfy the following formula:
(1+R1/R3)*lnN＝17.2
thus, the currents of the first bipolar transistor Q1 and the second bipolar transistor Q2 have positive temperature coefficients, the currents of the first resistor R1 and the second resistor R2 have negative temperature coefficients, and the currents of the sixth resistor R6 and the seventh resistor R7 have zero temperature coefficients.
3. A bandgap reference circuit according to claim 2, wherein the third bipolar transistor Q3 comprises M unit bipolar transistors connected in parallel, M representing the ratio of the dimensions of the third bipolar transistor Q3 to the second bipolar transistor Q2, M being equal to or greater than 1.
4. A bandgap reference circuit according to claim 3, wherein L groups of cascode current sources are connected to the zero temperature coefficient current synthesis circuit, J groups of cascode current sources are connected to the higher order curvature compensation circuit, and K groups of cascode current sources are connected to the output circuit, wherein L is greater than or equal to 1, K is greater than or equal to 1,1 is less than or equal to J < L, the first dynamic matching switch matrix comprises l+j+k paths, and rotation of all the cascode transistors is periodically achieved;
the second dynamic matching switch matrix comprises N+1+M paths, each path is connected with a unit bipolar transistor, and rotation of each unit bipolar transistor is periodically realized.
5. The bandgap reference circuit according to claim 4, wherein said output circuit comprises an eighth resistor Ro and a filter capacitor Co, and wherein said output voltage is VREF, i.e. a reference voltage value, and wherein a third current is input to said eighth resistor Ro and said filter capacitor Co, respectively, and wherein one end of said eighth resistor Ro and one end of said filter capacitor Co are both connected to said output voltage VREF and the other end thereof is both grounded; the output voltage VREF is expressed as:
VREF＝(2K/L)*(Ro/R1)*[|VBE2|+(R1/R3)*V T *lnN]
wherein V is T Is thermal voltage, i.e. V T =kt/q, k is boltzmann constant, T is kelvin temperature, q is electron charge; vbe2 is the collector voltage of the second bipolar transistor Q2;
appropriate values for K, L and Ro/R1 are selected based on the desired reference voltage value VREF.
6. The band gap reference circuit according to claim 5, further comprising a miller compensation circuit, wherein the miller compensation circuit is used for compensating the phase margin of the negative feedback loop and comprises a first capacitor Cm and a ninth resistor Rm, one end of the first capacitor Cm is connected with the output end of the notch filter, and the other end of the first capacitor Cm is connected with one end of the ninth resistor Rm; the other end of the ninth resistor Rm is connected with the input end of the zero temperature coefficient current synthesis circuit.
7. The bandgap reference circuit according to claim 6, wherein said sixth resistor R6 and said seventh resistor R7 are each formed by series-parallel connection of two or more cell resistors.
8. The bandgap reference circuit according to claim 7, wherein said chopper operational amplifier comprises a first chopper CHOP1, a second chopper CHOP2, seventh to fourteenth PMOS transistors: m7, M8, M9, M10, M11, M12, M13, M14, and first to fourth NMOS transistors: m15, M16, M17, M18, the positive input of the chopper operational amplifier being connected to the positive input of the first chopper CHOP1, the negative input of the chopper operational amplifier being connected to the negative input of the first chopper CHOP 1; the positive output end of the CHOP1 is connected to the grid electrode of the ninth PMOS tube M9, and the negative output end of the first chopper CHOP1 is connected to the grid electrode of the tenth PMOS tube M10; the source electrode of the ninth PMOS tube M9 and the source electrode of the tenth PMOS tube M10 are connected to the drain electrode of the eighth PMOS tube M8; the source electrode of the eighth PMOS tube M8 is connected to the drain electrode of the seventh PMOS tube M7, and the grid electrode is connected to the fifth voltage VP2; the grid electrode of the seventh PMOS tube M7 is connected to the sixth voltage VP1, and the source electrode is connected with a power supply; the drain electrode of the ninth PMOS tube M9 is connected to the drain electrode of the third NMOS tube M17 and the source electrode of the first NMOS tube M15, and the drain electrode of the tenth PMOS tube M10 is connected to the drain electrode of the fourth NMOS tube M18 and the source electrode of the second NMOS tube M16; the sources of the third NMOS tube M17 and the fourth NMOS tube M18 are grounded, and the gates are connected to the seventh voltage VN1; the gates of the first NMOS tube M15 and the second NMOS tube M16 are connected to an eighth voltage VN2; the drain electrode of the first NMOS tube M15 is connected to the drain electrode of the thirteenth PMOS tube M13 and the positive input end of the second chopper CHOP 2; the drain electrode of the second NMOSM16 is connected to the drain electrode of the fourteenth PMOS tube M14 and the negative input end of the second chopper CHOP 2; the grid electrodes of the thirteenth PMOS tube M13 and the fourteenth PMOS tube M14 are connected to the fifth voltage VP2, the source electrode of the thirteenth PMOS tube M13 is connected to the drain electrode of the eleventh PMOS tube M11, and the source electrode of the fourteenth PMOS tube M14 is connected to the drain electrode of the twelfth PMOS tube M12; the sources of the eleventh PMOS tube M11 and the twelfth PMOS tube M12 are connected with power sources, the grid electrodes are connected to the positive output end of the second chopper CHOP2, and the negative output end of the second chopper CHOP2 is the output end of the chopping operational amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211173768.XA CN115357087B (en) | 2022-09-26 | 2022-09-26 | Band gap reference circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211173768.XA CN115357087B (en) | 2022-09-26 | 2022-09-26 | Band gap reference circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115357087A CN115357087A (en) | 2022-11-18 |
| CN115357087B true CN115357087B (en) | 2024-01-19 |
Family
ID=84007585
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211173768.XA Active CN115357087B (en) | 2022-09-26 | 2022-09-26 | Band gap reference circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115357087B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118051088B (en) * | 2024-04-16 | 2024-06-21 | 成都电科星拓科技有限公司 | Voltage-current multiplexing band gap reference source |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101980097A (en) * | 2010-09-30 | 2011-02-23 | 浙江大学 | Low-voltage reference source with low flicker noise and high power-supply suppression |
| CN108664069A (en) * | 2017-03-31 | 2018-10-16 | 上海东软载波微电子有限公司 | The calibration method and device of band-gap reference circuit |
| CN109813455A (en) * | 2019-04-09 | 2019-05-28 | 杭州万高科技股份有限公司 | A kind of CMOS temperature transmitter |
| CN112219097A (en) * | 2018-06-29 | 2021-01-12 | 希奥检测有限公司 | Temperature sensor semiconductor device with paired diodes and feedback loop |
| CN114945887A (en) * | 2020-01-29 | 2022-08-26 | 松下知识产权经营株式会社 | Bandgap reference circuit with reduced flicker noise |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5996283B2 (en) * | 2012-06-07 | 2016-09-21 | ルネサスエレクトロニクス株式会社 | Semiconductor device provided with voltage generation circuit |
| TWI719809B (en) * | 2020-01-20 | 2021-02-21 | 瑞昱半導體股份有限公司 | Temperature sensing circuit |
-
2022
- 2022-09-26 CN CN202211173768.XA patent/CN115357087B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101980097A (en) * | 2010-09-30 | 2011-02-23 | 浙江大学 | Low-voltage reference source with low flicker noise and high power-supply suppression |
| CN108664069A (en) * | 2017-03-31 | 2018-10-16 | 上海东软载波微电子有限公司 | The calibration method and device of band-gap reference circuit |
| CN112219097A (en) * | 2018-06-29 | 2021-01-12 | 希奥检测有限公司 | Temperature sensor semiconductor device with paired diodes and feedback loop |
| CN109813455A (en) * | 2019-04-09 | 2019-05-28 | 杭州万高科技股份有限公司 | A kind of CMOS temperature transmitter |
| CN114945887A (en) * | 2020-01-29 | 2022-08-26 | 松下知识产权经营株式会社 | Bandgap reference circuit with reduced flicker noise |
Non-Patent Citations (2)
| Title |
|---|
| "A Single-Trim CMOS Bandgap Reference With a 3σ Inaccuracy of ±0.15% From -40 ℃ to 125℃";Guang Ge 等;IEEE JOURNAL OF SOLID-STATE CIRCUITS;第46卷(第11期);第2693-2701页 * |
| "A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%,−0.12% for Battery-Monitoring Applications";Jun-Ho Boo 等;IEEE JOURNAL OF SOLID-STATE CIRCUITS;第56卷(第4期);第1197-1206页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115357087A (en) | 2022-11-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101630176B (en) | Low-voltage complementary metal-oxide-semiconductor transistor (CMOS) band gap reference voltage source | |
| CN106959723A (en) | A kind of bandgap voltage reference of wide input range high PSRR | |
| CN106873704B (en) | Reference voltage source and its positive temperature coefficient voltage generation circuit | |
| CN109164867B (en) | all-MOS reference current generating circuit | |
| CN110825155B (en) | Zero temperature coefficient reference voltage and current source generating circuit | |
| CN115437442B (en) | High-order compensation band gap voltage reference circuit | |
| CN115357087B (en) | Band gap reference circuit | |
| CN113721694B (en) | Self-compensating band gap reference source structure based on curvature function and application thereof | |
| CN115877907A (en) | Band-gap reference source circuit | |
| CN114356014B (en) | Low-voltage reference voltage generating circuit and chip | |
| CN116880644A (en) | High-order curvature temperature compensation band gap reference circuit | |
| CN110879626A (en) | Reference circuit under low power supply voltage | |
| CN113655841B (en) | Band gap reference voltage circuit | |
| CN215340874U (en) | Zero temperature coefficient current generating circuit with band gap reference | |
| CN106020320B (en) | A kind of reference voltage source structure for improving supply-voltage rejection ratio | |
| CN211087041U (en) | Low-temperature coefficient CMOS reference voltage source | |
| CN117519403B (en) | Band gap reference circuit and electronic equipment | |
| CN111064453B (en) | Voltage comparator | |
| CN114546019A (en) | Temperature coefficient adjustable reference voltage source | |
| CN118051088B (en) | Voltage-current multiplexing band gap reference source | |
| CN111061329A (en) | Band-gap reference circuit with high loop gain and double loop negative feedback | |
| CN117517753B (en) | Current sampling circuit adopting resistance sampling and compatible with P, N type power tube | |
| CN112379715B (en) | Low-noise band-gap reference circuit | |
| CN218122538U (en) | Reference circuit with high order temperature compensation | |
| CN220526232U (en) | Band-gap reference voltage source controlled by digital signal of current mirror structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |