CN112379715B - Low-noise band-gap reference circuit - Google Patents

Low-noise band-gap reference circuit Download PDF

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CN112379715B
CN112379715B CN202011255285.5A CN202011255285A CN112379715B CN 112379715 B CN112379715 B CN 112379715B CN 202011255285 A CN202011255285 A CN 202011255285A CN 112379715 B CN112379715 B CN 112379715B
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pnp triode
emitter
pnp
base
drain
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CN112379715A (en
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黄少卿
罗永波
宣志斌
肖培磊
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CETC 58 Research Institute
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

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Abstract

The invention discloses a low-noise band-gap reference circuit, and belongs to the field of analog circuits. The low noise bandgap reference circuit comprises a currentThe amplifier comprises a source S1, PNP triodes Q1-Q9, PMOS tubes M1-M8, NMOS tubes M9-M11 and resistors R1 and R2, wherein the PNP triodes Q1, Q2, Q3 and the NMOS tubes M9-M11 form an amplifier structure. Through the connection mode of the structure, the reference voltage V can be realizedREFThe influence of noise and transistor mismatch voltage is reduced regardless of the change of temperature and power supply voltage, and constant output voltage is kept in a certain temperature and bias current range.

Description

Low-noise band-gap reference circuit
Technical Field
The invention relates to the technical field of analog circuits, in particular to a low-noise band-gap reference circuit.
Background
The bandgap reference circuit provides a constant output reference voltage if the output reference voltage VREFProblems can arise with even small changes, such as hundreds of millivolts, over a range of temperatures or bias currents. It is therefore desirable to have a bandgap reference circuit that provides an output reference voltage V that is substantially constant over a range of temperatures and bias currentsREF。
Conventional standard CMOS bandgap reference circuits typically include an amplifier that includes a pair of P-channel MOS transistors. Excess carriers can be trapped in the silicon and silicon dioxide surfaces of MOS transistors and the excess charge can cause variations in the threshold voltages of MOS transistors in the differential pair of amplifiers. For example, the threshold voltages of the two MOS transistors in a differential pair may differ by more than 5 mV. This difference introduces a mismatch voltage into the amplifier for the reference voltage V in the bandgap reference circuitREFA certain influence is produced. In addition, the charge trapped at the silicon and silicon dioxide surfaces of the differential pair MOS transistors of the bandgap reference amplifier can vary over time, resulting in VREFIt also varies with time, even at constant temperature. VREFCan result in undesirable 1/f output noise. In addition, due to the characteristics of MOS transistors, P-channel MOS transistors in a differential pair may be at VREFWhich introduces thermal noise, which is also undesirable.
Another disadvantage of conventional standard CMOS bandgap reference circuits is that they are sensitive to a supply voltage VCCMiddle relative ratioSmall variations are very sensitive. VCCWill cause a change in the bias current of the bandgap reference circuit, which will also be applied to the reference voltage VREFA certain influence is produced.
It is therefore desirable to provide a bandgap reference circuit with reduced noise that provides a constant output reference voltage V over a range of supply voltages and temperaturesREF。
Disclosure of Invention
The invention aims to provide a low-noise band-gap reference circuit to solve the problem of noise-to-reference voltage V in the traditional CMOS band-gap reference circuitREFThere is a problem of influence.
In order to solve the technical problem, the invention provides a low-noise band-gap reference circuit which comprises a current source S1, PNP triodes Q1-Q9, PMOS tubes M1-M8, NMOS tubes M9-M11, resistors R1 and R2; wherein the content of the first and second substances,
one end of the current source S1 and the power voltage VCCThe other end of the PNP triode is connected with an emitting electrode of a PNP triode Q3 and PMOS tubes M1-M8, and gates of the PMOS tubes M1-M8 are connected with each other and are connected with a drain electrode of a P-type MOS tube M5 to form a current mirror structure;
the drain of the PMOS transistor M1 is connected to the first input terminal of the resistor R1, the drain of the PMOS transistor M2 is connected to the emitter of the PNP transistor Q4, the drain of the PMOS transistor M3 is connected to the emitter of the PNP transistor Q6, the drain of the PMOS transistor M4 is connected to the emitter of the PNP transistor Q8, the drain of the PMOS transistor M5 is connected to the emitters of the PNP transistors Q1 and Q2, the drain of the PMOS transistor M6 is connected to the emitter of the PNP transistor Q9, the drain of the PMOS transistor M7 is connected to the emitter of the PNP transistor Q7, and the drain of the PMOS transistor M8 is connected to the emitter of the PNP transistor Q5.
Optionally, a base of the PNP transistor Q4 is connected to the first input terminal of the resistor R1, a base of the PNP transistor Q6 is connected to an emitter of the PNP transistor Q4, a base of the PNP transistor Q8 is connected to an emitter of the PNP transistor Q6, a base of the PNP transistor Q9 is connected to an emitter of the PNP transistor Q7, a base of the PNP transistor Q7 is connected to an emitter of the PNP transistor Q5, a base of the PNP transistor Q5 is connected to the second input terminal of the resistor R1, and collectors of the PNP transistors Q4, Q6, Q8, Q9, Q7, and Q5 are grounded.
Optionally, the PNP triode Q1, Q2, Q3 and the NMOS transistor M9-M11 form an amplifier circuit;
the base of a PNP triode Q1 is connected with the emitter of a PNP triode Q8, the collector of a PNP triode Q1 is connected with the drain of an NMOS tube M9, the base of the PNP triode Q2 is connected with the emitter of the PNP triode Q9, the collector of a PNP triode Q2 is connected with the drain of an NMOS tube M10, the gates of the NMOS tubes M9 and M10 are connected with each other and with the drain of the NMOS tube M9 to form a current mirror structure, the sources of the NMOS tubes M9 and M10 are grounded, the gate of the NMOS tube M11 is connected with the drain of the NMOS tube M10, the drain of the NMOS tube M11 is connected with the collector of the PNP triode Q3, the source of the NMOS tube M11 is grounded, and the base of the PNP triode Q3 is connected with the collector to form a diode structure.
Optionally, a second input terminal of the resistor R1 is connected to the first input terminal of the resistor R2, and a second input terminal of the resistor R2 is grounded.
The low-noise band-gap reference circuit provided by the invention comprises a current source S1, PNP triodes Q1-Q9, PMOS tubes M1-M8, NMOS tubes M9-M11, and resistors R1 and R2, wherein the PNP triodes Q1, Q2, Q3 and the NMOS tubes M9-M11 form an amplifier structure. Through the connection mode of the structure, the reference voltage V can be realizedREFThe influence of noise and transistor mismatch voltage is reduced regardless of the change of temperature and power supply voltage, and constant output voltage is kept in a certain temperature and bias current range.
Drawings
Fig. 1 is a schematic diagram of a low-noise bandgap reference circuit according to the present invention.
Detailed Description
The low noise bandgap reference circuit proposed by the present invention is further described in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention providesA low-noise band-gap reference circuit is structurally shown in figure 1 and comprises a current source S1, PNP triodes Q1-Q9, PMOS tubes M1-M8, NMOS tubes M9-M11, resistors R1 and R2; wherein, one end of the current source S1 is connected to the power voltage VCCThe other end of the PNP triode is connected with an emitting electrode of a PNP triode Q3 and PMOS tubes M1-M8, and gates of the PMOS tubes M1-M8 are connected with each other and are connected with a drain electrode of a P-type MOS tube M5 to form a current mirror structure; PNP triode Q1, Q2, Q3 and NMOS tube M9-M11 constitute amplifier circuit;
the drain electrode of a PMOS tube M1 is connected with the first input end of a resistor R1, the drain electrode of a PMOS tube M2 is connected with the emitter electrode of a PNP triode Q4, the drain electrode of the PMOS tube M3 is connected with the emitter electrode of a PNP triode Q6, the drain electrode of a PMOS tube M4 is connected with the emitter electrode of the PNP triode Q8, the drain electrode of the PMOS tube M5 is connected with the emitter electrodes of a PNP triode Q1 and a PNP triode Q2, the drain electrode of the PMOS tube M6 is connected with the emitter electrode of the PNP triode Q9, the drain electrode of a PMOS tube M7 is connected with the emitter electrode of the PNP triode Q7, and the drain electrode of the PMOS tube M8 is connected with the emitter electrode of the PNP triode Q5; the base of the PNP triode Q4 is connected with the first input end of the resistor R1, the base of the PNP triode Q6 is connected with the emitter of the PNP triode Q4, the base of the PNP triode Q8 is connected with the emitter of the PNP triode Q6, the base of the PNP triode Q9 is connected with the emitter of the PNP triode Q7, the base of the PNP triode Q7 is connected with the emitter of the PNP triode Q5, the base of the PNP triode Q5 is connected with the second input end of the resistor R1, and the collectors of the PNP triodes Q4, Q6, Q8, Q9, Q7 and Q5 are grounded; the base of a PNP triode Q1 is connected with the emitter of a PNP triode Q8, the collector of a PNP triode Q1 is connected with the drain of an NMOS tube M9, the base of the PNP triode Q2 is connected with the emitter of the PNP triode Q9, the collector of a PNP triode Q2 is connected with the drain of an NMOS tube M10, the gates of the NMOS tubes M9 and M10 are connected with each other and with the drain of the NMOS tube M9 to form a current mirror structure, the sources of the NMOS tubes M9 and M10 are grounded, the gate of the NMOS tube M11 is connected with the drain of the NMOS tube M10, the drain of the NMOS tube M11 is connected with the collector of the PNP triode Q3, the source of the NMOS tube M11 is grounded, and the base of the PNP triode Q3 is connected with the collector to form a diode structure. The second input end of the resistor R1 is connected with the first input end of the resistor R2, and the second input end of the resistor R2 is grounded.
The low noise bandgap reference circuit receives a supply voltage V from an external voltage sourceCC(ii) a The bias current source S1 with finite impedance provides a reference current source outputting a current equal to 15I, e.g. 15I for 150uA at 25 c. The bias current source S1 is proportional to absolute temperature. Thus, the temperature variation or supply voltage V of the low noise bandgap reference circuitCCWill result in a change in the current of current source S1.
The current of the bias current source S1 is divided by PMOS tubes M1-M8 and NMOS tube M11, wherein the current of the PMOS tubes M1-M8 is divided according to a certain proportion, and the proportion is determined by the width-length ratio of MOS transistors of the PMOS tubes M1-M8. The ratio of the transistors M1: M2: M3: M4: M5: M6: M7: M8 can be 4:1:1:1:1:1, and the current ratio is 4I: I: I: I: I, as shown in FIG. 1. W/L of the NMOS tube M11 is 8 times that of the NMOS tubes M9 and M10. Other suitable transistor ratios may also be used, if desired, in accordance with the principles of the present invention.
The low noise bandgap reference circuit also includes PNP transistors Q1 and Q2, which are differential pair transistors in the amplifier, and when the base voltages of the PNP transistors Q1 and Q2 are equal, I/2 current flows through Q1 and Q2, respectively.
The low-noise band-gap reference circuit comprises PNP triodes Q4-Q9, and the base electrode of the PNP triode Q2 is connected with the output V of the reference voltageREFThe value is as follows:
VREF＝VR2+VBE_Q9+VBE_Q7+VBE_Q5 (1)
wherein VR2Is the voltage drop across resistor R2, VBE_Q9、VBE_Q7And VBE_Q5Is the BE junction voltage of PNP triodes Q9, Q7 and Q5.
The base voltage value of the PNP transistor Q1 is:
VQ1＝VR2+VR1+VBE_Q8+VBE_Q6+VBE_Q4 (2)
wherein VR1Is the voltage drop across resistor R1, VBE_Q8、VBE_Q6And VBE_Q4Is the BE junction voltage of PNP triodes Q8, Q6 and Q4.
Base-emitter junction of PNP triodes Q4, Q6 and Q8The area is 8 times the area of the base-emitter junction of the PNP transistors Q5, Q7, and Q9. Thus, the base-emitter voltage V of the PNP transistors Q4, Q6 and Q8BEThe base-emitter voltage of the PNP transistors Q5, Q7, and Q9 is 26mV × ln (8) ═ 54mV greater. Thus VBE_Q8+VBE_Q6+VBE_Q4Ratio VBE_Q9+VBE_Q7+VBE_Q5162mV larger. For example, when the resistance R1 is 4.05k Ω, the voltage drop across the resistance R1 is 162mV, and the current across the resistance R1 is 40 μ A. When the base voltages of the PNP triodes Q1 and Q2 are equal, the low-noise band-gap reference circuit enters a stable state and outputs a voltage VREFIs constant.
The PNP transistors Q1 and Q2 as differential pair transistors introduce a low offset voltage which affects VREFThe offset voltage of the bipolar transistor is 100-1000 times smaller than that of the MOS transistor, and three emitter follower triode structures are used for providing three times of delta VBEThe variation further reduces the offset voltage to the reference value VREFThe influence of (c).
This embodiment is for the supply voltage VCCAlso has a certain resistance. When the power supply voltage VCCAs the current of the bias current source S1 increases, the current through resistors R1 and R2 also increases slightly, causing the base voltages of transistors Q1 and Q2 to increase. Since the base voltage increment of the transistor Q4 is larger than that of the transistor Q5, the base voltage increment of the transistor Q1 is larger than that of the transistor Q2, so that the current flowing through the transistor Q1 is reduced and is smaller than that flowing through the transistor Q2, the gate voltage of the M11 is increased, the current flowing through the M11 is increased, the current increment of the current source S1 is absorbed, the current increments of the resistors R1 and R2 are reduced, a negative feedback loop is formed, and the currents flowing through the PMOS transistors M1-M8 and the resistors R1 and R2 are kept constant. The NMOS transistor M11 makes the voltage drop across the resistor R2 constant at 162mV, the base voltages of Q1 and Q2 are equal, and the output voltage V isREFAnd VCCIs independent of first order small signal variations.
In the present invention, the terms "connected", "connecting", and the like mean electrically connected, and mean directly or indirectly electrically connected unless otherwise specified. The first port and the second port of all the resistors are defined according to the flowing direction of the current, one end of the current passing through the resistor firstly is the first port, and the other end of the current passing through the resistor is the second port.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (2)

1. A low-noise band-gap reference circuit is characterized by comprising a current source S1, PNP triodes Q1-Q9, PMOS tubes M1-M8, NMOS tubes M9-M11, resistors R1 and R2; wherein the content of the first and second substances,
one end of the current source S1 and the power voltage VCCThe other end of the PNP triode Q3 is connected with an emitter of a PNP triode Q3 and PMOS tubes M1-M8, and gates of the PMOS tubes M1-M8 are connected with each other and connected with a drain of a P-type MOS tube M5 to form a current mirror structure;
the drain electrode of a PMOS tube M1 is connected with the first input end of a resistor R1, the drain electrode of a PMOS tube M2 is connected with the emitter electrode of a PNP triode Q4, the drain electrode of the PMOS tube M3 is connected with the emitter electrode of a PNP triode Q6, the drain electrode of a PMOS tube M4 is connected with the emitter electrode of the PNP triode Q8, the drain electrode of the PMOS tube M5 is connected with the emitter electrodes of a PNP triode Q1 and a PNP triode Q2, the drain electrode of the PMOS tube M6 is connected with the emitter electrode of the PNP triode Q9, the drain electrode of a PMOS tube M7 is connected with the emitter electrode of the PNP triode Q7, and the drain electrode of the PMOS tube M8 is connected with the emitter electrode of the PNP triode Q5;
the base of the PNP triode Q4 is connected with the first input end of the resistor R1, the base of the PNP triode Q6 is connected with the emitter of the PNP triode Q4, the base of the PNP triode Q8 is connected with the emitter of the PNP triode Q6, the base of the PNP triode Q9 is connected with the emitter of the PNP triode Q7, the base of the PNP triode Q7 is connected with the emitter of the PNP triode Q5, the base of the PNP triode Q5 is connected with the second input end of the resistor R1, and the collectors of the PNP triodes Q4, Q6, Q8, Q9, Q7 and Q5 are grounded;
the PNP triode Q1, the Q2, the Q3 and the NMOS tubes M9-M11 form an amplifier circuit; the base of a PNP triode Q1 is connected with the emitter of a PNP triode Q8, the collector of a PNP triode Q1 is connected with the drain of an NMOS tube M9, the base of the PNP triode Q2 is connected with the emitter of the PNP triode Q9, the collector of a PNP triode Q2 is connected with the drain of an NMOS tube M10, the gates of the NMOS tubes M9 and M10 are connected with each other and with the drain of the NMOS tube M9 to form a current mirror structure, the sources of the NMOS tubes M9 and M10 are grounded, the gate of the NMOS tube M11 is connected with the drain of the NMOS tube M10, the drain of the NMOS tube M11 is connected with the collector of the PNP triode Q3, the source of the NMOS tube M11 is grounded, and the base of the PNP triode Q3 is connected with the collector to form a diode structure.
2. The low noise bandgap reference circuit of claim 1, wherein a second input terminal of the resistor R1 is connected to a first input terminal of a resistor R2, and a second input terminal of the resistor R2 is connected to ground.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101976095A (en) * 2010-11-19 2011-02-16 长沙景嘉微电子有限公司 High-precision band-gap reference source circuit based on emitter current compensation
CN104375553A (en) * 2014-12-10 2015-02-25 中国电子科技集团公司第四十七研究所 Bandgap reference circuit and base current compensation circuit
CN104503528A (en) * 2014-12-24 2015-04-08 电子科技大学 Low-noise band-gap reference circuit reducing detuning influence
CN111190454A (en) * 2020-02-28 2020-05-22 清华大学 Curvature compensation low-temperature drift band gap reference voltage source circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4064799B2 (en) * 2002-12-04 2008-03-19 旭化成エレクトロニクス株式会社 Constant voltage generator

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101976095A (en) * 2010-11-19 2011-02-16 长沙景嘉微电子有限公司 High-precision band-gap reference source circuit based on emitter current compensation
CN104375553A (en) * 2014-12-10 2015-02-25 中国电子科技集团公司第四十七研究所 Bandgap reference circuit and base current compensation circuit
CN104503528A (en) * 2014-12-24 2015-04-08 电子科技大学 Low-noise band-gap reference circuit reducing detuning influence
CN111190454A (en) * 2020-02-28 2020-05-22 清华大学 Curvature compensation low-temperature drift band gap reference voltage source circuit

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