CN105786081A - Reference voltage source circuit - Google Patents

Abstract

The invention discloses a reference voltage source circuit. The reference voltage source circuit comprises a biasing circuit, gate-source voltage difference generation circuits and a reference voltage output circuit, wherein a first NMOS (N-channel metal oxide semiconductor) transistor and a second NMOS transistor of the biasing circuit both work in a subthreshold area, and a gate-source voltage difference with a positive temperature coefficient is formed through subtraction of the gate-source voltage of the first NMOS transistor and the gate-source voltage of the second NMOS transistor and is supplied to two ends of a first resistor; each gate-source voltage difference generation circuit comprises a third NMOS transistor and a fourth NMOS transistor which work in the subthreshold area, the third NMOS transistor and the fourth NMOS transistor are connected in series, and a gate-source voltage difference of the third NMOS transistor and the fourth NMOS transistor is formed on a source and a drain of the third NMOS transistor; gate-source voltage differences generated by the biasing circuit and the gate-source voltage difference generation circuits are superposed to a source of a fifth NMOS transistor of the reference voltage output circuit, a gate and a drain of the fifth NMOS transistor are connected, reference voltage is output, the fifth NMOS transistor works in the subthreshold area, and reference voltage irrelevant with the temperature is formed through superposition of the gate-source voltage differences and positive and negative temperature coefficients of gate-source voltage of the fifth NMOS transistor. According to the reference voltage source circuit, the area and the energy consumption can be reduced.

Description

Reference voltage source circuit

Technical field

The present invention relates to a kind of semiconductor integrated circuit, particularly relate to a kind of reference voltage source circuit.

Background technology

Reference voltage source circuit is widely used in integrated circuits, as it is shown in figure 1, be the circuit structure diagram of existing reference voltage source circuit；The grid of NMOS tube MN101 and MN102 links together and is all connected to the drain electrode of NMOS tube NM101, the source ground of NMOS tube MN101, and the source electrode of NMOS tube MN102 passes through resistance R101 ground connection；The drain electrode of NMOS tube MN101 is connected to the current path being made up of PMOS MP101, and the drain electrode of NMOS tube MN102 is connected to the current path being made up of PMOS MP102, PMOS MP101 and MP102 mirror image each other.The channel width-over-length ratio of NMOS tube MN102 requires the channel width-over-length ratio more than NMOS tube MN101, it addition, the ratio of the channel width-over-length ratio of the channel width-over-length ratio of NMOS tube MN102 and NMOS tube MN101 is N.During work, NMOS tube MN101 and MN102 works in subthreshold region, and the source-drain current of the subthreshold region of NMOS tube has the property that

The formula of the On current being operated in the sub-threshold region of sub-threshold region, MOS transistor and NMOS tube or PMOS due to described 3rd NMOS tube M3 and described 4th NMOS tube M4 is:

$I_D=I_{D0}{\exp }^{\frac{V_{GS}}{m\×V_T}}---\left(1\right);$

Wherein, I_DLeakage current for corresponding MOS transistor；I_D0For the characteristic current of corresponding MOS transistor, I_D0The characteristic current of the nmos pass transistor being directly proportional with the breadth length ratio of the raceway groove of MOS transistor and adopt same process to be formed is a constant and identical；V_GSGate source voltage for MOS transistor；M is the imperfect factor of the subthreshold conduction electric current of metal-oxide-semiconductor transistor；V_TFor thermal voltage, andHaving positive temperature coefficient, T represents absolute temperature, and k is Boltzmann constant, and q is electron charge.

As shown in Figure 1, the voltage difference at resistance R101 two ends is, the gate source voltage V of NMOS tube MN101_GS101Gate source voltage V with NMOS tube MN102_GS102Difference, it may be assumed that

V_R101=V_GS101-V_GS102----------------------(2)；

Make PMOS MP101 and 102 be of the same size, the breadth length ratio of NMOS tube MN101 and NM102 be updated to formula (1) and be updated to formula (2) and can obtain:

$\begin{array}{cc}{V}_{R101}=m\×\frac{k\×T}{q}\×ln& \left(N\right)\end{array}---\left(3\right);$

Flowing through the electric current on R101 is:

It can be seen thatI.e. V_TThere is positive temperature coefficient there is positive temperature coefficient, therefore V_R101And I_R101All there is positive temperature coefficient.

Including NMOS tube NM103, resistance 102 and PMOS MP103 at reference voltage outgoing route, it is equivalently-sized that PMOS MP103 and MP101 forms both mirror image circuit and order.

As shown in Figure 1, the drain electrode link output reference voltage VREF of resistance R102 and PMOS MP103, NMOS tube MN103 works in subthreshold region, if the gate source voltage being not provided with resistance R102, NMOS tube MN103 can work in saturation region more than threshold voltage；After being provided with resistance R102, NMOS tube MN103 can work in subthreshold region, the source-drain current working in the MOS transistor such as NMOS tube or PMOS of pressing threshold region and gate source voltage is utilized all to have the characteristic of negative temperature coefficient, make output reference voltage Positive and Negative Coefficient Temperature offset thus and temperature unrelated, that is: the source-drain current flowing through NMOS tube MN103 has negative temperature characterisitic, and the electric current flowing through PMOS MP103 is I_R101Image current thus having positive temperature characterisitic, both Positive and Negative Coefficient Temperature can be cancelled out each other thus realizing.

Outgoing route in Fig. 1 needs adopt resistance R102, in semiconductor integrated circuit, resistance can take the area that chip is bigger, this can reduce the integrated level of chip thus relatively improving cost, and some cost sensitivity application area requirements is higher, so should phase way reduce circuit area.

Summary of the invention

The technical problem to be solved is to provide a kind of reference voltage source circuit, can reduce area.

For solving above-mentioned technical problem, reference voltage source circuit provided by the invention includes:

Biasing circuit, including the first NMOS tube, second NMOS tube and the first resistance, the channel width-over-length ratio of described second NMOS tube is more than the channel width-over-length ratio of described first NMOS tube, the source ground of described first NMOS tube, the source electrode of described second NMOS tube passes through described first resistance eutral grounding, the drain and gate of described first NMOS tube and the grid of described second NMOS tube all connect the first bias voltage, the drain electrode of described first NMOS tube connects the first current path, the drain electrode of described second NMOS tube connects the second current path, described first current path and described second current path mirror image each other；Described first NMOS tube and described second NMOS tube work in subthreshold region, link at described first resistance and the source electrode of described second NMOS tube provides the first order gate source voltage with positive temperature coefficient poor, and described first order gate source voltage difference is that the gate source voltage between described first NMOS tube and described second NMOS tube is poor.

Gate source voltage difference more than one-level produces circuit, each described gate source voltage difference produces circuit and includes the 3rd NMOS tube, the 4th NMOS tube and the 3rd current path, the source electrode of described 4th NMOS tube connects the drain electrode of described 3rd NMOS tube, the drain and gate of described 4th NMOS tube and the grid of described 3rd NMOS tube link together and are all connected to described 3rd current path, described 3rd current path and described first current path mirror image each other；The channel width-over-length ratio of described 4th NMOS tube is more than the channel width-over-length ratio of described 3rd NMOS tube, it is poor that the source electrode of described 3rd NMOS tube connects previous stage gate source voltage, it is that described first order gate source voltage is poor that the described gate source voltage difference of the first order produces the previous stage gate source voltage difference of circuit, described 3rd NMOS tube and described 4th NMOS tube be all operated in subthreshold region and the drain electrode output of described 3rd NMOS tube have positive temperature coefficient to work as prime gate source voltage poor.

Reference voltage output circuit, including the 5th NMOS tube and the 4th current path；Described 4th current path and described first current path mirror image each other；The grid of described 5th NMOS tube and drain electrode all connect described 4th current path, the drain electrode of described 5th NMOS tube is as the outfan of reference voltage, and the gate source voltage that gate source voltage difference generation circuit described in the source electrode connection afterbody of described 5th NMOS tube exports is poor；Described 5th NMOS tube is operated in sub-threshold region makes the gate source voltage of described 5th NMOS tube have negative temperature coefficient；Described reference voltage is the gate source voltage of described 5th NMOS tube and the sum of described gate source voltage at different levels difference, the characteristic that the gate source voltage utilizing described 5th NMOS tube has a negative temperature coefficient and described gate source voltage difference at different levels has positive temperature coefficient realizes the counteracting of temperature coefficient, makes described reference voltage and temperature unrelated.

Further improve and be, 3rd current path and described 4th current path of described first current path, described second current path, described gate source voltage difference at different levels generation circuit are all made up of a PMOS, and the grid of each PMOS links together and realizes mirror image relationship.

Further improving and be, the 3rd current path of described first current path, described second current path, described gate source voltage difference at different levels generation circuit and the size of current of described 4th current path are equal.

Further improve is that it is two-stage that described gate source voltage difference produces the progression of circuit.

The present invention produces, by adopting the gate source voltage difference being made up of NMOS tube and PMOS, the source voltage that circuit improves the output NMOS tube of reference voltage output circuit, the output NMOS tube making reference voltage output circuit works in subthreshold region, the gate source voltage utilizing the NMOS tube working in pressure threshold region has the gate source voltage difference of negative temperature coefficient and the NMOS tube working in subthreshold region at different levels and has the mutual coefficient realization of positive temperature coefficient and the reference voltage that temperature is unrelated, relative to prior art, the present invention need not adopt resistance in outgoing route, it is thus possible to save resistance make consumption, reduce circuit area.

Additionally, the present invention can also reduce the power consumption of circuit, reason is: the electric current of the reference voltage output circuit of the present invention and gate source voltage difference at different levels produce the electric current of circuit all can flow to the first resistance, and the voltage at the first resistance two ends remains unchanged, namely the electric current of compared to the prior art first resistance of the present invention is dispersed on each bar branch road, reference voltage output circuit and gate source voltage difference at different levels produce circuit will not bring extra power consumption, therefore the present invention can also reduce the power consumption of circuit.

Accompanying drawing explanation

Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:

Fig. 1 is the circuit structure diagram of existing reference voltage source circuit；

Fig. 2 is the circuit structure diagram of embodiment of the present invention reference voltage source circuit.

Detailed description of the invention

As in figure 2 it is shown, be the circuit structure diagram of embodiment of the present invention reference voltage V REF source circuit, embodiment of the present invention reference voltage V REF source circuit includes:

Biasing circuit 1, including the first NMOS tube MN1, second NMOS tube MN2 and the first resistance R1, the channel width-over-length ratio of the described second NMOS tube MN2 channel width-over-length ratio more than described first NMOS tube MN1, the source ground GNDA of described first NMOS tube MN1, the source electrode of described second NMOS tube MN2 passes through described first resistance R1 ground connection GNDA, the drain and gate of described first NMOS tube MN1 and the grid of described second NMOS tube MN2 all connect the first bias voltage NBIAS, the drain electrode of described first NMOS tube MN1 connects the first current path, the drain electrode of described second NMOS tube MN2 connects the second current path, described first current path and described second current path mirror image each other；Described in the embodiment of the present invention, the first current path is made up of PMOS MP1, and described second current path is made up of PMOS MP2.

Described first NMOS tube MN1 and described second NMOS tube MN2 works in subthreshold region, link at the source electrode of described first resistance R1 and described second NMOS tube MN2 provides the first order gate source voltage with positive temperature coefficient poor, and described first order gate source voltage difference is that the gate source voltage between described first NMOS tube MN1 and described second NMOS tube MN2 is poor.

Gate source voltage difference more than one-level produces circuit, each described gate source voltage difference produces circuit and includes the 3rd NMOS tube, the 4th NMOS tube and the 3rd current path, the source electrode of described 4th NMOS tube connects the drain electrode of described 3rd NMOS tube, the drain and gate of described 4th NMOS tube and the grid of described 3rd NMOS tube link together and are all connected to described 3rd current path, described 3rd current path and described first current path mirror image each other；The channel width-over-length ratio of described 4th NMOS tube is more than the channel width-over-length ratio of described 3rd NMOS tube, it is poor that the source electrode of described 3rd NMOS tube connects previous stage gate source voltage, it is that described first order gate source voltage is poor that the described gate source voltage difference of the first order produces the previous stage gate source voltage difference of circuit, described 3rd NMOS tube and described 4th NMOS tube be all operated in subthreshold region and the drain electrode output of described 3rd NMOS tube have positive temperature coefficient to work as prime gate source voltage poor.It is two-stage that gate source voltage difference described in the embodiment of the present invention produces the progression of circuit, respectively as shown in broken box 2a and 2b, described gate source voltage difference produces the 3rd NMOS tube MN3a labelling of circuit 2a, and the 4th NMOS tube MN4a labelling, the 3rd current path is made up of PMOS MP3a；Described gate source voltage difference produces the 3rd NMOS tube MN3b labelling of circuit 2b, and the 4th NMOS tube MN4b labelling, the 3rd current path is made up of PMOS MP3b.

Reference voltage output circuit 3, including the 5th NMOS tube MN5 and the four current path；Described 4th current path and described first current path mirror image each other, in the embodiment of the present invention, the 4th current path is made up of PMOS MP4；The grid of described 5th NMOS tube MN5 and drain electrode all connect described 4th current path, the drain electrode of described 5th NMOS tube MN5 is as the outfan of reference voltage V REF, and the gate source voltage that gate source voltage difference generation circuit described in the source electrode connection afterbody of described 5th NMOS tube MN5 exports is poor；Described 5th NMOS tube MN5 is operated in sub-threshold region makes the gate source voltage of described 5th NMOS tube MN5 have negative temperature coefficient；Described reference voltage V REF is the gate source voltage of described 5th NMOS tube MN5 and the sum of described gate source voltage at different levels difference, the characteristic that the gate source voltage utilizing described 5th NMOS tube MN5 has a negative temperature coefficient and described gate source voltage difference at different levels has positive temperature coefficient realizes the counteracting of temperature coefficient, makes described reference voltage V REF and temperature unrelated.

In the embodiment of the present invention, operation principle illustrates as follows:

For the ease of illustrating that the present invention is by described first current path, described second current path, the size of current of the 3rd current path and described 4th current path that described gate source voltage differences at different levels produce circuit is set to equal, PMOS MP1, MP2, MP3a, the source electrode of MP3b and MP4 is all supply voltage VDDA, grid all links together and connects PBIAS, drain electrode is the outfan of current path, PMOS MP1, MP2, MP3a, the setting of MP3b and MP4 is set to identical, can make described first current path, described second current path, 3rd current path of described gate source voltage differences at different levels generation circuit and the size of current of described 4th current path are equal.

First, comparison diagram 1 with Fig. 2 Suo Shi it can be seen that the biasing circuit 1 of the embodiment of the present invention is identical with available circuit, so having equally: the voltage difference at resistance R1 two ends is, the gate source voltage V of NMOS tube MN1_GS1Gate source voltage V with NMOS tube MN2_GS2Difference, it may be assumed that

V_R1=V_GS1-V_GS2----------------------(2a)；

The ratio making the channel width-over-length ratio of NMOS tube MN2 and the channel width-over-length ratio of NMOS tube MN1 equally is N, this breadth length ratio by NMOS tube MN1 and NM2 and ratio N is updated to formula (1) and is updated to formula (2a) and can obtain:

$\begin{array}{cc}{V}_{R1}=m\×\frac{k\×T}{q}\×ln& \left(N\right)\end{array}---\left(3a\right);$

It can be seen that therefore V_R1There is positive temperature coefficient, V in the embodiment of the present invention_R1First order gate source voltage is poor.

Secondly, gate source voltage difference produce circuit 2a and 2b to each provide other two-stage gate source voltage poor, respectively V_DS3aAnd V_DS3b, wherein V_DS3aSource-drain voltage and V for NMOS tube MN3a_DS3bSource-drain voltage for NMOS tube MN3b.Assuming that the breadth length ratio of NMOS tube MN4a is N1 times of NMOS tube MN3a, the breadth length ratio of NMOS tube MN4b is N2 times of NMOS tube MN3b, then have:

V_DS3aFormula be:

V_DS3a=V_GS3a-V_GS4a----------------------(2b)；

Wherein V_GS3aFor the gate source voltage of NMOS tube MN3a, V_GS4aGate source voltage for NMOS tube MN4a；

As seen from Figure 2, the source-drain current of NMOS tube MN3a is 3 times of the source-drain current of NMOS tube NM4a, this breadth length ratio by NMOS tube MN4a and NM3a and ratio N1 and current ratio 3 is updated to formula (1) accordingly and is updated to formula (2b) and can obtain:

$\begin{array}{cc}{V}_{DS3a}=m\×\frac{k\×T}{q}\×ln& (N1/3)\end{array}---\left(3b\right).$

V_DS3bFormula be:

V_DS3b=V_GS3b-V_GS4b----------------------(2c)；

Wherein V_GS3bFor the gate source voltage of NMOS tube MN3b, V_GS4bGate source voltage for NMOS tube MN4b；

As seen from Figure 2, the source-drain current of NMOS tube MN3b is 2 times of the source-drain current of NMOS tube NM4b, this breadth length ratio by NMOS tube MN4b and NM3b and ratio N1 and current ratio 2 is updated to formula (1) accordingly and is updated to formula (2c) and can obtain:

$\begin{array}{cc}{V}_{DS3b}=m\×\frac{k\×T}{q}\×ln& (N1/2)\end{array}---\left(3c\right).$

As shown in Figure 2, the formula of the reference voltage V REF finally exported is:

VREF=V_R1+V_DS3a+V_DS3b+V_GS5--------------------(4)。

Wherein V_GS5Gate source voltage for NMOS tube MN5.

By formula (4) it can be seen that V_R1, V_DS3a, V_DS3bAll it is operate on the difference of the gate source voltage of two NMOS tube of subthreshold region, there is positive temperature coefficient；And V_GS5Being operate on the gate source voltage of the NMOS tube of subthreshold region, have negative temperature coefficient, both can cancel out each other so that the reference voltage V REF and the temperature that export are unrelated.Relative to the existing structure shown in Fig. 1, the embodiment of the present invention by multistage gate source voltage difference and make the source voltage of NMOS tube MN5 raise and make NMOS tube MN5 work in pressure threshold region, so the embodiment of the present invention can save the resistance R102 shown in the output circuit in a Fig. 1, therefore the embodiment of the present invention can save resistance, it is thus possible to reduce circuit area.

Emulation experiment shows, embodiment of the present invention circuit necessary resistance is 231.5K Europe, and the existing structure shown in Fig. 1 is 1012.9K Europe, so area can be made to greatly reduce.

Additionally, the embodiment of the present invention can also reduce the power consumption of circuit, reason is: known shown in comparison diagram 1 and Fig. 2, the voltage at the first resistance R1 of the present invention and the resistance R101 two ends of existing structure is identical, namely both electric currents are also identical, the gate source voltage difference of the embodiment of the present invention produces circuit 2a, 2b and reference voltage output circuit 3 all can be input in the first resistance R1, namely first the electric current of resistance R1 be dispersed on each bar branch road, reference voltage output circuit and gate source voltage difference at different levels produce circuit will not bring extra power consumption, and the PMOS MP102 in Fig. 1, resistance R102 and NMOS tube MN103 place outgoing route need extra power consumption, therefore the present invention can also reduce the power consumption of circuit.Emulation display, the power consumption of the embodiment of the present invention is: 346.7nA, and the existing structure shown in Fig. 1 is 819.1nA, therefore the power consumption of the embodiment of the present invention is reduced really.

Above by specific embodiment, the present invention is described in detail, but these have not been construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art it may also be made that many deformation and improvement, and these also should be regarded as protection scope of the present invention.

Claims (4)

1. a reference voltage source circuit, it is characterised in that including:

Biasing circuit, including the first NMOS tube, second NMOS tube and the first resistance, the channel width-over-length ratio of described second NMOS tube is more than the channel width-over-length ratio of described first NMOS tube, the source ground of described first NMOS tube, the source electrode of described second NMOS tube passes through described first resistance eutral grounding, the drain and gate of described first NMOS tube and the grid of described second NMOS tube all connect the first bias voltage, the drain electrode of described first NMOS tube connects the first current path, the drain electrode of described second NMOS tube connects the second current path, described first current path and described second current path mirror image each other；Described first NMOS tube and described second NMOS tube work in subthreshold region, link at described first resistance and the source electrode of described second NMOS tube provides the first order gate source voltage with positive temperature coefficient poor, and described first order gate source voltage difference is that the gate source voltage between described first NMOS tube and described second NMOS tube is poor；

Gate source voltage difference more than one-level produces circuit, each described gate source voltage difference produces circuit and includes the 3rd NMOS tube, the 4th NMOS tube and the 3rd current path, the source electrode of described 4th NMOS tube connects the drain electrode of described 3rd NMOS tube, the drain and gate of described 4th NMOS tube and the grid of described 3rd NMOS tube link together and are all connected to described 3rd current path, described 3rd current path and described first current path mirror image each other；The channel width-over-length ratio of described 4th NMOS tube is more than the channel width-over-length ratio of described 3rd NMOS tube, it is poor that the source electrode of described 3rd NMOS tube connects previous stage gate source voltage, it is that described first order gate source voltage is poor that the described gate source voltage difference of the first order produces the previous stage gate source voltage difference of circuit, described 3rd NMOS tube and described 4th NMOS tube be all operated in subthreshold region and the drain electrode output of described 3rd NMOS tube have positive temperature coefficient to work as prime gate source voltage poor；

Reference voltage output circuit, including the 5th NMOS tube and the 4th current path；Described 4th current path and described first current path mirror image each other；The grid of described 5th NMOS tube and drain electrode all connect described 4th current path, the drain electrode of described 5th NMOS tube is as the outfan of reference voltage, and the gate source voltage that gate source voltage difference generation circuit described in the source electrode connection afterbody of described 5th NMOS tube exports is poor；Described 5th NMOS tube is operated in sub-threshold region makes the gate source voltage of described 5th NMOS tube have negative temperature coefficient；Described reference voltage is the gate source voltage of described 5th NMOS tube and the sum of described gate source voltage at different levels difference, the characteristic that the gate source voltage utilizing described 5th NMOS tube has a negative temperature coefficient and described gate source voltage difference at different levels has positive temperature coefficient realizes the counteracting of temperature coefficient, makes described reference voltage and temperature unrelated.

2. reference voltage source circuit as claimed in claim 1, it is characterized in that: the 3rd current path and described 4th current path of described first current path, described second current path, described gate source voltage difference at different levels generation circuit are all made up of a PMOS, and the grid of each PMOS links together and realizes mirror image relationship.

3. reference voltage source circuit as claimed in claim 1 or 2, it is characterised in that: the 3rd current path of described first current path, described second current path, described gate source voltage difference at different levels generation circuit and the size of current of described 4th current path are equal.

4. reference voltage source circuit as claimed in claim 1, it is characterised in that: it is two-stage that described gate source voltage difference produces the progression of circuit.