CN104156026B - Non-bandgap reference source is repaid in the full temperature compensation of a kind of non-resistance - Google Patents

Abstract

The present invention relates to Analogous Integrated Electronic Circuits technical field.Non-bandgap reference source of the present invention, comprises positive temperature coefficient (PTC) current source module, negative temperature parameter current source module, reference voltage generation module, high temperature compensation current generating module and low temp compensating current generating module; Wherein, positive temperature coefficient (PTC) current source module produces an input end of the first biased electrical crimping reference voltage generation module; Positive temperature coefficient (PTC) current source module produces the second bias voltage and connects the first input end of high temperature compensation current generating module and the first input end of low temp compensating current generating module respectively; Negative temperature parameter current source module produces the 3rd bias voltage and connects the second input end of high temperature compensation current generating module and the second input end of low temp compensating current generating module respectively; The output terminal of the output terminal of high temperature compensation current generating module and the output termination reference voltage generation module of low temp compensating current generating module.The present invention can compensate in low-temperature zone and high temperature section reference source circuit respectively.

Description

Non-bandgap reference source is repaid in the full temperature compensation of a kind of non-resistance

Technical field

The invention belongs to Analogous Integrated Electronic Circuits technical field, relate to the full temperature compensation of a kind of non-resistance specifically and repay non-bandgap reference source.

Background technology

At Analogous Integrated Electronic Circuits or composite signal integrated circuits design field, reference voltage source is extremely important and conventional module, often be applied in the Circuits System such as ADC converter, DC-DC parallel operation and power amplifier, its effect is for system provides one not with the voltage reference that temperature and supply voltage change.

Since bandgap voltage reference framework is proposed by Widlar, due to the performance that it is superior, bandgap voltage reference is widely used among a lot of system, and proposes a lot of improvement project for this kind of framework.But along with the further increase of chip system integrated level, low-voltage and low-power consumption become more and more important, but bandgap voltage reference causes power consumption larger owing to usually needing larger electric current, and need in the design process to use diode or BJT transistor to produce PTAT (with PTAT) voltage, but these two kinds of devices all can take larger chip area.Although proposed sub-threshold region reference voltage source for this problem, do not eliminate the nonlinear parameter in circuit completely, and caused the temperature coefficient of output reference voltage larger.

Summary of the invention

Object of the present invention is exactly for above-mentioned traditional benchmark source Problems existing, proposes a kind ofly to repay non-bandgap reference source to the full temperature compensation of non-resistance that reference source circuit proposes to compensate in low-temperature zone and high temperature section respectively.

Technical scheme of the present invention is, non-bandgap reference source is repaid in the full temperature compensation of a kind of non-resistance, comprises positive temperature coefficient (PTC) current source module, negative temperature parameter current source module, reference voltage generation module, high temperature compensation current generating module and low temp compensating current generating module; Wherein, positive temperature coefficient (PTC) current source module produces an input end of the first biased electrical crimping reference voltage generation module; Positive temperature coefficient (PTC) current source module produces the second bias voltage and connects the first input end of high temperature compensation current generating module and the first input end of low temp compensating current generating module respectively; Negative temperature parameter current source module produces the 3rd bias voltage and connects the second input end of high temperature compensation current generating module and the second input end of low temp compensating current generating module respectively; The output terminal of the output terminal of high temperature compensation current generating module and the output termination reference voltage generation module of low temp compensating current generating module;

Described positive temperature coefficient (PTC) current source module is by PMOS MP1, MP2, MP3, and NMOS tube MN1, MN2, MN3, MN4 are formed; Wherein, the source electrode of MP1 meets power vd D, and its grid connects the grid of MP2, and its drain electrode connects the drain electrode of MN1; The grid of MN1 and drain interconnection, its grid connects the grid of MN2, its source ground; The source electrode of MP2 meets power vd D, its grid and drain interconnection, and its drain electrode connects the drain electrode of MN2; The source electrode of MN2 connects the drain electrode of MN3; The grid of MN3 connects the grid of MN4, its source ground; The source electrode of MP3 meets power vd D, and its grid connects the tie point that MP2 drain electrode drains with MN2, and its drain electrode connects the drain electrode of MN4; The source ground of MN4; MP1 grid, MP2 grid leak pole, MN2 drain electrode the first output terminal be connected as positive temperature coefficient (PTC) current source module exports the first bias voltage with MP3 grid; MN3 grid, MN4 grid and MP3 drain electrode the second output terminal be connected as positive temperature coefficient (PTC) current source module export the second bias voltage;

Described negative temperature parameter current source module by PMOS MP5, MP6, NMOS tube MN6, MN7, MN8, DTMOST form; Wherein, the source electrode of MP5 meets power vd D, and its grid connects the grid of MP6, and its drain electrode connects the drain electrode of MN6; The drain electrode of MN6 and gate interconnection, its grid connects the grid of MN7, and its source electrode connects the source electrode of DTMOST; The grid of DTMOST, drain electrode and the equal ground connection of substrate; The source electrode of MP6 meets power vd D, its grid and drain interconnection, and its drain electrode connects the drain electrode of MN7; The source electrode of MN7 connects the drain electrode of MN8; The source ground of MN8, its grid connects the output terminal of reference voltage generation module; The output terminal that MP5 grid, MP6 grid leak pole, MN7 drain electrode connect as negative temperature parameter current source module exports the 3rd bias voltage;

Described reference voltage generation module is by PMOS MP4, and NMOS tube MN5 is formed; Wherein, the source electrode of MP4 connects power supply, and its grid connects the first output terminal of positive temperature coefficient (PTC) current source module, and its drain electrode connects the drain electrode of MN5; The grid of MN5 and drain interconnection, its source ground; MP4 drain electrode, MN5 grid leak pole connect the output terminal output reference voltage as reference voltage generation module;

Described high temperature compensation current generating module is by PMOS MP7, MP8, MP9, and NMOS tube MN9, MN10, MN11 are formed; Wherein, the source electrode of MP7 meets power vd D, and its grid connects the output terminal of negative temperature parameter current source module, and its drain electrode connects the drain electrode of MN9; The grid of MN9 connects the second output terminal of positive temperature coefficient (PTC) current source module, its source ground; The source electrode of MP8 meets power vd D, and its grid connects the grid of MP9, its drain electrode and gate interconnection, and its drain electrode connects the tie point of MP7 drain electrode and MN9 drain electrode; The source electrode of MP9 connects power supply, and its drain electrode connects the drain electrode of MN10; The drain electrode of MN10 and gate interconnection, its grid connects the grid of MN11, its source ground; The drain electrode of MN11 connects the output terminal of reference voltage generation module, its source ground;

Described low temp compensating current generating module is by PMOS MP10, and NMOS tube MN12, MN13, MN14 are formed, and wherein, the source electrode of MP10 meets power vd D, and its grid connects the output terminal of negative temperature parameter current source module, and its drain electrode connects the drain electrode of MN12; The grid of MN12 connects the second output terminal of positive temperature coefficient (PTC) current source module, its source ground; The drain and gate interconnection of MN13, its grid connects the grid of MN14, its source ground; The source ground of MN14, its drain electrode connects the output terminal of reference voltage generation module.

Beneficial effect of the present invention is, can compensate in low-temperature zone and high temperature section reference source circuit respectively, realizes exporting reference source within the scope of total temperature compensating, and obtains the reference source signal of low-temperature coefficient; Do not re-use BJT transistor or diode, chip area reduces greatly simultaneously; Thering is provided can the subzero temperature current source based on dynamic threshold metal-oxide-semiconductor of low pressure applications, and in this benchmark architecture, most of metal-oxide-semiconductor works in sub-threshold region, and the overall power of reference source is reduced greatly.

Accompanying drawing explanation

Fig. 1 is the structural representation of reference source of the present invention;

Fig. 2 is reference voltage generation module schematic diagram of the present invention;

Fig. 3 is that high temperature compensation electric current of the present invention produces schematic diagram;

Fig. 4 is that low temp compensating electric current of the present invention produces schematic diagram;

Fig. 5 is the reference source schematic diagram after full temperature compensation of the present invention is repaid;

Fig. 6 is positive temperature coefficient (PTC) current source module schematic diagram of the present invention;

Fig. 7 is negative temperature parameter current source module schematic diagram of the present invention;

Fig. 8 is high temperature compensation current generating module schematic diagram of the present invention;

Fig. 9 is low temp compensating current generating module schematic diagram of the present invention.

Embodiment

Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described

The present invention proposes the full temperature compensation of a kind of non-resistance and repays non-bandgap reference source, as shown in Figure 1, positive temperature coefficient (PTC) current source module, negative temperature parameter current source module, reference voltage generation module, high temperature compensation current generating module and low temp compensating current generating module is comprised; Wherein, the first bias voltage that positive temperature coefficient (PTC) current source module produces is connected to an input end of reference voltage generation module; The second bias voltage that positive temperature coefficient (PTC) current source module produces is connected respectively to an input end of high/low temperature offset current generation module; The 3rd bias voltage that negative temperature parameter current source module produces is connected respectively to another input end of high/low temperature offset current generation module; The output terminal of high/low temperature offset current is connected to the output terminal of reference voltage generation module.

As shown in Figure 6, positive temperature coefficient (PTC) current source module is by PMOS MP1, MP2, MP3, and NMOS tube MN1, MN2, MN3, MN4 are formed; Wherein, the source electrode of MP1 meets power vd D, and its grid connects the grid of MP2, and its drain electrode connects the drain electrode of MN1; The grid of MN1 and drain interconnection, its grid connects the grid of MN2, its source ground; The source electrode of MP2 meets power vd D, its grid and drain interconnection, and its drain electrode connects the drain electrode of MN2; The source electrode of MN2 connects the drain electrode of MN3; The grid of MN3 connects the grid of MN4, its source ground; The source electrode of MP3 meets power vd D, and its grid connects the tie point that MP2 drain electrode drains with MN2, and its drain electrode connects the drain electrode of MN4; The source ground of MN4; MP1 grid, MP2 grid leak pole, MN2 drain electrode the first output terminal be connected as positive temperature coefficient (PTC) current source module exports the first bias voltage with MP3 grid; MN3 grid, MN4 grid and MP3 drain electrode the second output terminal be connected as positive temperature coefficient (PTC) current source module export the second bias voltage;

As shown in Figure 7, negative temperature parameter current source module by PMOS MP5, MP6, NMOS tube MN6, MN7, MN8, DTMOST form; Wherein, the source electrode of MP5 meets power vd D, and its grid connects the grid of MP6, and its drain electrode connects the drain electrode of MN6; The drain electrode of MN6 and gate interconnection, its grid connects the grid of MN7, and its source electrode connects the source electrode of DTMOST; The grid of DTMOST, drain electrode and the equal ground connection of substrate; The source electrode of MP6 meets power vd D, its grid and drain interconnection, and its drain electrode connects the drain electrode of MN7; The source electrode of MN7 connects the drain electrode of MN8; The source ground of MN8, its grid connects the output terminal of reference voltage generation module; The output terminal that MP5 grid, MP6 grid leak pole, MN7 drain electrode connect as negative temperature parameter current source module exports the 3rd bias voltage;

As shown in Figure 2, reference voltage generation module is by PMOS MP4, and NMOS tube MN5 is formed; Wherein, the source electrode of MP4 connects power supply, and its grid connects the first output terminal of positive temperature coefficient (PTC) current source module, and its drain electrode connects the drain electrode of MN5; The grid of MN5 and drain interconnection, its source ground; MP4 drain electrode, MN5 grid leak pole connect the output terminal output reference voltage as reference voltage generation module;

As shown in Figure 8, high temperature compensation current generating module is by PMOS MP7, MP8, MP9, and NMOS tube MN9, MN10, MN11 are formed; Wherein, the source electrode of MP7 meets power vd D, and its grid connects the output terminal of negative temperature parameter current source module, and its drain electrode connects the drain electrode of MN9; The grid of MN9 connects the second output terminal of positive temperature coefficient (PTC) current source module, its source ground; The source electrode of MP8 meets power vd D, and its grid connects the grid of MP9, its drain electrode and gate interconnection, and its drain electrode connects the tie point of MP7 drain electrode and MN9 drain electrode; The source electrode of MP9 connects power supply, and its drain electrode connects the drain electrode of MN10; The drain electrode of MN10 and gate interconnection, its grid connects the grid of MN11, its source ground; The drain electrode of MN11 connects the output terminal of reference voltage generation module, its source ground;

As shown in Figure 9, low temp compensating current generating module is by PMOS MP10, and NMOS tube MN12, MN13, MN14 are formed, and wherein, the source electrode of MP10 meets power vd D, and its grid connects the output terminal of negative temperature parameter current source module, and its drain electrode connects the drain electrode of MN12; The grid of MN12 connects the second output terminal of positive temperature coefficient (PTC) current source module, its source ground; The drain and gate interconnection of MN13, its grid connects the grid of MN14, its source ground; The source ground of MN14, its drain electrode connects the output terminal of reference voltage generation module.

Principle of work of the present invention is:

Reference voltage generation module is by being operated in the gate source voltage of MN5 of saturation region as reference source (VREF=V _gSMN5).Known by the voltage-current characteristic of saturation region MOS

$I_{\mathrm{MN}5}=I_D=\frac{1}{2}\mathrm{\μ}{C}_{\mathrm{OX}}{S}_{\mathrm{MN}5}{(V_{\mathrm{GS}\left(\mathrm{MN}5\right)}-V_{\mathrm{TH}})}^{^2}$

Can obtain output reference voltage source is

$\mathrm{VREF}=V_{\mathrm{GS}\left(\mathrm{MN}5\right)}=\sqrt{\frac{2I_D}{\mathrm{\μ}{C}_{\mathrm{OX}}{S}_{\mathrm{MN}5}}}+V_{\mathrm{TH}}$

Wherein μ is channel carrier mobility; C _oXfor the gate oxide capacitance of unit area; S _n=(W/L) _nfor MOS breadth length ratio, subscript n is the label of referred to metal-oxide-semiconductor; V _{gS (p)}for the gate source voltage of metal-oxide-semiconductor is poor, subscript p is by being referred to metal-oxide-semiconductor; V _tHfor the threshold voltage of NMOS tube.The first bias voltage that the grid of MP4 is produced by positive temperature coefficient (PTC) current source module is biased, and produces positive temperature electric current I _d, suppose I _dfor proportional with temperature, as shown in the formula:

I _D(T)＝I _D0·[1+b _ID·(T-T ₀)]

Wherein, T ₀for reference temperature, b _iDfor I _dtemperature coefficient, T is arbitrary temperature, I _d0for T ₀current value during temperature.

Due to v _tH=V _tH0-a _vT(T-T ₀).U _ofor T ₀electron mobility during temperature; The temperature power number that m (m representative value is 1.5) is carrier mobility; V _tH0for T ₀threshold voltage during temperature; a _vTfor V _tHtemperature coefficient.Obtain not temperature variant benchmark, can make: Δ V _gSMN5=V _gS(T ₀+ Δ T)-V _gS(T ₀)=0, by I _d, μ, V _tHexpression formula substitute into above formula, and by T ₀taylor series expansion single order equivalent process is done at place, can obtain following formula

$\sqrt{\frac{I_{D0}}{2{\mathrm{\μ}}_0{C}_{\mathrm{OX}}{S}_{\mathrm{MN}5}}}(b_{\mathrm{ID}}+\frac{m}{T_0})=a_{\mathrm{VT}}$

From above formula, by controlling electric current I _dtemperature coefficient, the size of current value and the channel width-over-length ratio of MN5 pipe, can obtain temperature coefficient is in theory the reference source of zero.Because above formula is at T ₀the result that the Taylor expansion at temperature place obtains, so only at T ₀temperature place can obtain zero-temperature coefficient, and cannot obtain zero temperature or less temperature coefficient within the scope of total temperature, the waveform that benchmark exports as shown in solid lines in fig. 5.Propose a kind of full temperature compensation herein and repay thought, the positive temperature electric current I utilizing positive temperature coefficient (PTC) current source module to produce ₁, and the subzero temperature electric current I that negative temperature parameter current source module produces ₂, produce nonlinear compensation electric current I at high and low temperature compensation point TH and TL respectively _nL, as shown in Figure 3 and Figure 4.Among the metal-oxide-semiconductor MN5 of high and low temperature compensation point from output reference voltage, extract nonlinear compensation electric current I NL, thus obtain the reference source that full temperature compensation repays, as shown in phantom in Figure 5.

In positive temperature coefficient (PTC) current source module, MP1, MP2, MN1, MN2, MN3 form Self-bias Current source structure, MP1, MP2, MP3, MN1, MN2 are operated in sub-threshold region, MN4 works in saturation region, and provide biased for MN3 grid, MN3 works in linear zone, is equivalent to resistance R in automatic biasing structure _l1, can be obtained by linear zone current-voltage correlation

$R_{L1}=\frac{1}{\mathrm{\μ}{C}_{\mathrm{OX}}{S}_{\mathrm{MN}3}(V_{\mathrm{GSMN}3}-V_{\mathrm{TH}})}$

Suppose that automatic biasing structure generation current is I ₁, the image ratio of MP2 and MP1, MP3 is 1:1:1.Because MN4 is operated in saturation region, known by the voltage-current characteristic of saturation region MOS

$V_{\mathrm{GSMN}4}=\sqrt{\frac{{2I}_1}{\mathrm{\μ}{C}_{\mathrm{OX}}{S}_{\mathrm{MN}4}}}+V_{\mathrm{TH}}$

Due to V _gSMN4=V _gSMN3, can be obtained by above two formulas

$R_{L1}=\frac{1}{S_{\mathrm{MN}3}\sqrt{\frac{2I_1\mathrm{\μ}{C}_{\mathrm{OX}}}{S_{\mathrm{MN}4}}}}$

Because MN1, MN2 pipe works in sub-threshold region, from the voltage-current characteristic of sub-threshold region MOS

$I_{\mathrm{MN}2}=\mathrm{\μ}{C}_{\mathrm{OX}}{V_T}^2{S}_{\mathrm{MN}2}\exp \left(\frac{V_{\mathrm{GSMN}2}-V_{\mathrm{TH}}}{n{V}_T}\right)$

$I_{\mathrm{MN}1}=\mathrm{\μ}{C}_{\mathrm{OX}}{V_T}^2{S}_{\mathrm{MN}1}\exp \left(\frac{V_{\mathrm{GSMN}1}-V_{\mathrm{TH}}}{n{V}_T}\right)$

Wherein, k is Boltzmann constant, and q is the electricity of unit charge; N is sub-threshold slope, is temperature independent constant coefficient.I in the present invention _mN2=I _mN1, the drain-source voltage that can be obtained MN3 by above two formulas is

$V_{\mathrm{DS}3}=V_{\mathrm{GSMN}1}-V_{\mathrm{GSMN}2}=n{V}_T\ln \left(\frac{S_{\mathrm{MN}2}}{S_{\mathrm{MN}1}}\right)$

Thus can obtain

$I_1=\frac{V_{\mathrm{DS}3}}{R_{L1}}=K_1{V_T}^2\mathrm{\μ}$

Wherein, from above formula, I ₁∝ T ^0.5, I ₁it is a positive temperature electric current.

In negative temperature parameter current source module, MP5, MP6, MN6, MN7, MN8, DTMOST form Self-bias Current source structure, and wherein MP5, MP6, MN6, MN7 work in sub-threshold region; MN8 works in linear zone, and MN8 grid is biased by reference source VREF, is equivalent to resistance R in automatic biasing structure _l2, can be obtained by linear zone current-voltage correlation

$R_{L2}=\frac{1}{\mathrm{\μ}{C}_{\mathrm{OX}}{S}_{\mathrm{MN}8}(\mathrm{VREF}-V_{\mathrm{TH}})}$

VREF is substituted into above formula have

$R_{L2}=\sqrt{\frac{S_{\mathrm{MN}5}}{2I_1\mathrm{\μ}{C}_{\mathrm{OX}}{S}_{\mathrm{MN}8}^2}}$

Due to I ₁∝ T ^0.5, so R _l2∝ T ^0.5, that is: R _l2be directly proportional to temperature.

Suppose that automatic biasing structure generation current is I ₂, the image ratio of MP5 and MP6 is that the breadth length ratio of 1:1, MN6 and MN7 is equal, so the drain-source voltage V of MN8 _dSMN8difference equals the voltage difference V of DTMOST source and drain terminal _bEDTMOST.Electric current I ₂for the source of DTMOST and the voltage difference V of drain terminal _bEDTMOSTcharacteristic and diode characteristic similar, but there is less forward voltage and temperature characterisitic, therefore V _bEDTMOSTcan Approximate Equivalent be a single order negative temperature item.So electric current I ₂it is a subzero temperature electric current.

In high temperature compensation current generating module, MP7 mirror image subzero temperature electric current I ₂, output current I _b; The positive temperature electric current I of MN9 mirror image ₁, output current I _a.By controlling electric current I _bwith I _arelative size, the temperature value TH of high temperature compensation point can be adjusted; By the image ratio of MN11 and MN10, offset current I can be adjusted _nLsize, as shown in Figure 2, thus high temperature compensation is carried out to reference source.

In low temp compensating current generating module, MP10 mirror image subzero temperature electric current I ₂, output current I _d; The positive temperature electric current I of MN12 mirror image ₁, output current I _c.By controlling electric current I _dwith I _crelative size, the temperature value TL of low temp compensating point can be adjusted; By the image ratio of MN13 and MN14, offset current I can be adjusted _nLsize, as shown in Figure 4 and Figure 5, thus low temp compensating is carried out to reference source.

Claims (1)

1. a non-bandgap reference source is repaid in the full temperature compensation of non-resistance, comprises positive temperature coefficient (PTC) current source module, negative temperature parameter current source module, reference voltage generation module, high temperature compensation current generating module and low temp compensating current generating module; Wherein, positive temperature coefficient (PTC) current source module produces an input end of the first biased electrical crimping reference voltage generation module; Positive temperature coefficient (PTC) current source module produces the second bias voltage and connects the first input end of high temperature compensation current generating module and the first input end of low temp compensating current generating module respectively; Negative temperature parameter current source module produces the 3rd bias voltage and connects the second input end of high temperature compensation current generating module and the second input end of low temp compensating current generating module respectively; The output terminal of the output terminal of high temperature compensation current generating module and the output termination reference voltage generation module of low temp compensating current generating module;

Described positive temperature coefficient (PTC) current source module is by PMOS MP1, MP2, MP3, and NMOS tube MN1, MN2, MN3, MN4 are formed; Wherein, the source electrode of MP1 meets power vd D, and its grid connects the grid of MP2, and its drain electrode connects the drain electrode of MN1; The grid of MN1 and drain interconnection, its grid connects the grid of MN2, its source ground; The source electrode of MP2 meets power vd D, its grid and drain interconnection, and its drain electrode connects the drain electrode of MN2; The source electrode of MN2 connects the drain electrode of MN3; The grid of MN3 connects the grid of MN4, its source ground; The source electrode of MP3 meets power vd D, and its grid connects the tie point that MP2 drain electrode drains with MN2, and its drain electrode connects the drain electrode of MN4; The source ground of MN4; MP1 grid, MP2 grid leak pole, MN2 drain electrode the first output terminal be connected as positive temperature coefficient (PTC) current source module exports the first bias voltage with MP3 grid; MN3 grid, MN4 grid and MP3 drain electrode the second output terminal be connected as positive temperature coefficient (PTC) current source module export the second bias voltage;

Described negative temperature parameter current source module by PMOS MP5, MP6, NMOS tube MN6, MN7, MN8, DTMOST form; Wherein, the source electrode of MP5 meets power vd D, and its grid connects the grid of MP6, and its drain electrode connects the drain electrode of MN6; The drain electrode of MN6 and gate interconnection, its grid connects the grid of MN7, and its source electrode connects the source electrode of DTMOST; The grid of DTMOST, drain electrode and the equal ground connection of substrate; The source electrode of MP6 meets power vd D, its grid and drain interconnection, and its drain electrode connects the drain electrode of MN7; The source electrode of MN7 connects the drain electrode of MN8; The source ground of MN8, its grid connects the output terminal of reference voltage generation module; The output terminal that MP5 grid, MP6 grid leak pole, MN7 drain electrode connect as negative temperature parameter current source module exports the 3rd bias voltage;

Described reference voltage generation module is by PMOS MP4, and NMOS tube MN5 is formed; Wherein, the source electrode of MP4 connects power supply, and its grid connects the first output terminal of positive temperature coefficient (PTC) current source module, and its drain electrode connects the drain electrode of MN5; The grid of MN5 and drain interconnection, its source ground; MP4 drain electrode, MN5 grid leak pole connect the output terminal output reference voltage as reference voltage generation module;

Described high temperature compensation current generating module is by PMOS MP7, MP8, MP9, and NMOS tube MN9, MN10, MN11 are formed; Wherein, the source electrode of MP7 meets power vd D, and its grid connects the output terminal of negative temperature parameter current source module, and its drain electrode connects the drain electrode of MN9; The grid of MN9 connects the second output terminal of positive temperature coefficient (PTC) current source module, its source ground; The source electrode of MP8 meets power vd D, and its grid connects the grid of MP9, its drain electrode and gate interconnection, and its drain electrode connects the tie point of MP7 drain electrode and MN9 drain electrode; The source electrode of MP9 connects power supply, and its drain electrode connects the drain electrode of MN10; The drain electrode of MN10 and gate interconnection, its grid connects the grid of MN11, its source ground; The drain electrode of MN11 connects the output terminal of reference voltage generation module, its source ground;

Described low temp compensating current generating module is by PMOS MP10, and NMOS tube MN12, MN13, MN14 are formed, and wherein, the source electrode of MP10 meets power vd D, and its grid connects the output terminal of negative temperature parameter current source module, and its drain electrode connects the drain electrode of MN12; The grid of MN12 connects the second output terminal of positive temperature coefficient (PTC) current source module, its source ground; The drain and gate interconnection of MN13, its grid connects the grid of MN14, and its drain electrode connects the drain electrode of PMOS MP10 drain electrode and NMOS tube MN12, its source ground; The source ground of MN14, its drain electrode connects the output terminal of reference voltage generation module.