CN104881071A - Low-power reference voltage source - Google Patents

Abstract

The invention belongs to the technical field of integrated circuits and relates to a low-power reference voltage source comprising a three-stage amplifier circuit composed of an enhanced MOS (metal oxide semiconductor) transistor and a depletion NMOS (N-channel metal oxide semiconductor) transistor and a start circuit; a three-stage amplifier comprises a primary amplifier circuit, a secondary amplifier circuit and a tertiary amplifier circuit. The low-power reference voltage source is characterized in that the voltage of an output end VREF is irrelevant to power source voltage VDD and never changes with VDD changes; according to the feature that a threshold of the enhanced MOS transistor is opposite to that of the depletion NMOS transistor in temperature, circuit running current is very low, and the static power consumption is very low. The low-power reference voltage source with the combination of the deletion NMOS transistor and the enhanced MOS transistor is high in precision and low in power consumption and never changes with changes in the power source voltage and temperature.

Description

Low-power-consumptioreference reference voltage source

Technical field

The invention belongs to technical field of integrated circuits, relate to a kind of Low-power-consumptioreference reference voltage source.

Background technology

As everyone knows, relate in the scheme of Analog Circuit Design all, all can have a reference voltage source circuit, for other modules in chip provide the stable voltage source not with supply voltage and temperature variation.General sampled reference voltage source is bandgap voltage reference structure at present, but power consumption is often larger, and about tens uA, are difficult to the requirement meeting low power dissipation design (power consumption is less than 0.5uA).If reduce power consumption, the resistance of high value and large-sized metal-oxide-semiconductor must be used, will certainly chip area be increased.

As reference voltage source, although band gap reference voltage source circuit can provide a stable reference voltage, also there is intrinsic defect in prior art many employings band gap voltage:

1. include operational amplifier in bandgap voltage reference, general about tens uA of this structure power consumption, cannot realize low-power consumption;

2. the operational amplifier in bandgap voltage reference and triode and high resistance measurement can take very large area, are unfavorable for highly integrated low cost solution;

Summary of the invention

The object of the present invention is to provide a kind of Low-power-consumptioreference reference voltage source.It while providing the reference voltage not with supply voltage and temperature variation, can achieve the super low-power consumption lower than 0.5uA.

For solving the problems of the technologies described above, embodiments of the invention provide technical scheme as follows:

Low-power-consumptioreference reference voltage source comprises: the three-stage amplifier circuit be made up of enhancement mode metal-oxide-semiconductor and depletion type NMOS tube and start-up circuit;

Described first order amplifier is the first enhancement mode NMOS commonsource amplifier circuit, and the first PMOS of grid leak short circuit and the 3rd PMOS are connected and as amplifier load, a PMOS drain electrode is as output terminal;

The common source and common grid amplifier circuit that described second level amplifier circuit is made up of the second PMOS and the 4th PMOS, the grid of the second PMOS inputs and connects the output of first order amplifier, first depletion type NMOS tube of grid source short circuit is as amplifier load, and the 4th PMOS drain electrode is output terminal;

The common source and common grid amplifier circuit that described third level amplifier circuit is made up of the 5th PMOS and the 6th PMOS, 5th PMOS grid inputs and connects the output of second level amplifier, second depletion type NMOS tube of grid source short circuit is as amplifier load, second depletion type NMOS drain electrode is circuit output end VREF and receives the input end of first order amplifier, and output terminal VREF connection is to the compensation of GND and filtering first electric capacity.

Start-up circuit provides starting current for third stage amplifier, is made up of the 7th PMOS and the 8th PMOS and the 3rd depletion type NMOS tube; 7th gate pmos very input end, it receives first order amplifier out, 3rd depletion type NMOS tube of grid source short circuit is as the load of the 7th PMOS, 8th PMOS grid is connected to the drain electrode of the 7th PMOS, 8th PMOS source electrode meets VDD, drain electrode is connected to first order amp.in, for first order amplifier provides the starting current of a pull-up.

The present invention, owing to have employed above-mentioned technical scheme, makes it compared with prior art, has following advantage and good effect:

1. the present invention replaces high resistance measurement owing to adopting depletion type MOS tube, and the conducting resistance of the depletion type MOS tube of grid source short circuit is very big, realizing circuit extremely low power dissipation;

2. the present invention is owing to adopting enhancement mode metal-oxide-semiconductor and depletion type MOS tube, and its threshold value has contrary temperature characterisitic, can obtain the reference voltage value of Low Drift Temperature;

3. the present invention is not owing to using high resistance measurement and operational amplifier, and chip area is very little, is conducive to the high integration of realizing circuit.

Accompanying drawing explanation

Fig. 1 is a kind of embodiment circuit theory diagrams in Low-power-consumptioreference reference voltage source of the present invention.

Embodiment

As shown in Figure 1, Low-power-consumptioreference reference voltage source of the present invention comprises: enhancement mode NMOS tube N1, enhancement mode PMOS P1 ~ P7, depletion type NMOS tube D1 ~ D2 and building-out capacitor C1, first PMOS P1, second PMOS P2, 5th PMOS P5, the source of the 7th PMOS P7 meets power vd D, the grid end of P1 is with drain terminal short circuit and be connected P2, the grid end of P7 and the source of the 3rd PMOS P3, the drain terminal of P2 connects the source of the 4th PMOS P4, the grid end of P3 is with drain terminal short circuit and be connected the grid end of P4 and P6 and the drain terminal of N1, the source ground connection of the first enhancement mode NMOS tube N1, the drain terminal of P4 connects the drain terminal of the first depletion type NMOS tube D1 and the grid end of P5, the grid end of the first depletion type NMOS tube D1 and the second depletion type NMOS tube D2 and source short circuit also hold GND with being connected to, P5 drain terminal connects the source of the 6th PMOS P6, the drain terminal of P6 meets grid end and the D2 of N1, building-out capacitor C1 anode and output terminal VREF, the negative terminal of C1 meets GND.

Source electrode and the grid of described 7th PMOS are connected power end and ground respectively, and between the drain electrode that starting resistance is connected to the 7th PMOS and ground, the drain electrode of described 7th PMOS connects the grid of the first enhancement mode NMOS tube

This circuit can be divided into two parts: the reference voltage source main circuit that Part I is made up of P1 ~ P6 and N1, D1, D2 and C1; The start-up circuit that Part II is made up of P7 and starting resistance R.Principle of work of the present invention is:

Part I circuit: achieve the output obtaining reference voltage source at output terminal VREF, be made up of third stage amplifier: the NMOS commonsource amplifier that the first order is made up of P1, P3 and N1; The PMOS common source and common grid amplifier that the second level is made up of P2, P4 and D1; The PMOS common source and common grid amplifier that the third level is made up of P5, P6 and D2.The output vref signal of the 3rd pole is connected to again the input of the first order, defines a feedback loop, can strengthen the stability of output reference voltage VREF.Every one-level have employed the cascode structure of two PMOS, improves loop voltage enlargement factor and Power Supply Rejection Ratio.The effect of electric capacity C1 is the stability improving loop.The voltage computation process of VREF is:

As shown in Figure 1, the voltage of output terminal VREF equals the gate source voltage of N1 pipe, namely

VREF=Vgsn1 (formula 3)

Because P1 and P2 constitutes current source circuit, therefore first order amplifier is identical with the electric current of second level amplifier, namely

I _n1=I _d1(formula 4)

Because N1 and D1 is operated in saturation region, therefore

$I_{n1}=\frac{1}{2}{\mathrm{uc}}_{ox}{(W/L)}_{n1}{(Vgsn1-Vthn1)}^2$ (formula 5)

$I_{d1}=\frac{1}{2}{\mathrm{uc}}_{ox}{(W/L)}_{d1}{\left(Vthd1\right)}^2$ (formula 6)

Wherein, u represents carrier mobility, and Cox represents gate oxide capacitance, and formula 5, formula 6 are substituted into formula 4 and obtain

$Vgsn1=\sqrt{\frac{{(W/L)}_{d1}}{{(W/L)}_{n1}}}\left|Vthd1\right|+Vthn1$ (formula 7)

Formula 7 is substituted into formula 3 obtain

$VREF=\sqrt{\frac{{(W/L)}_{d1}}{{(W/L)}_{n1}}}\left|Vthd1\right|+Vthn1$ (formula 8)

As can be seen from formula 8, output reference voltage VREF is only relevant with the threshold voltage of N1 and D1 and breadth length ratio (W/L), has nothing to do with supply voltage.Make VREF not with temperature change, the result of formula 8 pairs of temperature differentiates should be 0, can obtain

$\frac{\∂VREF}{\∂T}=\sqrt{\frac{{(W/L)}_{d1}}{{(W/L)}_{n1}}}\frac{\∂\left|Vthd1\right|}{\∂T}+\frac{\∂Vthn1}{\∂T}=0$ (formula 9)

Because CMOS technology limited, the threshold voltage exhausting pipe D1 in formula 9 | Vthd1| is positive temperature coefficient (PTC) value, and the threshold voltage vt hn1 of enhancement mode pipe N1 is negative temperature coefficient value, therefore be normal number, be negative constant, can be obtained by formula 9,

$\sqrt{\frac{{(W/L)}_{d1}}{{(W/L)}_{n1}}}=-\left(\frac{\∂Vthn1}{\∂T}\right)/\left(\frac{\∂\left|Vthd1\right|}{\∂T}\right)$ (formula 10)

Therefore, as long as (W/L) ratio of D1 and N1 meets formula 10 requirement, the magnitude of voltage of VREF just can be made not vary with temperature, realize accurate reference voltage and export.

Due to the voltage source that this reference voltage source generating circuit is an automatic biasing, it has two functioning equalization points, and one is zero point, and another is non-zero points, and namely circuit loop can be stabilized in the magnitude of voltage of zero voltage value or a non-zero.When normally working to make circuit, functioning equalization point is non-zero points, and must add start-up circuit is circuit Injection Current, therefore just needs the Part II circuit in this circuit, i.e. start-up circuit.

The principle of work of start-up circuit is: after VDD powers on, the grounded-grid conducting of P7, is N1 gate charges by starting resistance R, and when N1 grid voltage rises to the cut-in voltage of NMOS tube, N1 conducting, circuit starts normal work.

The power consumption of whole electric current is made up of the working current of third stage amplifier and start-up circuit.And the working current of every grade is determined by the pipe that exhausts of grid source short circuit, wherein the first order and second level amplifier operation electric current are determined by the breadth length ratio of D1, third level amplifier operation electric current is determined by the breadth length ratio of D2, and the working current of start-up circuit is determined by the resistance of starting resistance R3.As long as select little breadth length ratio, just minimum working current can be obtained.The design is the current limit of every one-level at 0.1uA, and therefore the overall power of circuit is less than 0.5uA.

Above-described embodiment only illustrates technical conceive of the present invention and feature, its objective is and is person skilled in the art can be understood content of the present invention and implement according to this, can not limit the scope of the invention with this.All equivalences done according to Spirit Essence of the present invention change or modify, and as third stage amplifier become two-stage or common source and common grid amplifier being become common common-source amplifier, all should be encompassed within protection category of the present invention.

In sum, Low-power-consumptioreference reference voltage source circuit of the present invention, the voltage of output terminal VREF and supply voltage VDD have nothing to do, enhancement mode pipe is utilized to have contrary temperature characterisitic with the threshold value of depletion type pipe, the voltage of VREF is not changed with temperature, utilize the great feature of conducting resistance of the depletion type NMOS tube of grid source short circuit, make circuit have extremely low quiescent dissipation.Whole circuit area is very little, and the height being conducive to circuit is integrated.

Claims (4)

1. Low-power-consumptioreference reference voltage source, comprising: the three-stage amplifier circuit be made up of enhancement mode metal-oxide-semiconductor and depletion type NMOS tube and start-up circuit; Described three-stage amplifier circuit comprises: first order amplifier circuit, second level amplifier circuit and third level amplifier circuit;

Described first order amplifier is the first enhancement mode NMOS commonsource amplifier circuit, and the first PMOS of grid leak short circuit and the 3rd PMOS are connected and as amplifier load, a PMOS drain electrode is as output terminal; First enhancement mode NMOS tube connects the 3rd PMOS drain electrode, and described start-up circuit is for opening the first enhancement mode NMOS tube;

The common source and common grid amplifier circuit that described second level amplifier circuit is made up of the second PMOS and the 4th PMOS, the grid of the second PMOS inputs and connects the output of first order amplifier, first depletion type NMOS tube of grid source short circuit is as amplifier load, and the 4th PMOS drain electrode is output terminal;

The common source and common grid amplifier circuit that described third level amplifier circuit is made up of the 5th PMOS and the 6th PMOS, 5th PMOS grid inputs and connects the output terminal of second level amplifier, second depletion type NMOS tube of grid source short circuit is as amplifier load, second depletion type NMOS drain electrode is circuit output end, and receives the input end of first order amplifier.

2. Low-power-consumptioreference reference voltage source as claimed in claim 1, it is characterized in that, described start-up circuit is made up of the 7th PMOS and starting resistance, source electrode and the grid of described 7th PMOS are connected power end and ground respectively, between the drain electrode that starting resistance is connected to the 7th PMOS and ground, the drain electrode of described 7th PMOS connects the grid of the first enhancement mode NMOS tube.

3. Low-power-consumptioreference reference voltage source as claimed in claim 1, is characterized in that: the breadth length ratio of described first depletion type NMOS tube and the first enhancement mode NMOS tube meets the requirement of formula 1,

(formula 1)

In formula 1, be the breadth length ratio of the first depletion type NMOS tube, be the breadth length ratio of the first enhancement mode NMOS tube, Vthd1 is the threshold voltage of depletion type NMOS tube, and Vthn1 is the threshold voltage of enhancement mode NMOS tube, and T represents temperature.

4. Low-power-consumptioreference reference voltage source as claimed in claim 1, is characterized in that, described second depletion type NMOS drain electrode is also connected with the building-out capacitor on ground.