CN204576336U - Reference voltage source circuit - Google Patents

Abstract

The utility model provides a kind of reference voltage source circuit, and it comprises the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, feedback voltage sample circuit and reference voltage output end.The drain electrode of the 3rd metal-oxide-semiconductor is all connected with node O with the drain electrode of the second metal-oxide-semiconductor, the grid of the 3rd metal-oxide-semiconductor is connected with the grid of the second metal-oxide-semiconductor, the source electrode of the 3rd metal-oxide-semiconductor is connected with the grid of the 3rd metal-oxide-semiconductor, and the source electrode of the second metal-oxide-semiconductor is connected with reference voltage output end, and node O is connected with the first voltage end; The drain electrode of the first metal-oxide-semiconductor is connected with the source electrode of the 3rd metal-oxide-semiconductor, and the source electrode of the first metal-oxide-semiconductor is connected with the second voltage end.The input end of feedback voltage sample circuit is connected with reference voltage output end, its output terminal is connected with the grid of the first metal-oxide-semiconductor, feedback voltage sample circuit is used for the reference voltage that sampled reference voltage output end exports, and gives the grid of the first metal-oxide-semiconductor with output feedack voltage.Compared with prior art, the utility model just can provide stable reference voltage without the need to manufacturing special bipolar transistor.

Description

Reference voltage source circuit

[technical field]

The utility model relates to reference voltage techniques field, particularly a kind of reference voltage source circuit.

[background technology]

In mimic channel, often need reference voltage source circuit to provide reference voltage for other circuit, wish that the reference voltage exported is relatively more accurate, the change with supply voltage, temperature, technique is all less.In prior art, usually reference voltage is provided by band-gap reference (Bandgap Refrrence) potential circuit, its principle is the base band band gap voltage depending on semiconductor material, such as, stable reference voltage is produced by being added with certain proportion by the voltage △ Vbe (△ Vbe=Vbe2-Vbe1) of positive temperature coefficient (PTC) and the voltage Vbe (Vbe=Vbe2) of negative temperature coefficient, wherein, Vbe1 is the base emitter voltage of bipolar transistor Q1, Vbe2 is the base emitter voltage of bipolar transistor Q2, that is, design is needed to comprise the band-gap reference circuit of special bipolar transistor in order to obtain stable reference voltage.But do not have bipolar transistor in need in some technique, in order to provide required bipolar transistor especially, may need extra lithography step, this will increase the manufacturing cost of chip.

Therefore, be necessary to provide a kind of technical scheme of improvement to solve the problems referred to above.

[utility model content]

The purpose of this utility model is to provide a kind of reference voltage source circuit, and it just can provide stable reference voltage without the need to manufacturing special bipolar transistor, and circuit structure of the present utility model is simple, and shared chip area is less.

In order to solve the problem, the utility model provides a kind of reference voltage source circuit, and it comprises the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, feedback voltage sample circuit and reference voltage output end.Wherein, the drain electrode of the 3rd metal-oxide-semiconductor is all connected with node O with the drain electrode of the second metal-oxide-semiconductor, the grid of the 3rd metal-oxide-semiconductor is connected with the grid of the second metal-oxide-semiconductor, the source electrode of the 3rd metal-oxide-semiconductor is connected with the grid of the 3rd metal-oxide-semiconductor, the source electrode of the second metal-oxide-semiconductor is connected with reference voltage output end, and node O is connected with the first voltage end; The drain electrode of the first metal-oxide-semiconductor is connected with the source electrode of the 3rd metal-oxide-semiconductor, and the source electrode of the first metal-oxide-semiconductor is connected with the second voltage end.The input end of described feedback voltage sample circuit is connected with described reference voltage output end, its output terminal is connected with the grid of described first metal-oxide-semiconductor, the reference voltage that described feedback voltage sample circuit exports for described reference voltage output end of sampling, gives the grid of described first metal-oxide-semiconductor with output feedack voltage.

Further, reference voltage source circuit also comprises the electric capacity between the output terminal being connected to described reference voltage output end and feedback voltage sample circuit.

Further, reference voltage source circuit also comprises the 4th metal-oxide-semiconductor, and the drain electrode of described 4th metal-oxide-semiconductor is connected with described first pressure side, and its grid is connected with its source electrode, and its source electrode is connected with node O.

Further, described feedback voltage sample circuit comprises the second resistance and the first resistance that are series at reference voltage output end and the second voltage end, and the connected node between described first resistance and the second resistance adopts the output terminal of circuit as described feedback voltage.

Further, described first metal-oxide-semiconductor is enhancement mode nmos pass transistor, described 3rd metal-oxide-semiconductor is depletion type nmos transistor, described second metal-oxide-semiconductor is enhancement mode nmos pass transistor or depletion type nmos transistor, described first voltage end is power end, described second voltage end is earth terminal, described first power supply termination positive input voltage, and described reference voltage output end exports positive reference voltage.

Further, described 4th metal-oxide-semiconductor is depletion type nmos transistor.

Further, described first metal-oxide-semiconductor is enhancement mode PMOS transistor, described second metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor are depletion type PMOS transistor, described first voltage end is power end, described second voltage end is earth terminal, described first power supply termination negative input voltage, described reference voltage output end exports negative reference voltage.

Further, described 4th metal-oxide-semiconductor is depletion type PMOS transistor.

Further, described first resistance and the second resistance are the resistance of identical type, and temperature coefficient is identical.

Further, the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor meet following formula:

$\mathrm{VgsN}1=\mathrm{VTN}1+\sqrt{\frac{{\left(\frac{W}{L}\right)}_{N3}}{{\left(\frac{W}{L}\right)}_{N1}}}.\left(\right|\mathrm{VTN}3\left|\right)---\left(5\right)$

Wherein, VgsN1 is the gate source voltage of the first nmos pass transistor pipe, be the breadth length ratio of the first nmos pass transistor, VTN1 is the threshold voltage of the first nmos pass transistor pipe, be the breadth length ratio of the 3rd nmos pass transistor, VTN3 is the threshold voltage of the 3rd nmos pass transistor,

VTN1 be negative temperature coefficient on the occasion of, | VTN3| be positive temperature coefficient (PTC) on the occasion of, according to VTN1 and | the temperature coefficient ratio of VTN3|, determine

Further, the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor meet following formula:

$\left|\mathrm{VgsP}1\right|=\left|\mathrm{VTP}1\right|+\sqrt{\frac{{\left(\frac{W}{L}\right)}_{P3}}{{\left(\frac{W}{L}\right)}_{P1}}}.\left(\right|\mathrm{VTP}3\left|\right)---\left(6\right)$

Wherein, VgsP1 is the gate source voltage of the first PMOS transistor, be the breadth length ratio of the first PMOS transistor, VTP1 is the threshold voltage of the first PMOS transistor, be the breadth length ratio of the 3rd PMOS transistor, VTP3 is the threshold voltage of the 3rd PMOS transistor,

| VTP1| be negative temperature coefficient on the occasion of, | VTP3| be positive temperature coefficient (PTC) on the occasion of, according to | VTP1| and | the temperature coefficient ratio of VTP3|, determine

Compared with prior art, reference voltage source circuit of the present utility model forms negative feedback loop by multiple metal-oxide-semiconductor, regulates with the reference voltage exported reference voltage output end, thus the reference voltage of stable output.Because the reference voltage source circuit in the utility model just can provide stable reference voltage without the need to manufacturing special bipolar transistor, therefore, reference voltage source circuit of the present utility model is particularly useful for the manufacturing process without bipolar transistor.In addition, circuit structure of the present utility model is simple, and shared chip area is less.

[accompanying drawing explanation]

In order to be illustrated more clearly in the technical scheme of the utility model embodiment, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only embodiments more of the present utility model, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.Wherein:

Fig. 1 is the circuit diagram of the reference voltage source circuit of the utility model in first embodiment;

Fig. 2 is the circuit diagram of the utility model reference voltage source circuit in the second embodiment;

Fig. 3 is the circuit diagram of the reference voltage source circuit of the utility model in the 3rd embodiment;

Fig. 4 is the circuit diagram of the reference voltage source circuit of the utility model in the 4th embodiment.

[embodiment]

For enabling above-mentioned purpose of the present utility model, feature and advantage become apparent more, are described in further detail the utility model below in conjunction with the drawings and specific embodiments.

Alleged herein " embodiment " or " embodiment " refers to special characteristic, structure or the characteristic that can be contained at least one implementation of the utility model.Different local in this manual " in one embodiment " occurred not all refers to same embodiment, neither be independent or optionally mutually exclusive with other embodiments embodiment.Unless stated otherwise, connection herein, be connected, word that the expression that connects is electrically connected all represents and is directly or indirectly electrical connected.

Reference voltage source circuit of the present utility model forms negative feedback loop by multiple MOS (Metal Oxide Semiconductor) pipe, regulate with the reference voltage exported reference voltage output end, thus just can provide stable reference voltage without the need to manufacturing special bipolar transistor.

Please refer to shown in Fig. 1, it is the circuit diagram of the reference voltage source circuit of the utility model in first embodiment.This reference voltage source circuit comprises a NMOS (N-channel Metal OxideSemiconductor) transistor MN1, the second nmos pass transistor MN2, the 3rd nmos pass transistor MNd3, feedback voltage sample circuit 110 and reference voltage output end VR.

Wherein, the drain electrode of the 3rd nmos pass transistor MNd3 is all connected with node O with the drain electrode of the second nmos pass transistor MN2, the grid of the 3rd nmos pass transistor MNd3 is connected with the grid of the second nmos pass transistor MN2, the source electrode of the 3rd nmos pass transistor MNd3 is connected with the grid of the 3rd nmos pass transistor MNd3, the source electrode of the second nmos pass transistor MN2 and described reference voltage output end VR, node O is connected with power end VIN; The drain electrode of described first nmos pass transistor MN1 is connected with the source electrode of described 3rd nmos pass transistor MNd3, and the source electrode of described first nmos pass transistor MN1 is connected with earth terminal GND.In one embodiment, nmos pass transistor MN1 and MN2 is enhancement mode nmos pass transistor, and nmos pass transistor MNd3 is depletion type nmos transistor; In a preferred embodiment, nmos pass transistor MN2 also can be depletion type nmos transistor, like this, the reference voltage source circuit shown in Fig. 1 can be made to have lower operating supply voltage, namely, under lower supply voltage VIN, its reference voltage VR exported can remain stable.

The input end of described feedback voltage sample circuit 110 is connected with described reference voltage output end VR, its output terminal is connected with the grid of the first nmos pass transistor MN1, the reference voltage V R that described feedback voltage sample circuit 110 exports for described reference voltage output end of sampling, gives the grid of described first nmos pass transistor MN1 with output feedack voltage FB.In the embodiment shown in fig. 1, described feedback voltage sample circuit 110 comprises and is series at the second resistance R2 between reference voltage output end VR and earth terminal GND and the first resistance R1, connected node FB between described first resistance R1 and the second resistance R2 adopts the output terminal of circuit as described feedback voltage, and the voltage on this node is described feedback voltage FB.

Reference voltage source circuit shown in Fig. 1 based on the reference voltage V R of input supply voltage VIN stable output, can specifically introduce the principle of work of the reference voltage source circuit shown in Fig. 1 below.

Device in Fig. 1 forms a feedback loop.Suppose due to noise disturbance, when reference voltage V R is raised, feedback voltage FB after resistance R1 and R2 dividing potential drop also will raise, the ducting capacity of nmos pass transistor MN1 is caused to strengthen, the source voltage VG of nmos pass transistor MNd3 is caused to reduce, make the ducting capacity of nmos pass transistor MN2 decline further, then the reference voltage that reference voltage output end VR exports reduces; Suppose due to noise disturbance, when reference voltage V R is reduced, feedback voltage FB after resistance R1 and R2 dividing potential drop also will reduce, the ducting capacity of nmos pass transistor MN1 is caused to weaken, the source voltage VG of nmos pass transistor MNd3 is caused to raise, make the ducting capacity of nmos pass transistor MN2 strengthen further, then the reference voltage that reference voltage output end VR exports raises.The working point analyzing this negative feedback loop is known, and feedback voltage FB will be stable at the gate source voltage Vgs1 of nmos pass transistor MN1.Because nmos pass transistor MNd3 and MN1 is operated in saturation region, therefore, should meet under steady operation point:

$\mathrm{Id}1=\frac{1}{2}.\mathrm{\μ}.\mathrm{Cox}.{\left(\frac{W}{L}\right)}_{N1}.{(\mathrm{VgsN}1-\mathrm{VTN}1)}^2---\left(1\right),$

$\mathrm{Id}3=\frac{1}{2}.\mathrm{\μ}.\mathrm{Cox}.{\left(\frac{W}{L}\right)}_{N3}.{(\mathrm{VgsN}3-\mathrm{VTN}3)}^2---\left(2\right),$

Wherein, Id1 is the drain current of nmos pass transistor MN1, and Id3 is the drain current of nmos pass transistor MNd3, and μ is mobility, and Cox is unit area grid oxygen electric capacity, for the breadth length ratio of nmos pass transistor MN1, VgsN1 is the gate source voltage of nmos pass transistor MN1, and VTN1 is the threshold voltage of nmos pass transistor MN1; for the breadth length ratio of nmos pass transistor MNd3, VgsN3 is the gate source voltage of nmos pass transistor MNd3, and VTN3 is the threshold voltage of nmos pass transistor MNd3.

According to kirchhoff KCL law, Id1=Id3 (3)

Because the grid of nmos pass transistor MNd3 and source electrode link together, therefore, the gate source voltage VgsN3=0 (4) of nmos pass transistor MNd3

Equation (1), (2) and (4) are substituted into equation (3) and can obtain:

$\frac{1}{2}.\mathrm{\μ}.\mathrm{Cox}.{\left(\frac{W}{L}\right)}_{N1}.{(\mathrm{VgsN}1-\mathrm{VTN}1)}^2=\frac{1}{2}.\mathrm{\μ}.\mathrm{Cox}.{\left(\frac{W}{L}\right)}_{N3}.{\left(\right|\mathrm{VTN}3\left|\right)}^2$

Abbreviation obtains:

$\mathrm{VgsN}1=\mathrm{VTN}1+\sqrt{\frac{{\left(\frac{W}{L}\right)}_{N3}}{{\left(\frac{W}{L}\right)}_{N1}}}.\left(\right|\mathrm{VTN}3\left|\right)---\left(5\right),$

Threshold V T N1 due to nmos pass transistor MN1 be negative temperature coefficient on the occasion of, the threshold V T N3 of nmos pass transistor MNd3 is the negative of negative temperature coefficient, then | VTN3| be positive temperature coefficient (PTC) on the occasion of, therefore, both are added can carry out temperature compensation, realizes varying with temperature less VgsN1, such as, can according to VTN1 and | the temperature coefficient ratio of VTN3|, it is suitable to design thus realize good temperature compensation.

Again because under steady operation point, feedback voltage FB equals the gate source voltage Vgs1 of nmos pass transistor MN1, i.e. FB=VgsN1, and wherein, FB is the magnitude of voltage of feedback voltage, and VgsN1 is the gate source voltage of nmos pass transistor MN1; And the magnitude of voltage of reference voltage V R meets VR=[(R1+R2)/R1] .FB, wherein R1 is the resistance value of the first resistance R1, and R2 is the resistance value of the second resistance R2, and FB is the magnitude of voltage of feedback voltage; And because can matched design be passed through in integrated circuit, realize the ratio of R1 and R2 very accurately, this ratio is temperature independent, such as, first resistance R1 and the second resistance R2 is set to the resistance of identical type, and temperature coefficient is identical, so the reference voltage source circuit shown in Fig. 1 can produce temperature independent reference voltage V R by above-mentioned appropriate design.

Please refer to shown in Fig. 2, it is the circuit diagram of the utility model reference voltage source circuit in the second embodiment.The difference of itself and Fig. 1 is, is connected with electric capacity C1 between its input end at feedback voltage sample circuit 210 (i.e. reference voltage output end VR) and the output terminal FB of feedback voltage sample circuit 210.Like this, can improve the phase margin of feedback loop, thus improve the stability of feedback loop, concrete, the capacitance of electric capacity C1 can carry out small-signal analysis by simulation software and set.

Please refer to shown in Fig. 3, it is the circuit diagram of the reference voltage source circuit of the utility model in the 3rd embodiment.Its of itself and Fig. 2 is not, its depletion type nmos transistor MNd4 that connects between power end VIN and node O, be specially, the drain electrode of nmos pass transistor MNd4 is connected with power end VIN, and its grid is connected with its source electrode, and its source electrode is connected with node O.Like this, the Power Supply Rejection Ratio of the reference voltage V R of output can be improved, namely the fluctuation of reference voltage V R with the supply voltage VIN of input of output is reduced, its reason is, utilize the characteristic that nmos pass transistor MNd4 is depletion device, the electric current of nmos pass transistor MNd4 is very little with drain voltage fluctuation, main its gate source voltage of dependence, when the gate source voltage of nmos pass transistor MNd4 is shorted, its gate source voltage is zero.

Please refer to shown in Fig. 4, it is the circuit diagram of the reference voltage source circuit of the utility model in the 4th embodiment.The difference of itself and Fig. 1 is, the nmos pass transistor in Fig. 1 is all replaced with PMOS transistor by it, and power end VIN connects negative input voltage, and reference voltage output end VR exports negative reference voltage.

Reference voltage source circuit shown in Fig. 4 comprises the first PMOS transistor MP1, the second PMOS transistor MP2, the 3rd PMOS transistor MP3, feedback voltage sample circuit 410 and reference voltage output end VR.

Wherein, the drain electrode of the 3rd PMOS transistor MP3 is all connected with node O with the drain electrode of the second PMOS transistor MP2, the grid of the 3rd PMOS transistor MP3 is connected with the grid of the second PMOS transistor MP2, the source electrode of the 3rd PMOS transistor MP3 is connected with the grid of the 3rd PMOS transistor MP3, the source electrode of the second PMOS transistor MP2 and described reference voltage output end VR, node O is connected with power end VIN; The drain electrode of described first PMOS transistor MP1 is connected with the source electrode of described 3rd PMOS transistor MP3, and the source electrode of described first PMOS transistor MP1 is connected with earth terminal GND.In one embodiment, PMOS transistor MP1 is enhancement mode PMOS transistor, and PMOS transistor MP2 and MP3 is depletion type PMOS transistor.

The input end of described feedback voltage sample circuit 410 is connected with described reference voltage output end VR, its output terminal is connected with the grid of the first PMOS transistor MP1, the reference voltage V R that described feedback voltage sample circuit 410 exports for described reference voltage output end of sampling, gives the grid of described first PMOS transistor MP1 with output feedack voltage FB.

Device in Fig. 4 also forms a feedback loop.Feedback voltage FB can be stable at the gate source voltage Vgs1 of PMOS transistor MP1 by this negative feedback loop.In like manner, should meet under steady operation point:

$\frac{1}{2}.\mathrm{\μ}.\mathrm{Cox}.{\left(\frac{W}{L}\right)}_{P1}.{\left(\right|\mathrm{VgsP}1|-|\mathrm{VTP}1\left|\right)}^2=\frac{1}{2}.\mathrm{\μ}.\mathrm{Cox}.{\left(\frac{W}{L}\right)}_{P3}.{\left(\right|\mathrm{VTP}3\left|\right)}^2,$

Abbreviation obtains:

$\left|\mathrm{VgsP}1\right|=\left|\mathrm{VTP}1\right|+\sqrt{\frac{{\left(\frac{W}{L}\right)}_{P3}}{{\left(\frac{W}{L}\right)}_{P1}}}.\left(\right|\mathrm{VTP}3\left|\right)---\left(6\right),$

Wherein, μ is mobility, and Cox is unit area grid oxygen electric capacity, for the breadth length ratio of PMOS transistor MP1, VgsP1 is the gate source voltage of PMOS transistor MP1, and VTP1 is the threshold voltage of PMOS transistor MP1; for the breadth length ratio of PMOS transistor MP3, VgsP3 is the gate source voltage of PMOS transistor MP3, and VTP3 is the threshold voltage of PMOS transistor MP3.

Due to | VTP1| be negative temperature coefficient on the occasion of, | VTP3| be positive temperature coefficient (PTC) on the occasion of, therefore, both are added can carry out temperature compensation, realizes varying with temperature less VgsP1, such as, can basis | VTP1| and | the temperature coefficient ratio of VTP3|, it is suitable to design thus realize good temperature compensation.

Under steady operation point, the magnitude of voltage of reference voltage V R meets: VR=-[(R1+R2)/R1] .|VgsP1|, wherein R1 is the resistance value of the first resistance R1, and R2 is the resistance value of the second resistance R2, | VgsP1| is the absolute value of the gate source voltage of PMOS transistor MP1.

In like manner, also the nmos pass transistor of Fig. 2 and 3 all can be replaced with PMOS transistor.

In sum, reference voltage source circuit of the present utility model forms negative feedback loop by multiple metal-oxide-semiconductor, regulates with the reference voltage exported reference voltage output end, thus the reference voltage of stable output.Because the reference voltage source circuit in the utility model just can provide stable reference voltage without the need to manufacturing special bipolar transistor, therefore, reference voltage source circuit of the present utility model is particularly useful for the manufacturing process without bipolar transistor; Further, circuit structure of the present utility model is simple, and shared chip area is less.In addition, because the required device in the utility model is less, therefore, its equivalence is less to the device noise of the reference voltage V R exported.

In the utility model, " connection ", be connected, word that " companys ", the expression such as " connecing " are electrical connected, if no special instructions, then represent direct or indirect electric connection.

It is pointed out that the scope be familiar with person skilled in art and any change that embodiment of the present utility model is done all do not departed to claims of the present utility model.Correspondingly, the scope of claim of the present utility model is also not limited only to previous embodiment.

Claims (11)

1. a reference voltage source circuit, is characterized in that, it comprises the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, feedback voltage sample circuit and reference voltage output end,

Wherein, the drain electrode of the 3rd metal-oxide-semiconductor is all connected with node O with the drain electrode of the second metal-oxide-semiconductor, the grid of the 3rd metal-oxide-semiconductor is connected with the grid of the second metal-oxide-semiconductor, the source electrode of the 3rd metal-oxide-semiconductor is connected with the grid of the 3rd metal-oxide-semiconductor, the source electrode of the second metal-oxide-semiconductor is connected with reference voltage output end, and node O is connected with the first voltage end; The drain electrode of the first metal-oxide-semiconductor is connected with the source electrode of the 3rd metal-oxide-semiconductor, and the source electrode of the first metal-oxide-semiconductor is connected with the second voltage end,

The input end of described feedback voltage sample circuit is connected with described reference voltage output end, its output terminal is connected with the grid of described first metal-oxide-semiconductor, the reference voltage that described feedback voltage sample circuit exports for described reference voltage output end of sampling, gives the grid of described first metal-oxide-semiconductor with output feedack voltage.

2. reference voltage source circuit according to claim 1, is characterized in that, it also comprises the electric capacity between the output terminal being connected to described reference voltage output end and feedback voltage sample circuit.

3. reference voltage source circuit according to claim 1, is characterized in that, it also comprises the 4th metal-oxide-semiconductor, and the drain electrode of described 4th metal-oxide-semiconductor is connected with described first voltage end, and its grid is connected with its source electrode, and its source electrode is connected with node O.

4. reference voltage source circuit according to claim 1, is characterized in that,

Described feedback voltage sample circuit comprises the second resistance and the first resistance that are series at reference voltage output end and the second voltage end, and the connected node between described first resistance and the second resistance adopts the output terminal of circuit as described feedback voltage.

5. reference voltage source circuit according to claim 3, is characterized in that,

Described first metal-oxide-semiconductor is enhancement mode nmos pass transistor, and described 3rd metal-oxide-semiconductor is depletion type nmos transistor, and described second metal-oxide-semiconductor is enhancement mode nmos pass transistor or depletion type nmos transistor,

Described first voltage end is power end, and described second voltage end is earth terminal, described first power supply termination positive input voltage, and described reference voltage output end exports positive reference voltage.

6. reference voltage source circuit according to claim 5, is characterized in that, described 4th metal-oxide-semiconductor is depletion type nmos transistor.

7. reference voltage source circuit according to claim 3, is characterized in that,

Described first metal-oxide-semiconductor is enhancement mode PMOS transistor, described second metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor are depletion type PMOS transistor, described first voltage end is power end, described second voltage end is earth terminal, described first power supply termination negative input voltage, described reference voltage output end exports negative reference voltage.

8. reference voltage source circuit according to claim 7, is characterized in that, described 4th metal-oxide-semiconductor is depletion type PMOS transistor.

9. reference voltage source circuit according to claim 4, is characterized in that, described first resistance and the second resistance are the resistance of identical type, and temperature coefficient is identical.

10. reference voltage source circuit according to claim 5, is characterized in that, the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor meet following formula:

Wherein, VgsN1 is the gate source voltage of the first nmos pass transistor, be the breadth length ratio of the first nmos pass transistor, VTN1 is the threshold voltage of the first nmos pass transistor, be the breadth length ratio of the 3rd nmos pass transistor, VTN3 is the threshold voltage of the 3rd nmos pass transistor,

VTN1 be negative temperature coefficient on the occasion of, | VTN3| be positive temperature coefficient (PTC) on the occasion of, according to VTN1 and | the temperature coefficient ratio of VTN3|, determine

11. reference voltage source circuits according to claim 7, is characterized in that, the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor meet following formula:

Wherein, VgsP1 is the gate source voltage of the first PMOS transistor, be the breadth length ratio of the first PMOS transistor, VTP1 is the threshold voltage of the first PMOS transistor, be the breadth length ratio of the 3rd PMOS transistor, VTP3 is the threshold voltage of the 3rd PMOS transistor,

| VTP1| be negative temperature coefficient on the occasion of, | VTP3| be positive temperature coefficient (PTC) on the occasion of, according to | VTP1| and | the temperature coefficient ratio of VTP3|, determine