CN103869868B - Band-gap reference circuit with temperature compensation function - Google Patents

Abstract

The invention discloses a band-gap reference circuit with a temperature compensation function, and belongs to the technical field of microelectronics. By means of the band-gap reference circuit with the temperature compensation function, segmented current INL and current IP11 directly proportional to temperature T1.5 are added to the traditional first-order band-gap reference circuit, and namely the leakage current of a PMOS tube MP7 in a high-order temperature compensation circuit and the leakage current of a PMOS tube MP11 in the high-order temperature compensation circuit are added to a resistor R5 to achieve high-order temperature compensation so as to obtain a reference voltage. Due to the adoption of the technology, the reference voltage with the small temperature coefficient can be obtained.

Description

A kind of band-gap reference reference circuit with temperature compensation

Technical field

The invention belongs to microelectronics technology, particularly relate to a kind of band-gap reference reference circuit with temperature compensation.

Background technology

Band-gap reference circuit is widely used in Analogous Integrated Electronic Circuits and hydrid integrated circuit system, as data converter, power management and oscillator etc., its Main Function is for other unit of system provides stable reference voltage or electric current, the quality of its temperature coefficient (TC, Temperature Coefficient) decision systems performance to a great extent.

As shown in Figure 1, traditional band-gap reference circuit is NPN type triode base stage based on negative temperature coefficient and emitter both end voltage V _bEwith the thermal voltage of positive temperature coefficient (PTC) the principle of linear superposition, wherein k is Boltzmann constant, and T is absolute temperature, and q is electron charge.

According to superposition principle, bandgap voltage reference V can be obtained _rEFexpression formula be V _rEF=V _bE+ m × V _t, wherein, thermal voltage V _tfor being proportional to the voltage of absolute temperature (PTAT, Proporational To Absolute Temperature), V _bEthere is negative temperature coefficient, the size of Reasonable adjustment Coefficient m, in certain temperature range, just can obtain the band-gap reference reference voltage V of zero-temperature coefficient _rEF.

But, due to V _bEthe non-linear band-gap reference reference voltage of first compensation phase that makes there is larger temperature coefficient, thus constrain the application of single order band-gap reference circuit in High Precision Low Temperature degree coefficient system.

Summary of the invention

Because the above-mentioned defect of prior art, technical matters to be solved by this invention is to provide a kind ofly has higher compensation stability, greatly can reduce the band-gap reference reference circuit of output voltage temperature coefficient.

For achieving the above object, the invention provides a kind of band-gap reference reference circuit with temperature compensation, comprise start-up circuit, single order band-gap reference circuit and high-order temperature compensation circuit; The enabling signal output terminal of described start-up circuit connects the enabling signal input end of described single order band-gap reference circuit and high-order temperature compensation circuit respectively; The current signal output end of described single order band-gap reference circuit connects the current signal input end of described high-order temperature compensation circuit.

Described start-up circuit comprises: the first PMOS and the second PMOS, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube and the 4th NMOS tube.

Described single order band-gap reference circuit comprises: the 3rd PMOS, the 4th PMOS, the 5th PMOS, the 6th PMOS and the 7th PMOS, first PNP type triode and the second PNP type triode, first error amplifier and the second error amplifier, the first resistance, the second resistance, the 3rd resistance, the 4th resistance and the 5th resistance.

Described high-order temperature compensation circuit comprises: the 8th PMOS, the 9th PMOS, the tenth PMOS, the 11 PMOS, the 12 PMOS, the 13 PMOS, the 14 PMOS and the 15 PMOS, the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube and the tenth NMOS tube.

The source electrode of described first PMOS is connected with external power source, the drain electrode of described first PMOS is connected with the source electrode of described second PMOS, the grid of the first PMOS, the drain electrode of the drain electrode of described second PMOS and the grid of the second PMOS, the first NMOS tube, the grid of the second NMOS tube, the grid of the 3rd NMOS tube, the grid of the 4th NMOS tube are connected, and the source electrode of described first NMOS tube is connected with the source electrode of the source electrode of outside ground wire, the second NMOS tube, the 3rd NMOS tube, the source electrode of the 4th NMOS tube.

The source electrode of described 3rd PMOS is connected with the source electrode of external power source, the 4th PMOS, the drain electrode of the grid of the grid of the 3rd PMOS and the grid of the 4th PMOS, the 7th PMOS, the output terminal of the first error amplifier, the second NMOS tube of described start-up circuit is connected, the drain electrode of the 3rd PMOS is connected with the emitter of the reverse input end of the first error amplifier, the first PNP type triode, and the base stage of the first PNP type triode is connected with the collector of the first PNP type triode, outside ground wire.

The drain electrode of described 4th PMOS is connected with the positive input of the first error amplifier, the reverse input end of the second error amplifier, one end of the first resistance, the other end of described first resistance is connected with the emitter of the second PNP type triode, and the base stage of described second PNP type triode is connected with the collector of outside ground wire GND, the second PNP type triode.

The source electrode of described 5th PMOS is connected with external power source, the grid of described 5th PMOS is connected with the drain electrode of the 3rd NMOS tube of the output terminal of the second error amplifier, the grid of the 6th PMOS, described start-up circuit, the drain electrode of described 5th PMOS is connected with the positive input of the second error amplifier, one end of the second resistance, and the other end of described second resistance is connected with outside ground wire GND.

The source electrode of described 6th PMOS is connected with the source electrode of external power source, the 7th PMOS, the drain electrode of described 6th PMOS is connected with one end of one end of the 3rd resistance, the 4th resistance, the other end of described 3rd resistance is connected with the grid of the first NMOS tube of the drain electrode of the 7th PMOS, single order band-gap reference circuit output terminal VREF, described start-up circuit, the other end of described 4th resistance is connected with one end of the 5th resistance, and the other end of described 5th resistance is connected with outside ground wire GND.

The source electrode of described 8th PMOS is connected with external power source, the grid of described 8th PMOS is connected with the grid of the 4th PMOS of described single order band-gap reference, the drain electrode of the 8th PMOS is connected with the grid of the drain electrode of the 5th NMOS tube, the 5th NMOS tube, the grid of the 6th NMOS tube, and the source electrode of described 5th NMOS tube is connected with the source electrode of the 6th NMOS tube, outside ground wire.

The source electrode of described 9th PMOS is connected with external power source, the grid of described 9th PMOS is connected with the grid of the 5th PMOS of described single order band-gap reference circuit, and the drain electrode of the drain electrode of described 9th PMOS and the grid of the tenth PMOS, the tenth PMOS, the grid of the 11 PMOS, the drain electrode of the 6th NMOS tube are connected.

The source electrode of described 11 PMOS is connected with the source electrode of external power source, the tenth PMOS, and the drain electrode of described 11 PMOS is connected between described 4th resistance and the 5th resistance.

The source electrode of described 12 PMOS is connected with external power source, the grid of described 12 PMOS is connected with the grid of the 4th PMOS of described single order band-gap reference circuit, the drain electrode of described 12 PMOS is connected with the grid of the drain electrode of the 7th NMOS tube, the 7th NMOS tube, the grid of the 8th NMOS tube, and the source electrode of described 7th NMOS tube is connected with the source electrode of the 8th NMOS tube, outside ground wire.

The source electrode of described 13 PMOS and external power source, the source electrode of the 14 PMOS is connected, the described grid of the 13 PMOS and the grid of the 14 PMOS, the drain electrode of the 13 PMOS, the drain electrode of the 9th NMOS tube, the drain electrode of the 4th NMOS tube of described start-up circuit is connected, the grid of described 9th NMOS tube and the grid of the tenth NMOS tube, the drain electrode of the tenth NMOS tube, the drain electrode of the 14 PMOS is connected, the source electrode of described 9th NMOS tube is connected with the drain electrode of the 8th NMOS tube, the source electrode of described 8th NMOS tube and the source electrode of the tenth NMOS tube, outside ground wire GND is connected.

The source electrode of described 15 PMOS is connected with external power source, and the grid of described 15 PMOS is connected with the grid of the 13 PMOS, and the drain electrode of described 15 PMOS is connected between described 4th resistance and the 5th resistance.

The invention has the beneficial effects as follows: the band-gap reference of temperature compensation of the present invention is with reference to passing through segmented current I _nLand with temperature T ^1.5the electric current I be directly proportional _p11join in traditional single order band-gap reference circuit, namely by the leakage current of the 11 PMOS MP7 in high-order temperature compensation circuit and the leakage current of the 15 PMOS MP11 are joined resistance R5 realizes high-order temperature compensated, obtain reference voltage, adopt this technology, the reference voltage of less temperature coefficient can be obtained.

Accompanying drawing explanation

Fig. 1 is the basic principle schematic of conventional first order band-gap reference reference.

Fig. 2 is circuit theory schematic diagram of the present invention.

Fig. 3 is the electrical block diagram of the band-gap reference reference of temperature compensation of the present invention.

Fig. 4 is single order band-gap reference reference output voltage curve synoptic diagram.

Fig. 5 is the output voltage curve synoptic diagram of the band-gap reference reference of temperature compensation of the present invention.

Fig. 6 is the temperature characterisitic simulation curve schematic diagram of the output voltage of the band-gap reference reference of temperature compensation of the present invention.

Embodiment

Below in conjunction with drawings and Examples, the invention will be further described:

As shown in Figure 2 and Figure 3, a kind of band-gap reference reference circuit with temperature compensation, the enabling signal output terminal of described start-up circuit 1 connects the enabling signal input end of described single order band-gap reference circuit 2 and high-order temperature compensation circuit 3 respectively; The current signal output end of described single order band-gap reference circuit 2 connects the current signal input end of described high-order temperature compensation circuit 3.Described start-up circuit 1 normally works for making the band-gap reference circuit of temperature compensation, described single order band-gap reference circuit 2 produces the band gap reference voltage of low-temperature coefficient, and described high-order temperature compensation circuit 3 is for carrying out temperature compensation to described single order band-gap reference circuit 2.

Described start-up circuit 1 comprises: the first PMOS MSP1 and the second PMOS MSP2, the first NMOS tube MSN1, the second NMOS tube MSN2, the 3rd NMOS tube MSN3 and the 4th NMOS tube MSN4.

Described single order band-gap reference circuit 2 comprises: the 3rd PMOS MP1, the 4th PMOS MP2, the 5th PMOS MP3, the 6th PMOS MP12 and the 7th PMOS MP13, first PNP type triode Q1 and the second PNP type triode Q2, first error amplifier A1 and the second error amplifier A2, the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4 and the 5th resistance R5.

Described high-order temperature compensation circuit 3 comprises: the 8th PMOS MP4, the 9th PMOS MP5, the tenth PMOS MP6, the 11 PMOS MP7, the 12 PMOS MP8, the 13 PMOS MP9, the 14 PMOS MP10 and the 15 PMOS MP11, the 5th NMOS tube MN1, the 6th NMOS tube MN2, the 7th NMOS tube MN3, the 8th NMOS tube MN4, the 9th NMOS tube MN5 and the tenth NMOS tube MN6.

The source electrode of described first PMOS MSP1 is connected with external power source VDD, the drain electrode of described first PMOS MSP1 and the source electrode of described second PMOS MSP2, the grid of the first PMOS MSP1 is connected, the drain electrode of described second PMOS MSP2 and the grid of the second PMOS MSP2, the drain electrode of the first NMOS tube MSN1, the grid of the second NMOS tube MSN2, the grid of the 3rd NMOS tube MSN3, the grid of the 4th NMOS tube MSN4 is connected, the source electrode of described first NMOS tube MSN1 and outside ground wire GND, the source electrode of the second NMOS tube MSN2, the source electrode of the 3rd NMOS tube MSN3, the source electrode of the 4th NMOS tube MSN4 is connected.

The source electrode of described 3rd PMOS MP1 is connected with the source electrode of external power source VDD, the 4th PMOS MP2, the drain electrode of the grid of the grid of the 3rd PMOS MP1 and the grid of the 4th PMOS MP2, the 7th PMOS MP13, the output terminal of the first error amplifier A1, the second NMOS tube MSN2 of described start-up circuit 1 is connected, the drain electrode of the 3rd PMOS MP1 is connected with the reverse input end of the first error amplifier A1, the emitter of the first PNP type triode Q1, and the base stage of the first PNP type triode Q1 is connected with the collector of the first PNP type triode Q1, outside ground wire GND.

The drain electrode of described 4th PMOS MP2 is connected with the reverse input end of the positive input of the first error amplifier A1, the second error amplifier A2, one end of the first resistance R1, the other end of described first resistance R1 is connected with the emitter of the second PNP type triode Q2, and the base stage of described second PNP type triode Q2 is connected with the collector of outside ground wire GND, the second PNP type triode Q2.

The source electrode of described 5th PMOS MP3 is connected with external power source VDD, the grid of described 5th PMOS MP3 is connected with the drain electrode of the grid of the output terminal of the second error amplifier A2, the 6th PMOS MP12, the 3rd NMOS tube MSN3 of described start-up circuit 1, the drain electrode of described 5th PMOS MP3 is connected with one end of the positive input of the second error amplifier A2, the second resistance R2, and the other end of described second resistance R2 is connected with outside ground wire GND.

The source electrode of described 6th PMOS MP12 is connected with the source electrode of external power source VDD, the 7th PMOS MP13, the drain electrode of described 6th PMOS MP12 is connected with one end of one end of the 3rd resistance R3, the 4th resistance R4, the other end of described 3rd resistance R3 is connected with the grid of the first NMOS tube MSN1 of the drain electrode of the 7th PMOS MP13, single order band-gap reference circuit output terminal VREF, described start-up circuit 1, the other end of described 4th resistance R4 is connected with one end of the 5th resistance R5, and the other end of described 5th resistance R5 is connected with outside ground wire GND.

The source electrode of described 8th PMOS MP4 is connected with external power source VDD, the grid of described 8th PMOS MP4 is connected with the grid of the 4th PMOS MP2 of described single order band-gap reference 2, the drain electrode of described 8th PMOS MP4 is connected with the grid of the drain electrode of the 5th NMOS tube MN1, the 5th NMOS tube MN1, the grid of the 6th NMOS tube MN2, and the source electrode of described 5th NMOS tube MN1 is connected with the source electrode of the 6th NMOS tube MN2, outside ground wire GND.

The source electrode of described 9th PMOS MP5 is connected with external power source VDD, the grid of described 9th PMOS MP5 is connected with the grid of the 5th PMOS MP3 of described single order band-gap reference circuit 2, and the drain electrode of the drain electrode of described 9th PMOS MP5 and the grid of the tenth PMOS MP6, the tenth PMOS MP6, the grid of the 11 PMOS MP7, the drain electrode of the 6th NMOS tube MN2 are connected.

The source electrode of described 11 PMOS MP7 is connected with the source electrode of external power source VDD, the tenth PMOS MP6, and the drain electrode of described 11 PMOS MP7 is connected between described 4th resistance R4 and the 5th resistance R5;

The source electrode of described 12 PMOS MP8 is connected with external power source VDD, the grid of described 12 PMOS MP8 is connected with the grid of the 4th PMOS MP2 of described single order band-gap reference circuit 2, the drain electrode of described 12 PMOS MP8 is connected with the grid of the drain electrode of the 7th NMOS tube MN3, the 7th NMOS tube MN3, the grid of the 8th NMOS tube MN4, and the source electrode of described 7th NMOS tube MN3 is connected with the source electrode of the 8th NMOS tube MN4, outside ground wire GND.

The source electrode of described 13 PMOS MP9 and external power source VDD, the source electrode of the 14 PMOS MP10 is connected, the described grid of the 13 PMOS MP9 and the grid of the 14 PMOS MP10, the drain electrode of the 13 PMOS MP9, the drain electrode of the 9th NMOS tube MN5, the drain electrode of the 4th NMOS tube MSN4 of described start-up circuit 1 is connected, the grid of described 9th NMOS tube MN5 and the grid of the tenth NMOS tube MN6, the drain electrode of the tenth NMOS tube MN6, the drain electrode of the 14 PMOS MP10 is connected, the source electrode of described 9th NMOS tube MN5 is connected with the drain electrode of the 8th NMOS tube MN4, the source electrode of described 8th NMOS tube MN4 and the source electrode of the tenth NMOS tube MN6, outside ground wire GND is connected.

The source electrode of described 15 PMOS MP11 is connected with external power source VDD, the grid of described 15 PMOS MP11 is connected with the grid of the 13 PMOS MP9, and the drain electrode of described 15 PMOS MP11 is connected between described 4th resistance R4 and the 5th resistance R5.

Adopt above technical scheme, start-up circuit makes band-gap reference circuit normally work, and produces bandgap voltage reference and exports.Start-up circuit only plays a role when band-gap reference reference circuit powers on, and after band-gap reference reference circuit has started, start-up circuit quits work, and avoids the impact of start-up circuit on circuit below.

Error amplifier A1 and A2 in described single order band-gap reference circuit is prior art, does not repeat them here.

First error amplifier A1 makes the voltage of the input node A of the first error amplifier and input node B equal, i.e. V _a=V _b=V _eB1, wherein, V _eB1it is the emitter base voltage of the first PNP type triode Q1.

3rd PMOS MP1 and the 4th PMOS MP2 is just the same, then the drain current I of the 4th PMOS MP2 _pTAT0for:

$I_{\mathrm{PTAT}0}=\frac{\mathrm{kT}}{q{R}_1}\ln N---\left(1\right)$

Described N is the ratio of the emitter area of the second PNP type triode Q2 and the first PNP type triode Q1, and k is Boltzmann constant, and T is absolute temperature, and q is electron charge, and simultaneously all resistance is all that same material realizes.Second error amplifier A2 makes the voltage of the input node C of the input node B of the first error amplifier and the second error amplifier equal, i.e. V _b=V _c=V _eB1, the input node B of described first error amplifier is the input node of described second error amplifier simultaneously, then the drain current I of the 5th PMOS MP3 _cTAT0for:

$I_{\mathrm{CTAT}0}=\frac{V_{\mathrm{EB}1}}{R_2}---\left(2\right)$

The breadth length ratio of the 7th PMOS MP13 is the K of the 4th PMOS MP2 ₁doubly, then the drain current I of the 7th PMOS MP13 _pTAT1for:

$I_{\mathrm{PTAT}1}=K_1\×I_{\mathrm{PTAT}0}=K_1\×\frac{\mathrm{kT}}{q{R}_1}\ln N---\left(3\right)$

The breadth length ratio of the 6th PMOS MP12 is the K of the 5th PMOS MP3 ₂doubly, then the drain current I of the 6th PMOS MP12 _cTAT1for:

$I_{\mathrm{CTAT}1}=K_2\×I_{\mathrm{CTAT}0}=K_2\×\frac{V_{\mathrm{EB}1}}{R_2}---\left(4\right)$

The present invention is for compensating V _eB1temperature high-order nonlinear item, adopt high-order temperature compensation circuit.8th PMOS MP4 and the 4th PMOS MP2 is duplicate, and the breadth length ratio of the 6th NMOS tube MN2 is the K of the 5th NMOS tube MN1 ₃doubly, then the drain current I of the 6th NMOS tube MN2 _pTAT2for:

$I_{\mathrm{PTAT}2}=K_3\×I_{\mathrm{PTAT}0}=K_3\×\frac{\mathrm{kT}}{q{R}_1}\ln N---\left(5\right)$

The breadth length ratio of the 9th PMOS MP5 is the K of the 5th PMOS MP3 ₄doubly, then the drain current I of the 9th PMOS MP5 _cTAT2for:

$I_{\mathrm{CTAT}2}=K_4\×I_{\mathrm{CTAT}0}=K_4\×\frac{V_{\mathrm{EB}1}}{R_2}---\left(6\right)$

From formula (5), (6), at temperature T _r1under, by Optimal Parameters K ₃with K ₄, there is following relation:

I _CTAT2＝I _PTAT2（7）

From Kirchhoff's current law (KCL), the drain current I of the tenth PMOS MP6 _p6for:

I _P6＝I _PTAT2-I _CTAT2（8）

11 PMOS MP7 and the tenth PMOS MP6 forms current mirror pair, and the breadth length ratio of the 11 PMOS MP7 is β times of the tenth PMOS MP6.From formula (5), (6), (7), (8), the drain current I of the 11 PMOS MP7 _nLfor:

$I_{\mathrm{NL}}=\left\{\begin{array}{cc}0& \mathrm{whenT}\≤T_{r1}\\ \mathrm{\β}\×K_3\×\frac{\mathrm{kT}}{q{R}_1}\ln N-\mathrm{\β}\×K_4\×\frac{V_{\mathrm{EB}1}}{R_2}& \mathrm{whenT}>T_{r1}\end{array}\right.---\left(9\right)$

The breadth length ratio of the 12 PMOS MP8 is the K of the 4th PMOS MP2 ₅doubly, the drain current I of the 7th NMOS tube MN3 _pTAT3for:

$I_{\mathrm{PTAT}3}=K_5\×I_{\mathrm{PTAT}0}=K_5\×\frac{\mathrm{kT}}{q{R}_1}\ln N---\left(10\right)$

In Fig. 2, the 7th NMOS tube MN3 is operated in saturation region, and the 8th NMOS tube MN4 is operated in dark linear zone, then the drain-source resistance r of the 8th NMOS tube MN4 _ds4for

$r_{\mathrm{ds}4}=\frac{\sqrt{{(W/L)}_3}}{{(W/L)}_4\sqrt{{2\mathrm{\μ}}_n{C}_{\mathrm{ox}}{K}_5{I}_{\mathrm{PTAT}0}}}---\left(11\right)$

(W/L) ₃the wide length of the 7th NMOS tube MN3, (W/L) ₄the wide length of the 8th NMOS tube MN4, μ _nelectron mobility, C _oXit is unit area gate oxide capacitance.13 PMOS MP9 has identical breadth length ratio with the 14 PMOS MP10, and is all operated in saturation region.9th NMOS tube MN5 and the tenth NMOS tube MN6 is operated in sub-threshold region, and the breadth length ratio of the 9th NMOS tube MN5 is α times of the tenth NMOS tube MN6.Wherein, the drain current I of the metal-oxide-semiconductor of sub-threshold region is operated in _dfor:

$I_D\≈\frac{W}{L}{I}_{D0}\exp \left(\frac{V_{\mathrm{GS}}}{\mathrm{nkT}/q}\right)---\left(12\right)$

Here, W/L is the breadth length ratio of metal-oxide-semiconductor, V _gSthe gate source voltage of metal-oxide-semiconductor, I _d0be the parameter relevant to technique, n is the imperfect factor being greater than 1.

15 PMOS MP11 and the 13 PMOS MP9 forms current mirror pair, and the breadth length ratio of the 15 PMOS MP11 is the K of the 13 PMOS MP9 ₆doubly, then from Fig. 2 and formula (10), (11), (12), the drain current I of the 15 PMOS MP11 _p11for:

$I_{P11}=K_6\×n\left(\ln \mathrm{\α}\right){\left(\frac{W}{L}\right)}_4\frac{\sqrt{{2\mathrm{\μ}}_n{C}_{\mathrm{ox}}{K}_5\left(\ln N\right)}}{\sqrt{R_1{(W/L)}_3}}\frac{k^{1.5}}{q^{1.5}}\×T^{1.5}---\left(13\right)$

From formula (3), (4), (9), (13), the output voltage V of the band-gap reference reference of temperature compensation _rEFfor:

$V_{\mathrm{REF}}=V_{\mathrm{PTAT}}+V_{\mathrm{CTAT}}+V_{\mathrm{NL}}+V_{\mathrm{PTA}{T}^{1.5}}---\left(14\right)$

Here,

$V_{\mathrm{PTAT}}=K_1\×\frac{\mathrm{kT}}{q{R}_1}\left(\ln N\right)\×(R_3+R_4+R_5)---\left(15\right)$

$V_{\mathrm{CTAT}}=K_2\×\frac{V_{\mathrm{EB}1}}{R_2}\×(R_4+R_5)---\left(16\right)$

$V_{\mathrm{NL}}=\left\{\begin{array}{cc}0& \mathrm{whenT}\≤T_{r1}\\ \mathrm{\β}\×K_3\×\frac{{\mathrm{kTR}}_5}{q{R}_1}\ln N-\mathrm{\β}\×K_4\×\frac{R_5{V}_{\mathrm{EB}1}}{R_2}& \mathrm{whenT}>T_{r1}\end{array}\right.---\left(17\right)$

$V_{\mathrm{PTA}{T}^{1.5}}=K_6\×n\left(\ln \mathrm{\α}\right){\left(\frac{W}{L}\right)}_4\frac{\sqrt{{2\mathrm{\μ}}_n{C}_{\mathrm{ox}}{K}_5\left(\ln N\right)}}{\sqrt{R_1{(W/L)}_3}}\frac{k^{1.5}}{q^{1.5}}{\×T}^{1.5}\×R_5---\left(18\right)$

From formula (15), V _pTATthe voltage of a positive temperature coefficient (PTC), the V in formula (16) _eB1the emitter base voltage of the first PNP type triode Q1, thus by the parameter K in optimized-type (15) ₁, N and resistance R ₃, R ₄, R ₅, realize single order temperature compensation, obtain single order band-gap reference reference voltage, band-gap reference reference voltage curve as shown in Figure 4 can be obtained.

In fact, V _eB1there is high-order nonlinear temperature item, from Fig. 4 and formula (15), (16), V _pTATonly offset V _eB1the once item of temperature T, therefore need to carry out high-order temperature compensated.The technology of the present invention is introduce a segmented current I at single order band-gap reference with reference on basis _nLproduce circuit and one and temperature T ^1.5the electric current I be directly proportional _p11produce circuit, solve single order band-gap reference with reference to Problems existing.From formula (17), voltage V _nLbe one and there is segmented characterizing voltage, simultaneously from formula (18), voltage one and temperature T ^1.5the voltage be directly proportional, thus by V _nLwith two voltages are incorporated in the reference of single order band gap base, effectively can compensate V _eB1in the higher order term of temperature T, obtain high-order temperature compensation bandgap reference, the band-gap reference reference voltage curve of temperature compensation of the present invention as shown in Figure 5 can be obtained.Fig. 6 is the output reference voltage V of the band-gap reference reference of temperature compensation of the present invention _rEFtemperature characterisitic simulation curve, wherein horizontal ordinate is temperature, and ordinate is band-gap reference output voltage.Simulation result shows, is-55 DEG C ~ 125 DEG C in temperature range, and the band-gap reference of this temperature compensation is with reference to the temperature coefficient reaching 2.54ppm/ DEG C.

Here, when start-up circuit starts, due to band-gap reference reference output voltage V _rEFrelatively low, first NMOS tube MNS1 cut-off, make the second NMOS tube MSN2, the grid potential of the 3rd NMOS tube MSN3 and the 4th NMOS tube MSN4 is noble potential, thus make the 3rd PMOS MP1, 4th PMOS MP2, the grid of the 5th PMOS MP3 and the 14 PMOS MP10 is electronegative potential, this just defines the 3rd PMOS MP1 to the first PNP type triode Q1, 4th PMOS MP2 is to the second PNP type triode Q2, the current path of 5th PMOS MP3 to the second resistance R2 and the 14 PMOS MP10 to the tenth NMOS tube MN6, circuit is made to depart from zero condition, enter duty.But, V _rEFwhen rising to more than NMOS threshold voltage, first NMOS tube MSN1 conducting, the grid of the second NMOS tube MSN2, the 3rd NMOS tube MSN3 and the 4th NMOS tube MSN4 is made to be electronegative potential and to be operated in cut-off region, start-up circuit is no longer had an impact to band-gap reference reference circuit below, and startup completes.

Present invention employs a segmented current I _nLproduce circuit and with temperature T ^1.5the electric current I be directly proportional _p11produce the compensation technique of circuit, make band-gap reference reference output voltage have very high stability, simultaneously because circuit meets the requirement of low voltage operating, make the present invention have range of application very widely.

More than describe preferred embodiment of the present invention in detail.Should be appreciated that those of ordinary skill in the art just design according to the present invention can make many modifications and variations without the need to creative work.Therefore, all technician in the art, all should by the determined protection domain of claims under this invention's idea on the basis of existing technology by the available technical scheme of logical analysis, reasoning, or a limited experiment.

Claims (1)

1. the band-gap reference reference circuit with temperature compensation, comprises start-up circuit (1) and single order band-gap reference circuit (2), it is characterized in that: also comprise high-order temperature compensation circuit (3); The enabling signal output terminal of described start-up circuit (1) connects the enabling signal input end of described single order band-gap reference circuit (2) and high-order temperature compensation circuit (3) respectively; The current signal output end of described single order band-gap reference circuit (2) connects the current signal input end of described high-order temperature compensation circuit (3), described start-up circuit (1) normally works for making the band-gap reference circuit of temperature compensation, described single order band-gap reference circuit (2) is for generation of the band gap reference voltage of low-temperature coefficient, and described high-order temperature compensation circuit (3) is for carrying out temperature compensation to described single order band-gap reference circuit (2);

Described start-up circuit (1) comprising: the first PMOS (MSP1) and the second PMOS (MSP2), the first NMOS tube (MSN1), the second NMOS tube (MSN2), the 3rd NMOS tube (MSN3) and the 4th NMOS tube (MSN4);

Described single order band-gap reference circuit (2) comprising: the 3rd PMOS (MP1), the 4th PMOS (MP2), the 5th PMOS (MP3), the 6th PMOS (MP12) and the 7th PMOS (MP13), first PNP type triode (Q1) and the second PNP type triode (Q2), first error amplifier (A1) and the second error amplifier (A2), the first resistance (R1), the second resistance (R2), the 3rd resistance (R3), the 4th resistance (R4) and the 5th resistance (R5);

Described high-order temperature compensation circuit (3) comprising: the 8th PMOS (MP4), the 9th PMOS (MP5), the tenth PMOS (MP6), the 11 PMOS (MP7), the 12 PMOS (MP8), the 13 PMOS (MP9), the 14 PMOS (MP10) and the 15 PMOS (MP11), the 5th NMOS tube (MN1), the 6th NMOS tube (MN2), the 7th NMOS tube (MN3), the 8th NMOS tube (MN4), the 9th NMOS tube (MN5) and the tenth NMOS tube (MN6);

The source electrode of described first PMOS (MSP1) is connected with external power source (VDD), the drain electrode of described first PMOS (MSP1) and the source electrode of described second PMOS (MSP2), the grid of the first PMOS (MSP1) is connected, the drain electrode of described second PMOS (MSP2) and the grid of the second PMOS (MSP2), the drain electrode of the first NMOS tube (MSN1), the grid of the second NMOS tube (MSN2), the grid of the 3rd NMOS tube (MSN3), the grid of the 4th NMOS tube (MSN4) is connected, the source electrode of described first NMOS tube (MSN1) and outside ground wire (GND), the source electrode of the second NMOS tube (MSN2), the source electrode of the 3rd NMOS tube (MSN3), the source electrode of the 4th NMOS tube (MSN4) is connected,

The source electrode of described 3rd PMOS (MP1) and external power source (VDD), the source electrode of the 4th PMOS (MP2) is connected, the grid of the 3rd PMOS (MP1) and the grid of the 4th PMOS (MP2), the grid of the 7th PMOS (MP13), the output terminal of the first error amplifier (A1), the drain electrode of second NMOS tube (MSN2) of described start-up circuit (1) is connected, the drain electrode of the 3rd PMOS (MP1) and the reverse input end of the first error amplifier (A1), the emitter of the first PNP type triode (Q1) is connected, the base stage of the first PNP type triode (Q1) and the collector of the first PNP type triode (Q1), outside ground wire (GND) is connected,

The drain electrode of described 4th PMOS (MP2) is connected with the positive input of the first error amplifier (A1), the reverse input end of the second error amplifier (A2), one end of the first resistance (R1), the other end of described first resistance (R1) is connected with the emitter of the second PNP type triode (Q2), and the base stage of described second PNP type triode (Q2) is connected with the collector of outside ground wire (GND), the second PNP type triode (Q2);

The source electrode of described 5th PMOS (MP3) is connected with external power source (VDD), the grid of described 5th PMOS (MP3) is connected with the drain electrode of the grid of the output terminal of the second error amplifier (A2), the 6th PMOS (MP12), the 3rd NMOS tube (MSN3) of described start-up circuit (1), the drain electrode of described 5th PMOS (MP3) is connected with the positive input of the second error amplifier (A2), one end of the second resistance (R2), and the other end of described second resistance (R2) is connected with outside ground wire (GND);

The source electrode of described 6th PMOS (MP12) and external power source (VDD), the source electrode of the 7th PMOS (MP13) is connected, the drain electrode of described 6th PMOS (MP12) and one end of the 3rd resistance (R3), one end of 4th resistance (R4) is connected, the other end of described 3rd resistance (R3) and the drain electrode of the 7th PMOS (MP13), single order band-gap reference circuit output terminal VREF, the grid of first NMOS tube (MSN1) of described start-up circuit (1) is connected, the other end of described 4th resistance (R4) is connected with one end of the 5th resistance (R5), the other end of described 5th resistance (R5) is connected with outside ground wire (GND),

The source electrode of described 8th PMOS (MP4) is connected with external power source (VDD), the grid of described 8th PMOS (MP4) is connected with the grid of the 4th PMOS (MP2) of described single order band-gap reference, the drain electrode of the 8th PMOS (MP4) is connected with the grid of the drain electrode of the 5th NMOS tube (MN1), the 5th NMOS tube (MN1), the grid of the 6th NMOS tube (MN2), and the source electrode of described 5th NMOS tube (MN1) is connected with the source electrode of the 6th NMOS tube (MN2), outside ground wire (GND);

The source electrode of described 9th PMOS (MP5) is connected with external power source (VDD), the grid of described 9th PMOS (MP5) is connected with the grid of the 5th PMOS (MP3) of described single order band-gap reference circuit (2), and the drain electrode of the drain electrode of described 9th PMOS (MP5) and the grid of the tenth PMOS (MP6), the tenth PMOS (MP6), the grid of the 11 PMOS (MP7), the drain electrode of the 6th NMOS tube (MN2) are connected;

The source electrode of described 11 PMOS (MP7) is connected with the source electrode of external power source (VDD), the tenth PMOS (MP6), and the drain electrode of described 11 PMOS (MP7) is connected between described 4th resistance (R4) and the 5th resistance (R5);

The source electrode of described 12 PMOS (MP8) is connected with external power source (VDD), the grid of described 12 PMOS (MP8) is connected with the grid of the 4th PMOS (MP2) of described single order band-gap reference circuit (2), the drain electrode of described 12 PMOS (MP8) is connected with the grid of the drain electrode of the 7th NMOS tube (MN3), the 7th NMOS tube (MN3), the grid of the 8th NMOS tube (MN4), and the source electrode of described 7th NMOS tube (MN3) is connected with the source electrode of the 8th NMOS tube (MN4), outside ground wire (GND);

The source electrode of described 13 PMOS (MP9) and external power source (VDD), the source electrode of the 14 PMOS (MP10) is connected, the described grid of the 13 PMOS (MP9) and the grid of the 14 PMOS (MP10), the drain electrode of the 13 PMOS (MP9), the drain electrode of the 9th NMOS tube (MN5), the drain electrode of the 4th NMOS tube (MSN4) of described start-up circuit (1) is connected, the grid of described 9th NMOS tube (MN5) and the grid of the tenth NMOS tube (MN6), the drain electrode of the tenth NMOS tube (MN6), the drain electrode of the 14 PMOS (MP10) is connected, the source electrode of described 9th NMOS tube (MN5) is connected with the drain electrode of the 8th NMOS tube (MN4), the source electrode of described 8th NMOS tube (MN4) and the source electrode of the tenth NMOS tube (MN6), outside ground wire (GND) is connected,

The source electrode of described 15 PMOS (MP11) is connected with external power source (VDD), the grid of described 15 PMOS (MP11) is connected with the grid of the 13 PMOS (MP9), and the drain electrode of described 15 PMOS (MP11) is connected between described 4th resistance (R4) and the 5th resistance (R5).