CN104714588B - A kind of based on the linearizing Low Drift Temperature bandgap voltage reference of VBE - Google Patents

Abstract

The present invention is open a kind of based on the linearizing Low Drift Temperature bandgap voltage reference of VBE, and circuit comprises PTAT current generating circuit, high-order compensation band gap reference circuit, start-up circuit one and start-up circuit two.This reference circuit builds nonlinear terms by the difference of the different VBE of two collector current temperature characterisitics, then superpose with VBE, and counteracting nonlinear terms wherein, reach the effect of high-order compensation.Its zero-temperature coefficient feature set electrode current superposes by two VBE the voltage deducting a VBE to be again added in negative temperature parameter current that resistance R3 two ends produce and the positive temperature coefficient (PTC) current summation that Δ VBE produces on resistance R1 forms, temperature characterisitic by the impact of output voltage precision, not ensure that the precision of high-order compensation.Compared with traditional VBE linearization technique, this circuit adopts voltage-mode to export VREF, avoid current mirror mismatch and output resistance temperature characterisitic to the impact of compensation precision, thus obtain the reference voltage of high precision zero-temperature coefficient, and then solve the problems such as conversion accuracy is low.

Description

A kind of based on the linearizing Low Drift Temperature bandgap voltage reference of VBE

Technical field

The present invention relates to Analogical Circuit Technique field, be specifically related to a kind of based on the linearizing Low Drift Temperature bandgap voltage reference of VBE.

Background technology

Band gap reference is most widely used a kind of reference source in modern large scale integrated circuit, is widely used in data conversion system, power-supply management system and accumulator system etc.Its ultimate principle is voltage (the normally VBE utilizing a negative temperature coefficient, refer to the voltage difference between transistor base stage B and emitter E) and voltage (the normally △ VBE of a positive temperature coefficient (PTC), refer to the difference of two VBE) superimposed, their Positive and Negative Coefficient Temperature is offseted, thus realizes low-temperature coefficient voltage.

Along with the raising that system accuracy requires, the temperature coefficient of traditional single order reference voltage creates restriction to system accuracy.In the prior art, the high-order temperature compensated technology of usual employing realizes the reference voltage of lower temperature coefficient, and described high-order temperature compensated technology is generally the reference circuit utilizing extra high order compensation circuit generation non-linear positive temperature coefficient voltages and single order reference voltage to superpose to realize low-temperature coefficient.Existing high-order compensation technology has Exponential curvature-compensation method, VBE linearization, piece-wise linearization, the method that compensate different from utilizing different materials temperature-coefficient of electrical resistance.Index temperature compensation utilizes the currentgainβ of triode to do temperature compensation with the rule of temperature exponentially type change to reference voltage, and shortcoming is β variation range considerable restraint compensation effect in reality, and its supply voltage requires higher in addition, generally at 5V; The non-linear voltage component that the VBE superposition that VBE linearization technique utilizes two collector current temperature characterisitics different produces is to offset the nonlinear terms in VBE, its shortcoming is that the accuracy requirement of circuit to resistance ratio is high, and the temperature coefficient etc. exporting branch road output resistance can affect high-order compensation precision; Whole temperature range is divided into some sections by section linear compensating, in each segment, reference voltage will reduce greatly with the side-play amount of temperature, the hop count separated is more, side-play amount is less, thus the effective voltage accuracy improved in whole temperature range, its shortcoming is compensating circuit complex structure, increases area and the power consumption of chip; Different materials electric-resistivity method utilizes two kinds of resistance with different temperature coefficients to do secondary temperature compensation, and its shortcoming is large by technogenic influence, and extra one deck resistor mask version also increases design cost.

Summary of the invention

For improving the precision of bandgap voltage reference, the invention provides a kind of based on the linearizing Low Drift Temperature bandgap voltage reference of VBE, do traditional VBE linearization technique reference circuit structure and further to expand and perfect, object is to avoid current mirror mismatch and output resistance temperature characterisitic on the impact of high-order compensation precision.

For solving the problems of the technologies described above, the invention provides a kind of based on the linearizing Low Drift Temperature bandgap voltage reference of VBE, comprising PTAT current generating circuit, high-order compensation band gap reference circuit, start-up circuit one and start-up circuit two;

Described PTAT current generating circuit, for generation of bias voltage and the PTAT electric current of described high-order compensation band gap reference circuit;

Described high-order compensation band gap reference circuit, the difference being flowed through the triode base-emitter voltage VBE of collector by the electric current with different temperatures characteristic builds nonlinear terms, then superposes with VBE, offsets nonlinear terms wherein, exports the bandgap voltage reference of high-order compensation;

Described start-up circuit one, for generation of the starting current of described PTAT current generating circuit, avoids circuit to enter degeneracy bias point after the power-up, after startup completes, turns off starting current, reduces circuit power consumption;

Described start-up circuit two, for generation of the starting current of described high-order compensation band gap reference circuit, avoids circuit to enter degeneracy bias point after the power-up, after startup completes, turns off starting current, reduces circuit power consumption.

Wherein, described PTAT current generating circuit comprises operational amplifier A MP1, PMOS MP1, PMOS MP2, PNP pipe Q0, PNP pipe Q1 and resistance R0;

The source electrode of described PMOS MP1 and described PMOS MP2 connects direct supply, grid connects the output terminal of described operational amplifier A MP1, the drain electrode of described PMOS MP1 connects the negative input end of described operational amplifier A MP1, and the drain electrode of described PMOS MP2 connects the positive input terminal of described operational amplifier A MP1; One end of described resistance R0 connects the positive input terminal of described operational amplifier A MP1, the emitter of PNP pipe Q1 described in another termination; The emitter of described PNP pipe Q0 connects the negative input end of described operational amplifier A MP1, base stage, the grounded collector of described PNP pipe Q0 and described PNP pipe Q1.

Described high-order compensation band gap reference circuit comprises operational amplifier A MP2, PMOS MP3, PMOS MP4, PMOS MP5, PNP pipe Q2, PNP pipe Q3, PNP pipe Q4, PNP pipe Q5, resistance R1, resistance R2, resistance R3, resistance R4, resistance R10, NMOS tube MN1, NMOS tube MN2;

The source electrode of described PMOS MP3, described PMOS MP4 and described PMOS MP5 connects direct supply, grid connects the output terminal of described operational amplifier A MP1, the drain electrode of described PMOS MP3 connects the emitter of described PNP pipe Q2, and the drain electrode of described PMOS MP4 connects the emitter of described PNP pipe Q3; The base stage of described PNP pipe Q3 connects the emitter of described PNP pipe Q2, the grounded collector of described PNP pipe Q3, the base stage of described PNP pipe Q2, grounded collector; The drain electrode of described PMOS MP5 connects the drain electrode of described NMOS tube MN2, the grid of described NMOS tube MN1, described NMOS tube MN2 connects the drain electrode of described NMOS tube MN2, the source ground of described NMOS tube MN1 and described NMOS tube MN2, one end of the drain electrode connecting resistance R10 of described NMOS tube MN1, the other end of described resistance R10 connects the negative input end of described operational amplifier A MP2; One end of resistance R3 connects the emitter of described PNP pipe Q3, the other end of described resistance R3 connects the emitter of described PNP pipe Q4, the emitter of described PNP pipe Q5 connects the positive input terminal of described operational amplifier A MP2, base stage, the grounded collector of described PNP pipe Q4 and described PNP pipe Q5; One end of described resistance R1 connects the emitter of described PNP pipe Q4, the other end connects the negative input end of described operational amplifier A MP2, one end of described resistance R4 connects the negative input end of described operational amplifier A MP2, one end of described resistance R2 connects the positive input terminal of described operational amplifier A MP2, and the output terminal of the other end of described resistance R4, the other end of described resistance R2 and described operational amplifier A MP2 forms the output terminal of reference voltage V REF.

Described start-up circuit one, comprises PMOS MP6, PMOS MP7, NMOS tube MN3, NMOS tube MN4, NMOS tube MN5;

The source electrode of described PMOS MP6 and described PMOS MP7 connects direct supply, the grid of described PMOS MP6 connects the output terminal of described operational amplifier A MP1, the grounded-grid of described PMOS MP7, the drain electrode of described PMOS MP6 connects the drain electrode of described NMOS tube MN3, the drain electrode of described PMOS MP7 connects the drain electrode of described NMOS tube MN4, the grid of described NMOS tube MN3 and described NMOS tube MN4 connects the drain electrode of described NMOS tube MN3, the source ground of described NMOS tube MN3 and described NMOS tube MN4, the grid of described NMOS tube MN5 connects the drain electrode of described NMOS tube MN4, the output terminal of the drain electrode concatenation operation amplifier AMP1 of described NMOS tube MN5, the source ground of described NMOS tube MN5.

Described start-up circuit two comprises PMOS MP8, PMOS MP9, NMOS tube MN6, NMOS tube MN7, resistance R5;

The source electrode of described PMOS MP8 and described PMOS MP9 connects direct supply, the grid of described PMOS MP8 and described PMOS MP9 connects the output terminal of operational amplifier A MP1, the drain electrode of described PMOS MP8 connects the drain electrode of described NMOS tube MN6, the drain electrode of described PMOS MP9 connects the drain electrode of described NMOS tube MN7, the grid of described NMOS tube MN6 connects the drain electrode of described NMOS tube MN7, the source electrode of described NMOS tube MN6 connects the positive input terminal of operational amplifier A MP2, the output terminal of the grid concatenation operation amplifier AMP2 of described NMOS tube MN7, one end of the source electrode connecting resistance R5 of described NMOS tube MN7, the other end ground connection of resistance R5.

The zero-temperature coefficient feature set electrode current of described triode base is that the positive temperature coefficient (PTC) current summation that the difference Δ VBE superposing the negative temperature parameter current and triode base-emitter voltage that the voltage deducting a VBE is again added in the generation of resistance two ends by two VBE produces on resistance forms, and its temperature characterisitic is by the impact exporting branch current mirror mismatch and output resistance temperature characterisitic.

The Advantageous Effects that the present invention reaches:

1. whole circuit uses same type resistance, reduces mask quantity, saves design cost.

2. compared with traditional VBE linearization technique, this circuit adopts voltage-mode to export VREF, avoid current mirror mismatch and output resistance temperature characterisitic to the impact of compensation precision, thus obtain the reference voltage of high precision zero-temperature coefficient, and then solve the problems such as conversion accuracy is low.

3. whole reference circuit temperature coefficient is low to moderate 1.097ppm, and when frequency is 1KHz, its Power Supply Rejection Ratio (PSRR) can reach 82.3dB.

4. reference voltage source circuit of the present invention adopts parasitic PNP pipe, can realize under CMOS technology; Without the metal-oxide-semiconductor being operated in subthreshold region in circuit, debugging is simple, and stability is higher.

Accompanying drawing explanation

The each parts of Fig. 1 circuit of the present invention and connecting circuit figure thereof;

The temperature characteristics figure of reference circuit output voltage shown in Fig. 2 Fig. 1;

The power supply rejection ratio characteristics figure of reference circuit output voltage shown in Fig. 3 Fig. 1.

Wherein: 1PTAT current generating circuit; 2 high-order compensation band gap reference circuits; 3 start-up circuits one; 4 start-up circuits two.

Embodiment

In order to the technique effect that auditor can better understand technical characteristic of the present invention, technology contents and reach, now accompanying drawing of the present invention is described in detail in conjunction with the embodiments.But, shown accompanying drawing, just in order to technical scheme of the present invention is better described, so, auditor please not limit claims of the present invention with regard to accompanying drawing.

Below in conjunction with drawings and Examples, patent of the present invention is further illustrated.

As shown in Figure 1, the invention provides a kind of based on the linearizing Low Drift Temperature bandgap voltage reference of VBE, comprise PTAT current generating circuit, high-order compensation band gap reference circuit, start-up circuit one and start-up circuit two;

Described PTAT current generating circuit, for generation of bias voltage and the PTAT electric current of described high-order compensation band gap reference circuit;

Described high-order compensation band gap reference circuit, the difference being flowed through the triode base-emitter voltage VBE of collector by the electric current with different temperatures characteristic builds nonlinear terms, then superposes with VBE, offsets nonlinear terms wherein, exports the bandgap voltage reference of high-order compensation;

Described start-up circuit one, for generation of the starting current of described PTAT current generating circuit, avoids circuit to enter degeneracy bias point after the power-up, after startup completes, turns off starting current, reduces circuit power consumption;

Described start-up circuit two, for generation of the starting current of described high-order compensation band gap reference circuit, avoids circuit to enter degeneracy bias point after the power-up, after startup completes, turns off starting current, reduces circuit power consumption.

Wherein, described PTAT current generating circuit comprises operational amplifier A MP1, PMOS MP1, PMOS MP2, PNP pipe Q0, PNP pipe Q1 and resistance R0;

The source electrode of described PMOS MP1 and described PMOS MP2 connects direct supply, grid connects the output terminal of described operational amplifier A MP1, the drain electrode of described PMOS MP1 connects the negative input end of described operational amplifier A MP1, and the drain electrode of described PMOS MP2 connects the positive input terminal of described operational amplifier A MP1; One end of described resistance R0 connects the positive input terminal of described operational amplifier A MP1, the emitter of PNP pipe Q1 described in another termination; The emitter of described PNP pipe Q0 connects the negative input end of described operational amplifier A MP1, base stage, the grounded collector of described PNP pipe Q0 and described PNP pipe Q1.

Described high-order compensation band gap reference circuit comprises operational amplifier A MP2, PMOS MP3, PMOS MP4, PMOS MP5, PNP pipe Q2, PNP pipe Q3, PNP pipe Q4, PNP pipe Q5, resistance R1, resistance R2, resistance R3, resistance R4, resistance R10, NMOS tube MN1, NMOS tube MN2;

The source electrode of described PMOS MP3, described PMOS MP4 and described PMOS MP5 connects direct supply, grid connects the output terminal of described operational amplifier A MP1, the drain electrode of described PMOS MP3 connects the emitter of described PNP pipe Q2, and the drain electrode of described PMOS MP4 connects the emitter of described PNP pipe Q3; The base stage of described PNP pipe Q3 connects the emitter of described PNP pipe Q2, the grounded collector of described PNP pipe Q3, the base stage of described PNP pipe Q2, grounded collector; The drain electrode of described PMOS MP5 connects the drain electrode of described NMOS tube MN2, the grid of described NMOS tube MN1, described NMOS tube MN2 connects the drain electrode of described NMOS tube MN2, the source ground of described NMOS tube MN1 and described NMOS tube MN2, one end of the drain electrode connecting resistance R10 of described NMOS tube MN1, the other end of described resistance R10 connects the negative input end of described operational amplifier A MP2; One end of resistance R3 connects the emitter of described PNP pipe Q3, the other end of described resistance R3 connects the emitter of described PNP pipe Q4, the emitter of described PNP pipe Q5 connects the positive input terminal of described operational amplifier A MP2, base stage, the grounded collector of described PNP pipe Q4 and described PNP pipe Q5; One end of described resistance R1 connects the emitter of described PNP pipe Q4, the other end connects the negative input end of described operational amplifier A MP2, one end of described resistance R4 connects the negative input end of described operational amplifier A MP2, one end of described resistance R2 connects the positive input terminal of described operational amplifier A MP2, and the output terminal of the other end of described resistance R4, the other end of described resistance R2 and described operational amplifier A MP2 forms the output terminal of reference voltage V REF.

Described start-up circuit one, comprises PMOS MP6, PMOS MP7, NMOS tube MN3, NMOS tube MN4, NMOS tube MN5;

The source electrode of described PMOS MP6 and described PMOS MP7 connects direct supply, the grid of described PMOS MP6 connects the output terminal of described operational amplifier A MP1, the grounded-grid of described PMOS MP7, the drain electrode of described PMOS MP6 connects the drain electrode of described NMOS tube MN3, the drain electrode of described PMOS MP7 connects the drain electrode of described NMOS tube MN4, the grid of described NMOS tube MN3 and described NMOS tube MN4 connects the drain electrode of described NMOS tube MN3, the source ground of described NMOS tube MN3 and described NMOS tube MN4, the grid of described NMOS tube MN5 connects the drain electrode of described NMOS tube MN4, the output terminal of the drain electrode concatenation operation amplifier AMP1 of described NMOS tube MN5, the source ground of described NMOS tube MN5.

Described start-up circuit two comprises PMOS MP8, PMOS MP9, NMOS tube MN6, NMOS tube MN7, resistance R5;

The source electrode of described PMOS MP8 and described PMOS MP9 connects direct supply, the grid of described PMOS MP8 and described PMOS MP9 connects the output terminal of operational amplifier A MP1, the drain electrode of described PMOS MP8 connects the drain electrode of described NMOS tube MN6, the drain electrode of described PMOS MP9 connects the drain electrode of described NMOS tube MN7, the grid of described NMOS tube MN6 connects the drain electrode of described NMOS tube MN7, the source electrode of described NMOS tube MN6 connects the positive input terminal of operational amplifier A MP2, the output terminal of the grid concatenation operation amplifier AMP2 of described NMOS tube MN7, one end of the source electrode connecting resistance R5 of described NMOS tube MN7, the other end ground connection of resistance R5.

The zero-temperature coefficient feature set electrode current of described triode base is that the positive temperature coefficient (PTC) current summation that the difference Δ VBE superposing the negative temperature parameter current and triode base-emitter voltage that the voltage deducting a VBE is again added in the generation of resistance two ends by two VBE produces on resistance forms, and its temperature characterisitic is by the impact exporting branch current mirror mismatch and output resistance temperature characterisitic.

Principle Analysis of the present invention is as follows:

The expression of VBE is as follows:

$V_{\mathrm{BE}}=V_G\left(T_0\right)+[V_{\mathrm{BE}}\left(T_0\right)-V_G\left(T_0\right)]\left(\frac{T}{T_0}\right)-(\mathrm{\η}-\mathrm{\α})\left(\frac{\mathrm{KT}}{q}\right)\ln \left(\frac{T}{T_0}\right)---\left(1\right)$

In formula (1), VG (T ₀) be that silicon is at absolute zero T ₀time band gap voltage, k is Boltzmann constant, and q is electron charge, and η is the thermal constant relevant to audion, is determined by technique, is about 3.2.T ₀be reference temperature, the value of α is then determined by the character flowing through transistor collector electric current, if what flow through transistor collector is positive temperature current, then α=1, if what flow through transistor collector is zero-temperature coefficient electric current, then α=0.

The triode VBE2 of triode VBE1 and the zero-temperature coefficient current offset that the nonlinear terms containing TlnT generally adopt a positive temperature current to be biased makes difference and obtains:

$V_{\mathrm{BE}1}=V_G\left(T_0\right)+[V_{\mathrm{BE}1}\left(T_0\right)-V_G\left(T_0\right)]\left(\frac{T}{T_0}\right)-(\mathrm{\η}-1)\left(\frac{\mathrm{KT}}{q}\right)\ln \left(\frac{T}{T_0}\right)---\left(2\right)$

$V_{\mathrm{BE}2}=V_G\left(T_0\right)+[V_{\mathrm{BE}2}\left(T_0\right)-V_G\left(T_0\right)]\left(\frac{T}{T_0}\right)-(\mathrm{\η}-0)\left(\frac{\mathrm{KT}}{q}\right)\ln \left(\frac{T}{T_0}\right)---\left(3\right)$

Formula (2) subtracts formula (3) and can obtain:

$\mathrm{\Δ}{V}_{\mathrm{BE}}=V_{\mathrm{BE}1}-V_{\mathrm{BE}2}=[V_{\mathrm{BE}1}\left(T_0\right)-V_{\mathrm{BE}2}\left(T_0\right)]\left(\frac{T}{T_0}\right)+\left(\frac{\mathrm{KT}}{q}\right)\ln \left(\frac{T}{T_0}\right)---\left(4\right)$

Namely the nonlinear terms containing TlnT are obtained.

The electric current I 3 in Fig. 1, resistance R3 flowed through can be expressed as formula (5), is negative temperature electric current; Because two input terminal voltages of amplifier are equal, electric current I on resistance R1 1 available formula (6) represents, is positive temperature current, the circuit I Q4=I1+I3 on PNP pipe Q4, when suitable resistance value and current ratio, can make PNP pipe Q4 flows through zero-temperature coefficient electric current.Electric current I 2 on resistance R2 then available formula (7) represents, easily know flow through PNP pipe Q5 for positive temperature current.

V hereinafter described _bEn, n represents natural number, represents the base stage B of transistor Qn and the voltage difference of emitter E in Fig. 1, and V _eBn, represent crystal three and the transmitting extreme pressure E of pipe Qn and the voltage difference of base stage B in Fig. 1.

$\begin{array}{c}I3=\frac{V_{\mathrm{BE}3}+V_{\mathrm{BE}2}-V_{\mathrm{BE}4}}{R3}\\ =\frac{V_G\left(T_0\right)+[V_{\mathrm{EB}2}\left(T_0\right)+V_{\mathrm{EB}3}\left(T_0\right)-V_{\mathrm{EB}4}\left(T_0\right)-V_G\left(T_0\right)]\left(\frac{T}{T_0}\right)+(\mathrm{\η}-2)\left(\frac{\mathrm{KT}}{q}\right)\ln \left(\frac{T}{T_0}\right)}{R3}\end{array}---\left(5\right)$

$I1=\frac{V_{\mathrm{EB}5}-V_{\mathrm{EB}4}}{R1}=\frac{[V_{\mathrm{EB}5}\left(T_0\right)-V_{\mathrm{EB}4}\left(T_0\right)]\left(\frac{T}{T_0}\right)+\left(\frac{\mathrm{KT}}{q}\right)\ln \left(\frac{T}{T_0}\right)}{R1}---\left(6\right)$

$I2=\frac{\mathrm{VREF}-V_{\mathrm{EB}5}}{R2}---\left(7\right)$

From formula (4), the voltage at R1 two ends can be expressed as:

$\mathrm{\Δ}{V}_{\mathrm{BE}}=V_{\mathrm{EB}5}-V_{\mathrm{EB}4}=[V_{\mathrm{EB}5}\left(T_0\right)-V_{\mathrm{EB}4}\left(T_0\right)]\left(\frac{T}{T_0}\right)+\left(\frac{\mathrm{KT}}{q}\right)\ln \left(\frac{T}{T_0}\right)=I1*R1---\left(8\right)$

Again because the electric current I 0=V on resistance R0 _t* lnN/R0, electric current I 4=I1+I10 on resistance R4, get PNP pipe Q1, the ratio of PNP pipe Q0 collector current is N, PMOS MP5 is a with the number ratio of PMOS MP2, the value of [VBE5 (T0) – VBE4 (T0)] is constant when PNP pipe Q4 and PNP pipe Q5 collector current determine, makes its value equal b, then can obtain band gap voltage and export:

$\begin{array}{c}{V}_{\mathrm{REF}}=V_{\mathrm{EB}5}+I4*R4=V_{\mathrm{EB}5}+I10*R4+I1*R4\\ =V_{\mathrm{EB}5}+a\frac{R4}{R0}\left(\frac{\mathrm{KT}}{q}\right)\ln N+b\frac{R4}{R1}\left(\frac{T}{T_0}\right)+\frac{R4}{R1}\left(\frac{\mathrm{KT}}{q}\right)\ln \left(\frac{T}{T_0}\right)\end{array}---\left(9\right)$

Claims (3)

1. based on the linearizing Low Drift Temperature bandgap voltage reference of VBE, it is characterized in that: comprise PTAT current generating circuit, high-order compensation band gap reference circuit, start-up circuit one and start-up circuit two;

Described PTAT current generating circuit, for generation of bias voltage and the PTAT electric current of described high-order compensation band gap reference circuit;

Described high-order compensation band gap reference circuit, the difference being flowed through the triode base-emitter voltage VBE of collector by the electric current with different temperatures characteristic builds nonlinear terms, then superposes with VBE, offsets nonlinear terms wherein, exports the bandgap voltage reference of high-order compensation;

Described start-up circuit one, for generation of the starting current of described PTAT current generating circuit, avoids circuit to enter degeneracy bias point after the power-up, after startup completes, turns off starting current, reduces circuit power consumption;

Described start-up circuit two, for generation of the starting current of described high-order compensation band gap reference circuit, avoids circuit to enter degeneracy bias point after the power-up, after startup completes, turns off starting current, reduces circuit power consumption;

Described high-order compensation band gap reference circuit comprises operational amplifier A MP2, PMOS MP3, PMOS MP4, PMOS MP5, PNP pipe Q2, PNP pipe Q3, PNP pipe Q4, PNP pipe Q5, resistance R1, resistance R2, resistance R3, resistance R4, resistance R10, NMOS tube MN1, NMOS tube MN2;

The source electrode of described PMOS MP3, described PMOS MP4 and described PMOS MP5 connects direct supply, grid connects the output terminal of described operational amplifier A MP1, the drain electrode of described PMOS MP3 connects the emitter of described PNP pipe Q2, and the drain electrode of described PMOS MP4 connects the emitter of described PNP pipe Q3; The base stage of described PNP pipe Q3 connects the emitter of described PNP pipe Q2, the grounded collector of described PNP pipe Q3, the base stage of described PNP pipe Q2, grounded collector; The drain electrode of described PMOS MP5 connects the drain electrode of described NMOS tube MN2, the grid of described NMOS tube MN1, described NMOS tube MN2 connects the drain electrode of described NMOS tube MN2, the source ground of described NMOS tube MN1 and described NMOS tube MN2, one end of the drain electrode connecting resistance R10 of described NMOS tube MN1, the other end of described resistance R10 connects the negative input end of described operational amplifier A MP2; One end of resistance R3 connects the emitter of described PNP pipe Q3, the other end of described resistance R3 connects the emitter of described PNP pipe Q4, the emitter of described PNP pipe Q5 connects the positive input terminal of described operational amplifier A MP2, base stage, the grounded collector of described PNP pipe Q4 and described PNP pipe Q5; One end of described resistance R1 connects the emitter of described PNP pipe Q4, the other end connects the negative input end of described operational amplifier A MP2, one end of described resistance R4 connects the negative input end of described operational amplifier A MP2, one end of described resistance R2 connects the positive input terminal of described operational amplifier A MP2, and the output terminal of the other end of described resistance R4, the other end of described resistance R2 and described operational amplifier A MP2 forms the output terminal of reference voltage V REF;

Described start-up circuit two comprises PMOS MP8, PMOS MP9, NMOS tube MN6, NMOS tube MN7, resistance R5;

The source electrode of described PMOS MP8 and described PMOS MP9 connects direct supply, the grid of described PMOS MP8 and described PMOS MP9 connects the output terminal of operational amplifier A MP1, the drain electrode of described PMOS MP8 connects the drain electrode of described NMOS tube MN6, the drain electrode of described PMOS MP9 connects the drain electrode of described NMOS tube MN7, the grid of described NMOS tube MN6 connects the drain electrode of described NMOS tube MN7, the source electrode of described NMOS tube MN6 connects the positive input terminal of operational amplifier A MP2, the output terminal of the grid concatenation operation amplifier AMP2 of described NMOS tube MN7, one end of the source electrode connecting resistance R5 of described NMOS tube MN7, the other end ground connection of resistance R5.

2. according to claim 1 based on the linearizing Low Drift Temperature bandgap voltage reference of VBE, it is characterized in that: described PTAT current generating circuit comprises operational amplifier A MP1, PMOS MP1, PMOS MP2, PNP pipe Q0, PNP pipe Q1 and resistance R0;

The source electrode of described PMOS MP1 and described PMOS MP2 connects direct supply, grid connects the output terminal of described operational amplifier A MP1, the drain electrode of described PMOS MP1 connects the negative input end of described operational amplifier A MP1, and the drain electrode of described PMOS MP2 connects the positive input terminal of described operational amplifier A MP1; One end of described resistance R0 connects the positive input terminal of described operational amplifier A MP1, the emitter of PNP pipe Q1 described in another termination; The emitter of described PNP pipe Q0 connects the negative input end of described operational amplifier A MP1, base stage, the grounded collector of described PNP pipe Q0 and described PNP pipe Q1.

3. according to claim 1 based on the linearizing Low Drift Temperature bandgap voltage reference of VBE, it is characterized in that: described start-up circuit one, comprises PMOS MP6, PMOS MP7, NMOS tube MN3, NMOS tube MN4, NMOS tube MN5;

The source electrode of described PMOS MP6 and described PMOS MP7 connects direct supply, the grid of described PMOS MP6 connects the output terminal of operational amplifier A MP1, the grounded-grid of described PMOS MP7, the drain electrode of described PMOS MP6 connects the drain electrode of described NMOS tube MN3, the drain electrode of described PMOS MP7 connects the drain electrode of described NMOS tube MN4, the grid of described NMOS tube MN3 and described NMOS tube MN4 connects the drain electrode of described NMOS tube MN3, the source ground of described NMOS tube MN3 and described NMOS tube MN4, the grid of described NMOS tube MN5 connects the drain electrode of described NMOS tube MN4, the output terminal of the drain electrode concatenation operation amplifier AMP1 of described NMOS tube MN5, the source ground of described NMOS tube MN5.