CN104714588B - A kind of based on the linearizing Low Drift Temperature bandgap voltage reference of VBE - Google Patents

Abstract

The present invention is open a kind of based on the linearizing Low Drift Temperature bandgap voltage reference of VBE, and circuit comprises PTAT current generating circuit, high-order compensation band gap reference circuit, start-up circuit one and start-up circuit two.This reference circuit builds nonlinear terms by the difference of the different VBE of two collector current temperature characterisitics, then superpose with VBE, and counteracting nonlinear terms wherein, reach the effect of high-order compensation.Its zero-temperature coefficient feature set electrode current superposes by two VBE the voltage deducting a VBE to be again added in negative temperature parameter current that resistance R3 two ends produce and the positive temperature coefficient (PTC) current summation that Δ VBE produces on resistance R1 forms, temperature characterisitic by the impact of output voltage precision, not ensure that the precision of high-order compensation.Compared with traditional VBE linearization technique, this circuit adopts voltage-mode to export VREF, avoid current mirror mismatch and output resistance temperature characterisitic to the impact of compensation precision, thus obtain the reference voltage of high precision zero-temperature coefficient, and then solve the problems such as conversion accuracy is low.

Description

A Low Temperature Drift Bandgap Reference Voltage Source Based on VBE Linearization

technical field

The invention relates to the technical field of analog circuits, in particular to a low-temperature drift bandgap reference voltage source based on VBE linearization.

Background technique

The bandgap reference source is the most widely used reference source in modern large-scale integrated circuits, and is widely used in data conversion systems, power management systems, and memory systems. The basic principle is to use a voltage with a negative temperature coefficient (usually VBE, which refers to the voltage difference between the base B and the emitter E of the transistor) and a voltage with a positive temperature coefficient (usually △VBE, which refers to the difference between the two VBE difference) are superimposed so that their positive and negative temperature coefficients cancel each other out, thereby achieving a low temperature coefficient voltage.

With the improvement of system accuracy requirements, the temperature coefficient of the traditional first-order reference voltage has restricted the system accuracy. In the prior art, high-order temperature compensation technology is usually used to achieve a reference voltage with a lower temperature coefficient. The high-order temperature compensation technology generally uses an additional high-order compensation circuit to generate a nonlinear positive temperature coefficient voltage and a first-order reference voltage. stacked to achieve a low temperature coefficient reference circuit. Existing high-order compensation techniques include exponential curvature compensation method, VBE linearization, piecewise linearization, and compensation methods using different temperature coefficients of resistance of different materials. Exponential temperature compensation uses the law that the current gain β of the triode changes exponentially with the temperature to compensate the reference voltage. The disadvantage is that the range of β variation in practice limits the compensation effect. In addition, the power supply voltage requirement is relatively high, generally at 5V; The VBE linearization method uses the nonlinear voltage component generated by the superposition of two VBEs with different collector current temperature characteristics to offset the nonlinear term in the VBE. The disadvantage is that the circuit has high requirements for the accuracy of the resistance ratio, and the output resistance of the output branch Temperature coefficient, etc. will affect the accuracy of high-order compensation; piecewise linear compensation divides the entire temperature range into several segments, and in each small segment, the offset of the reference voltage with temperature will be greatly reduced. The more segments are divided, the offset The smaller the amount, the voltage accuracy in the entire temperature range can be effectively improved. The disadvantage is that the structure of the compensation circuit is complex, which increases the area and power consumption of the chip; the resistance method of different materials uses two kinds of resistance with different temperature coefficients as the secondary temperature Compensation, its disadvantage is that it is greatly affected by the process, and an additional layer of resistive mask also increases the design cost.

Contents of the invention

In order to improve the accuracy of the bandgap reference voltage source, the present invention provides a low-temperature drift bandgap reference voltage source based on VBE linearization, which further expands and improves the reference circuit structure of the traditional VBE linearization technology, with the purpose of avoiding current mirror Effect of Mismatch and Output Resistor Temperature Characteristics on Higher-Order Compensation Accuracy.

In order to solve the above technical problems, the present invention provides a low-temperature drift bandgap reference voltage source based on VBE linearization, including a PTAT current generation circuit, a high-order compensation bandgap reference circuit, a start-up circuit 1 and a start-up circuit 2;

The PTAT current generation circuit is used to generate the bias voltage and PTAT current of the high-order compensated bandgap reference circuit;

The high-order compensated bandgap reference circuit constructs a non-linear term through the difference between the triode base-emitter voltage VBE of the current with different temperature characteristics flowing through the collector, and then superimposes it with VBE to cancel the non-linear term, and outputs a high Bandgap reference voltage for order compensation;

The first described start-up circuit is used to generate the start-up current of the PTAT current generating circuit to prevent the circuit from entering a degenerate bias point after power-on, and when the start-up is completed, turn off the start-up current to reduce power consumption of the circuit;

The second start-up circuit is used to generate the start-up current of the high-order compensated bandgap reference circuit, so as to prevent the circuit from entering the degenerate bias point after power-on, and turn off the start-up current after the start-up is completed to reduce power consumption of the circuit .

Wherein, the PTAT current generating circuit includes an operational amplifier AMP1, a PMOS transistor MP1, a PMOS transistor MP2, a PNP transistor Q0, a PNP transistor Q1, and a resistor R0;

The sources of the PMOS transistor MP1 and the PMOS transistor MP2 are connected to a DC power supply, the gates are connected to the output terminal of the operational amplifier AMP1, and the drains of the PMOS transistor MP1 are connected to the negative input terminal of the operational amplifier AMP1. The drain of the PMOS transistor MP2 is connected to the positive input terminal of the operational amplifier AMP1; one end of the resistor R0 is connected to the positive input terminal of the operational amplifier AMP1, and the other end is connected to the emitter of the PNP transistor Q1; the PNP The emitter of the transistor Q0 is connected to the negative input terminal of the operational amplifier AMP1, and the bases and collectors of the PNP transistor Q0 and the PNP transistor Q1 are grounded.

The high-order compensation bandgap reference circuit includes operational amplifier AMP2, PMOS transistor MP3, PMOS transistor MP4, PMOS transistor MP5, PNP transistor Q2, PNP transistor Q3, PNP transistor Q4, PNP transistor Q5, resistor R1, resistor R2, resistor R3, resistor R4, resistor R10, NMOS tube MN1, NMOS tube MN2;

The sources of the PMOS transistor MP3, the PMOS transistor MP4 and the PMOS transistor MP5 are connected to a DC power supply, the gate is connected to the output terminal of the operational amplifier AMP1, and the drain of the PMOS transistor MP3 is connected to the PNP transistor Q2 The emitter of the PMOS transistor MP4 is connected to the emitter of the PNP transistor Q3; the base of the PNP transistor Q3 is connected to the emitter of the PNP transistor Q2, and the collector of the PNP transistor Q3 is grounded. The base and collector of the PNP transistor Q2 are grounded; the drain of the PMOS transistor MP5 is connected to the drain of the NMOS transistor MN2, and the gates of the NMOS transistor MN1 and the NMOS transistor MN2 are connected to the NMOS transistor The drain of MN2, the sources of the NMOS transistor MN1 and the NMOS transistor MN2 are grounded, the drain of the NMOS transistor MN1 is connected to one end of the resistor R10, and the other end of the resistor R10 is connected to the negative terminal of the operational amplifier AMP2. Input terminal; one end of the resistor R3 is connected to the emitter of the PNP transistor Q3, the other end of the resistor R3 is connected to the emitter of the PNP transistor Q4, and the emitter of the PNP transistor Q5 is connected to the positive terminal of the operational amplifier AMP2 The input terminal, the base and collector of the PNP transistor Q4 and the PNP transistor Q5 are grounded; one end of the resistor R1 is connected to the emitter of the PNP transistor Q4, and the other end is connected to the negative input terminal of the operational amplifier AMP2 , one end of the resistor R4 is connected to the negative input terminal of the operational amplifier AMP2, one end of the resistor R2 is connected to the positive input terminal of the operational amplifier AMP2, the other end of the resistor R4, the other end of the resistor R2 and the output terminal of the operational amplifier AMP2 form the output terminal of the reference voltage VREF.

The start-up circuit one includes PMOS transistor MP6, PMOS transistor MP7, NMOS transistor MN3, NMOS transistor MN4, and NMOS transistor MN5;

The sources of the PMOS transistor MP6 and the PMOS transistor MP7 are connected to a DC power supply, the gate of the PMOS transistor MP6 is connected to the output end of the operational amplifier AMP1, the gate of the PMOS transistor MP7 is grounded, and the gate of the PMOS transistor MP7 is connected to the ground. The drain of MP6 is connected to the drain of the NMOS transistor MN3, the drain of the PMOS transistor MP7 is connected to the drain of the NMOS transistor MN4, and the gates of the NMOS transistor MN3 and the NMOS transistor MN4 are connected to the NMOS transistor MN4. The drain of the transistor MN3, the sources of the NMOS transistor MN3 and the NMOS transistor MN4 are grounded, the gate of the NMOS transistor MN5 is connected to the drain of the NMOS transistor MN4, and the drain of the NMOS transistor MN5 is connected to the operation The output terminal of the amplifier AMP1 and the source of the NMOS transistor MN5 are grounded.

The start-up circuit two includes PMOS transistor MP8, PMOS transistor MP9, NMOS transistor MN6, NMOS transistor MN7, and resistor R5;

The sources of the PMOS transistor MP8 and the PMOS transistor MP9 are connected to a DC power supply, the gates of the PMOS transistor MP8 and the PMOS transistor MP9 are connected to the output terminal of the operational amplifier AMP1, and the drains of the PMOS transistor MP8 are connected to the The drain of the NMOS transistor MN6, the drain of the PMOS transistor MP9 is connected to the drain of the NMOS transistor MN7, the gate of the NMOS transistor MN6 is connected to the drain of the NMOS transistor MN7, and the drain of the NMOS transistor MN6 The source is connected to the positive input terminal of the operational amplifier AMP2, the gate of the NMOS transistor MN7 is connected to the output terminal of the operational amplifier AMP2, the source of the NMOS transistor MN7 is connected to one end of the resistor R5, and the other end of the resistor R5 is grounded.

The zero-temperature characteristic collector current of the triode base is generated by the difference ΔVBE between the negative temperature coefficient current generated at both ends of the resistor and the base-emitter voltage of the triode by superimposing two VBEs and then subtracting a VBE voltage. The positive temperature coefficient current is added, and its temperature characteristics are not affected by the mismatch of the output branch current mirror and the temperature characteristics of the output resistance.

Beneficial technical effect achieved by the present invention:

1. The whole circuit uses the same type of resistors, reducing the number of reticles and saving design costs.

2. Compared with the traditional VBE linearization method, the circuit adopts the voltage mode output VREF, which avoids the influence of current mirror mismatch and output resistance temperature characteristics on the compensation accuracy, thereby obtaining a high-precision reference voltage with zero temperature coefficient, and then solving the conversion low precision issues.

3. The temperature coefficient of the entire reference circuit is as low as 1.097ppm, and its power supply rejection ratio (PSRR) can reach 82.3dB when the frequency is 1KHz.

4. The reference voltage source circuit of the present invention adopts a parasitic PNP transistor, which can be realized under the CMOS process; there is no MOS transistor working in the sub-threshold region in the circuit, and the debugging is simple and the stability is higher.

Description of drawings

Fig. 1 each component of the circuit of the present invention and its connection circuit diagram;

The temperature characteristic graph of the output voltage of the reference circuit shown in Fig. 2 Fig. 1;

Figure 3 Figure 1 shows the reference circuit output voltage power supply rejection ratio characteristic diagram.

Among them: 1PTAT current generation circuit; 2 high-order compensation bandgap reference circuit; 3 start circuit one; 4 start circuit two.

detailed description

In order for examiners to better understand the technical features, technical contents and technical effects of the present invention, the accompanying drawings of the present invention will now be described in more detail in conjunction with the embodiments. However, the drawings shown are only for better explaining the technical solution of the present invention, so the examiner is requested not to limit the protection scope of the claims of the present invention based on the drawings.

Below in conjunction with accompanying drawing and embodiment the patent of the present invention is further described.

As shown in Figure 1, the present invention provides a low-temperature drift bandgap reference voltage source based on VBE linearization, including a PTAT current generation circuit, a high-order compensation bandgap reference circuit, a start-up circuit 1 and a start-up circuit 2;

The PTAT current generation circuit is used to generate the bias voltage and PTAT current of the high-order compensated bandgap reference circuit;

The high-order compensated bandgap reference circuit constructs a non-linear term through the difference between the triode base-emitter voltage VBE of the current with different temperature characteristics flowing through the collector, and then superimposes it with VBE to cancel the non-linear term, and outputs a high Bandgap reference voltage for order compensation;

The first described start-up circuit is used to generate the start-up current of the PTAT current generating circuit to prevent the circuit from entering a degenerate bias point after power-on, and when the start-up is completed, turn off the start-up current to reduce power consumption of the circuit;

The second start-up circuit is used to generate the start-up current of the high-order compensated bandgap reference circuit, so as to prevent the circuit from entering the degenerate bias point after power-on, and turn off the start-up current after the start-up is completed to reduce power consumption of the circuit .

Wherein, the PTAT current generating circuit includes an operational amplifier AMP1, a PMOS transistor MP1, a PMOS transistor MP2, a PNP transistor Q0, a PNP transistor Q1, and a resistor R0;

The sources of the PMOS transistor MP1 and the PMOS transistor MP2 are connected to a DC power supply, the gates are connected to the output terminal of the operational amplifier AMP1, and the drains of the PMOS transistor MP1 are connected to the negative input terminal of the operational amplifier AMP1. The drain of the PMOS transistor MP2 is connected to the positive input terminal of the operational amplifier AMP1; one end of the resistor R0 is connected to the positive input terminal of the operational amplifier AMP1, and the other end is connected to the emitter of the PNP transistor Q1; the PNP The emitter of the transistor Q0 is connected to the negative input terminal of the operational amplifier AMP1, and the bases and collectors of the PNP transistor Q0 and the PNP transistor Q1 are grounded.

The high-order compensation bandgap reference circuit includes operational amplifier AMP2, PMOS transistor MP3, PMOS transistor MP4, PMOS transistor MP5, PNP transistor Q2, PNP transistor Q3, PNP transistor Q4, PNP transistor Q5, resistor R1, resistor R2, resistor R3, resistor R4, resistor R10, NMOS tube MN1, NMOS tube MN2;

The sources of the PMOS transistor MP3, the PMOS transistor MP4 and the PMOS transistor MP5 are connected to a DC power supply, the gate is connected to the output terminal of the operational amplifier AMP1, and the drain of the PMOS transistor MP3 is connected to the PNP transistor Q2 The emitter of the PMOS transistor MP4 is connected to the emitter of the PNP transistor Q3; the base of the PNP transistor Q3 is connected to the emitter of the PNP transistor Q2, and the collector of the PNP transistor Q3 is grounded. The base and collector of the PNP transistor Q2 are grounded; the drain of the PMOS transistor MP5 is connected to the drain of the NMOS transistor MN2, and the gates of the NMOS transistor MN1 and the NMOS transistor MN2 are connected to the NMOS transistor The drain of MN2, the sources of the NMOS transistor MN1 and the NMOS transistor MN2 are grounded, the drain of the NMOS transistor MN1 is connected to one end of the resistor R10, and the other end of the resistor R10 is connected to the negative terminal of the operational amplifier AMP2. Input terminal; one end of the resistor R3 is connected to the emitter of the PNP transistor Q3, the other end of the resistor R3 is connected to the emitter of the PNP transistor Q4, and the emitter of the PNP transistor Q5 is connected to the positive terminal of the operational amplifier AMP2 The input terminal, the base and collector of the PNP transistor Q4 and the PNP transistor Q5 are grounded; one end of the resistor R1 is connected to the emitter of the PNP transistor Q4, and the other end is connected to the negative input terminal of the operational amplifier AMP2 , one end of the resistor R4 is connected to the negative input terminal of the operational amplifier AMP2, one end of the resistor R2 is connected to the positive input terminal of the operational amplifier AMP2, the other end of the resistor R4, the other end of the resistor R2 and the output terminal of the operational amplifier AMP2 form the output terminal of the reference voltage VREF.

The start-up circuit one includes PMOS transistor MP6, PMOS transistor MP7, NMOS transistor MN3, NMOS transistor MN4, and NMOS transistor MN5;

The sources of the PMOS transistor MP6 and the PMOS transistor MP7 are connected to a DC power supply, the gate of the PMOS transistor MP6 is connected to the output end of the operational amplifier AMP1, the gate of the PMOS transistor MP7 is grounded, and the gate of the PMOS transistor MP7 is connected to the ground. The drain of MP6 is connected to the drain of the NMOS transistor MN3, the drain of the PMOS transistor MP7 is connected to the drain of the NMOS transistor MN4, and the gates of the NMOS transistor MN3 and the NMOS transistor MN4 are connected to the NMOS transistor MN4. The drain of the transistor MN3, the sources of the NMOS transistor MN3 and the NMOS transistor MN4 are grounded, the gate of the NMOS transistor MN5 is connected to the drain of the NMOS transistor MN4, and the drain of the NMOS transistor MN5 is connected to the operation The output terminal of the amplifier AMP1 and the source of the NMOS transistor MN5 are grounded.

The start-up circuit two includes PMOS transistor MP8, PMOS transistor MP9, NMOS transistor MN6, NMOS transistor MN7, and resistor R5;

The sources of the PMOS transistor MP8 and the PMOS transistor MP9 are connected to a DC power supply, the gates of the PMOS transistor MP8 and the PMOS transistor MP9 are connected to the output terminal of the operational amplifier AMP1, and the drains of the PMOS transistor MP8 are connected to the The drain of the NMOS transistor MN6, the drain of the PMOS transistor MP9 is connected to the drain of the NMOS transistor MN7, the gate of the NMOS transistor MN6 is connected to the drain of the NMOS transistor MN7, and the drain of the NMOS transistor MN6 The source is connected to the positive input terminal of the operational amplifier AMP2, the gate of the NMOS transistor MN7 is connected to the output terminal of the operational amplifier AMP2, the source of the NMOS transistor MN7 is connected to one end of the resistor R5, and the other end of the resistor R5 is grounded.

The zero-temperature characteristic collector current of the triode base is generated by the difference ΔVBE between the negative temperature coefficient current generated at both ends of the resistor and the base-emitter voltage of the triode by superimposing two VBEs and then subtracting a VBE voltage. The positive temperature coefficient current is added, and its temperature characteristics are not affected by the mismatch of the output branch current mirror and the temperature characteristics of the output resistance.

Principle of work of the present invention is analyzed as follows:

The specific expression of VBE is as follows:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; G</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span><span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; G</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; \&eta;</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; \&alpha;</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; KT</span>}}{\mathrm{<span\; class="notranslate">\; q</span>}}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; ln</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

In formula (1), VG(T ₀ ) is the bandgap voltage of silicon at absolute zero T ₀ , k is the Boltzmann constant, q is the electronic charge, and η is a temperature constant related to the triode structure, which is determined by the process , about 3.2. T ₀ is the reference temperature, and the value of α is determined by the nature of the current flowing through the collector of the triode. If the current flowing through the collector of the triode is a positive temperature current, then α=1. If the current flowing through the collector of the triode is zero temperature current, then α=0.

The nonlinear term including TlnT is generally obtained by using a triode VBE1 biased by a positive temperature current and a triode VBE2 biased by a zero temperature current to obtain:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; G</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span><span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; G</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; \&eta;</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; KT</span>}}{\mathrm{<span\; class="notranslate">\; q</span>}}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; ln</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; G</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span><span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; G</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; \&eta;</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 0</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; KT</span>}}{\mathrm{<span\; class="notranslate">\; q</span>}}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; ln</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

Formula (2) minus formula (3) can get:

$\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span><span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; KT</span>}}{\mathrm{<span\; class="notranslate">\; q</span>}}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; ln</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

That is, the nonlinear term including TlnT is obtained.

The current I3 flowing through the resistor R3 in Figure 1 can be expressed as formula (5), which is a negative temperature current; since the voltages of the two input terminals of the op amp are equal, the current I1 on the resistor R1 can be expressed by formula (6), which is a positive temperature Current, the circuit IQ4=I1+I3 on the PNP transistor Q4, when the appropriate resistance value and current ratio, can make the zero temperature current flow through the PNP transistor Q4. The current I2 on the resistor R2 can be expressed by formula (7), and it is easy to know that the current flowing through the PNP transistor Q5 is a positive temperature current.

In the V _BEn described below, n represents a natural number, which means the voltage difference _between the base B and the emitter E of the transistor Qn in FIG. Pole B voltage difference.

$\begin{array}{c}\mathrm{<span\; class="notranslate">\; I</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}\\ <span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; G</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span><span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; EB</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; EB</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; EB</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; G</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; \&eta;</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; KT</span>}}{\mathrm{<span\; class="notranslate">\; q</span>}}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; ln</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}\end{array}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$

$\mathrm{<span\; class="notranslate">\; I</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; EB</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; EB</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>\frac{<span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; EB</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; EB</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span><span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; KT</span>}}{\mathrm{<span\; class="notranslate">\; q</span>}}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; ln</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; )</span>$

$\mathrm{<span\; class="notranslate">\; I</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; VREF</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; EB</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 7</span>}<span\; class="notranslate">\; )</span>$

It can be seen from formula (4) that the voltage across R1 can be expressed as:

$\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; EB</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; EB</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; EB</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; EB</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span><span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; KT</span>}}{\mathrm{<span\; class="notranslate">\; q</span>}}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; ln</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; I</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; )</span>$

And because the current I0=V _T *lnN/R0 on the resistor R0, and the current I4=I1+I10 on the resistor R4, the ratio of the collector current of the PNP transistor Q1 and the PNP transistor Q0 is N, and the PMOS transistor MP5 and the PMOS transistor MP2 The number ratio is a, and the value of [VBE5(T0)–VBE4(T0)] is a constant when the collector currents of PNP transistor Q4 and PNP transistor Q5 are determined. If its value is equal to b, the bandgap voltage output can be obtained:

$\begin{array}{c}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; REF</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; EB</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; I</span>}\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; EB</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; I</span>}\mathrm{<span\; class="notranslate">\; 10</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; I</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 4</span>}\\ <span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; EB</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; a</span>}\frac{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; KT</span>}}{\mathrm{<span\; class="notranslate">\; q</span>}}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; b</span>}\frac{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; KT</span>}}{\mathrm{<span\; class="notranslate">\; q</span>}}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; ln</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; )</span>\end{array}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 9</span>}<span\; class="notranslate">\; )</span>$

Claims (3)

1. A low-temperature drift bandgap reference voltage source based on VBE linearization, characterized in that: comprise a PTAT current generating circuit, a high-order compensation bandgap reference circuit, a starting circuit one and a starting circuit two; The PTAT current generation circuit is used to generate the bias voltage and PTAT current of the high-order compensated bandgap reference circuit; The high-order compensated bandgap reference circuit constructs a non-linear term through the difference between the triode base-emitter voltage VBE of the current with different temperature characteristics flowing through the collector, and then superimposes it with VBE to cancel the non-linear term, and outputs a high Bandgap reference voltage for order compensation; The first described start-up circuit is used to generate the start-up current of the PTAT current generating circuit to prevent the circuit from entering a degenerate bias point after power-on, and when the start-up is completed, turn off the start-up current to reduce power consumption of the circuit; The second start-up circuit is used to generate the start-up current of the high-order compensated bandgap reference circuit, so as to prevent the circuit from entering the degenerate bias point after power-on, and turn off the start-up current after the start-up is completed to reduce power consumption of the circuit ; The high-order compensation bandgap reference circuit includes operational amplifier AMP2, PMOS transistor MP3, PMOS transistor MP4, PMOS transistor MP5, PNP transistor Q2, PNP transistor Q3, PNP transistor Q4, PNP transistor Q5, resistor R1, resistor R2, resistor R3, resistor R4, resistor R10, NMOS tube MN1, NMOS tube MN2; The sources of the PMOS transistor MP3, the PMOS transistor MP4 and the PMOS transistor MP5 are connected to a DC power supply, the gate is connected to the output terminal of the operational amplifier AMP1, and the drain of the PMOS transistor MP3 is connected to the PNP transistor Q2 The emitter of the PMOS transistor MP4 is connected to the emitter of the PNP transistor Q3; the base of the PNP transistor Q3 is connected to the emitter of the PNP transistor Q2, and the collector of the PNP transistor Q3 is grounded. The base and collector of the PNP transistor Q2 are grounded; the drain of the PMOS transistor MP5 is connected to the drain of the NMOS transistor MN2, and the gates of the NMOS transistor MN1 and the NMOS transistor MN2 are connected to the NMOS transistor The drain of MN2, the sources of the NMOS transistor MN1 and the NMOS transistor MN2 are grounded, the drain of the NMOS transistor MN1 is connected to one end of the resistor R10, and the other end of the resistor R10 is connected to the negative terminal of the operational amplifier AMP2. Input terminal; one end of the resistor R3 is connected to the emitter of the PNP transistor Q3, the other end of the resistor R3 is connected to the emitter of the PNP transistor Q4, and the emitter of the PNP transistor Q5 is connected to the positive terminal of the operational amplifier AMP2 The input terminal, the base and collector of the PNP transistor Q4 and the PNP transistor Q5 are grounded; one end of the resistor R1 is connected to the emitter of the PNP transistor Q4, and the other end is connected to the negative input terminal of the operational amplifier AMP2 , one end of the resistor R4 is connected to the negative input terminal of the operational amplifier AMP2, one end of the resistor R2 is connected to the positive input terminal of the operational amplifier AMP2, the other end of the resistor R4, the other end of the resistor R2 and the output end of the operational amplifier AMP2 constitute the output end of the reference voltage VREF; The start-up circuit two includes PMOS transistor MP8, PMOS transistor MP9, NMOS transistor MN6, NMOS transistor MN7, and resistor R5; The sources of the PMOS transistor MP8 and the PMOS transistor MP9 are connected to a DC power supply, the gates of the PMOS transistor MP8 and the PMOS transistor MP9 are connected to the output terminal of the operational amplifier AMP1, and the drains of the PMOS transistor MP8 are connected to the The drain of the NMOS transistor MN6, the drain of the PMOS transistor MP9 is connected to the drain of the NMOS transistor MN7, the gate of the NMOS transistor MN6 is connected to the drain of the NMOS transistor MN7, and the drain of the NMOS transistor MN6 The source is connected to the positive input terminal of the operational amplifier AMP2, the gate of the NMOS transistor MN7 is connected to the output terminal of the operational amplifier AMP2, the source of the NMOS transistor MN7 is connected to one end of the resistor R5, and the other end of the resistor R5 is grounded. 2. The low-temperature drift bandgap reference voltage source based on VBE linearization according to claim 1, characterized in that: the PTAT current generation circuit comprises operational amplifier AMP1, PMOS transistor MP1, PMOS transistor MP2, PNP transistor Q0, PNP Tube Q1 and resistor R0; The sources of the PMOS transistor MP1 and the PMOS transistor MP2 are connected to a DC power supply, the gates are connected to the output terminal of the operational amplifier AMP1, and the drains of the PMOS transistor MP1 are connected to the negative input terminal of the operational amplifier AMP1. The drain of the PMOS transistor MP2 is connected to the positive input terminal of the operational amplifier AMP1; one end of the resistor R0 is connected to the positive input terminal of the operational amplifier AMP1, and the other end is connected to the emitter of the PNP transistor Q1; the PNP The emitter of the transistor Q0 is connected to the negative input terminal of the operational amplifier AMP1, and the bases and collectors of the PNP transistor Q0 and the PNP transistor Q1 are grounded. 3. The low-temperature drift bandgap reference voltage source based on VBE linearization according to claim 1, characterized in that: said start-up circuit one includes PMOS transistor MP6, PMOS transistor MP7, NMOS transistor MN3, NMOS transistor MN4, NMOS transistor Tube MN5; The sources of the PMOS transistor MP6 and the PMOS transistor MP7 are connected to a DC power supply, the gate of the PMOS transistor MP6 is connected to the output end of the operational amplifier AMP1, the gate of the PMOS transistor MP7 is grounded, and the gate of the PMOS transistor MP6 is connected to the output terminal of the operational amplifier AMP1. The drain is connected to the drain of the NMOS transistor MN3, the drain of the PMOS transistor MP7 is connected to the drain of the NMOS transistor MN4, and the gates of the NMOS transistor MN3 and the NMOS transistor MN4 are connected to the NMOS transistor MN3 The drain of the NMOS transistor MN3 and the source of the NMOS transistor MN4 are grounded, the gate of the NMOS transistor MN5 is connected to the drain of the NMOS transistor MN4, and the drain of the NMOS transistor MN5 is connected to the operational amplifier AMP1 The output terminal of the NMOS transistor MN5 is grounded.