CN103246311B - Non-resistor band-gap reference voltage source with high-order curvature compensation - Google Patents

Abstract

The invention relates to a reference voltage source and discloses a non-resistor band-gap reference voltage source with high-order curvature compensation. According to the technical scheme, the reference voltage source comprises a first current source module, a second current source module, a high-order current generating module and a reference voltage generation module. A first bias voltage generated by the first current source module is connected with one input end of the high-order current generating module and one input end of the reference voltage generation module. A second bias voltage generated by the second current source module is connected with the other input end of the high-order current generating module, a third bias voltage generated by the high-order current generating module is connected with the other input end of the reference voltage generation module, and an output end of the reference voltage generation module outputs a reference voltage. According to the non-resistor band-gap reference voltage source, the high-order curvature compensation method is used, so that the band-gap reference voltage source of the low-voltage coefficient is obtained.

Description

With the Bandgap Reference Without Resistors of source compensated by using high-order curvature

Technical field

The present invention relates to a kind of reference voltage source, belong to Analogous Integrated Electronic Circuits technical field.

Background technology

In Analogous Integrated Electronic Circuits or mixed-signal designs field, reference voltage source is extremely important and conventional module, be applied in the circuit such as simulation and digital quantizer, power converter, power amplifier, its effect is for system provides one not with the voltage reference that temperature and supply voltage change.

Traditional reference voltage source relies on band-gap reference circuit to produce usually, and as shown in Figure 1, it comprises error amplifier A1, the mirror current source that PMOS M1, M2 and M3 are formed, resistance R1, R2 and PNP pipe T1, T2, T3.Then obtain reference output voltage V according to the voltage-current characteristic of bipolar transistor _rEF

$V_{\mathrm{REF}}=V_{\mathrm{EBQ}3}+\frac{R_2}{R_1}{V}_T\ln N$

Wherein V _eBQ3emitter and the base voltage difference of bipolar transistor T3; k is Boltzmann constant, and q is the electricity of unit charge, and T is temperature.

Although for the single order item of temperature, but voltage V _eBQ3temperature characterisitic be in nonlinear, therefore the temperature characterisitic of the bandgap voltage reference of prior art can not reach good effect, needs the reference voltage precision that the compensation way adopting other reaches higher.In addition, bandgap voltage reference due to prior art needs to realize by resistance, in some specific techniques, such as standard digital CMOS (Complementary Metal-Oxide-Semiconductor) technique does not often have Resistance model for prediction or Resistance model for prediction and unreliable, and conventional architectures therefore cannot be used to come design basis source.Although have in prior art to produce the technology that order current carrys out compensation band gap reference voltage source, above-mentioned shortcoming still exists, and temperature characterisitic not ideal enough.

Summary of the invention

Technical matters to be solved by this invention, is just to provide a kind of Bandgap Reference Without Resistors with source compensated by using high-order curvature, adopts source compensated by using high-order curvature method, obtains the bandgap voltage reference of lower temperature coefficient.

The present invention solve the technical problem, and the technical scheme of employing is, with the Bandgap Reference Without Resistors of source compensated by using high-order curvature, comprises the first current source module, the second current source module, order current generation module and reference voltage generation module; First current source module is for generation of positive temperature coefficient (PTC) electric current, and the second current source module is for generation of negative temperature parameter current;

Wherein, the first bias voltage that the first current source module produces is connected to the first input end of order current generation module and the first input end of reference voltage generation module; The second bias voltage that second current source module produces is connected to the second input end of order current generation module, and the 3rd bias voltage that order current generation module produces is connected to the second input end of reference voltage generation module; The output terminal output reference voltage of reference voltage generation module.

Concrete, described order current generation module comprises, PMOS: MP1, MP2, MP3, MP4, MP5, MP6, MPN1, MPN2, MPN3, MPN4, NMOS tube: MN1, MN2, MN3, MN4, and operational amplifier; Wherein: the grid of MP1 inputs the first bias voltage with the grid phase downlink connection of MP2, MP3, source electrode connects supply voltage, and drain electrode connects the grid of MN1 and the grid of drain electrode and MN2, and the source electrode of MN1 connects earth potential; The source electrode of MN2 connects earth potential, and drain electrode connects the substrate electric potential of the grid of the drain electrode of MP2 and MPN1, drain electrode, source electrode and MPN2, and the substrate of MPN1 connects earth potential; The grid of MPN2, drain electrode, source electrode are connected and are connected to the drain electrode of MP3 and the reverse input end of operational amplifier; The source electrode of MP2, MP3 all connects supply voltage; The in-phase input end of operational amplifier connects the grid of the drain electrode of MP4 and MPN3, drain electrode, source electrode, export be connected to MP4, MP6 grid as output the 3rd bias voltage of this module, the source electrode of MP4 connects supply voltage; The substrate electric potential of MPN3 is connected to the drain electrode of the grid of MPN4, drain electrode, source electrode and MP5, MN3, and the substrate of MPN4 is connected to earth potential; The grid of MP5 connects input second bias voltage, and source electrode connects supply voltage; The grid of MN3 connects the grid of MN4 and the drain electrode of drain electrode and MP6, and the source electrode of MN3 and MN4 connects earth potential; The source electrode of MP6 connects supply voltage.

Concrete, described reference voltage generation module comprises, PMOS: MP7, MP8, MP9, MP10, MP11, MP12, NMOS tube: MN5, MN6, MN7, MN8, and PNP pipe: Q1; Wherein, the grid of MP7 inputs the first bias voltage with the grid phase downlink connection of MP8, MP10, and source electrode connects supply voltage, and drain electrode connects the grid of MN5 and the grid of drain electrode and MN6, MN7, and the source electrode of MN5 connects earth potential; The source electrode of MN6 connects earth potential, and drain electrode connects the drain electrode of MP11 and the grid of MN8; The grid of MP11 connects the drain electrode of MP8, MP9 and the emitter of Q1, and source electrode connects the source electrode of MP12 and the drain electrode of MP10, MN8, and the source electrode of MN8 connects earth potential; The grid of MP12 and the output terminal of the drain electrode of drain electrode phase downlink connection MN7 as reference voltage generation module, the source electrode of MN7 connects earth potential; The source electrode of MP8, MP9, MP10 all connects supply voltage, and the grid of MP9 connects input the 3rd bias voltage; The base stage of Q1 is connected with collector and is connected to earth potential.

The invention has the beneficial effects as follows, owing to adopting source compensated by using high-order curvature, the emitter of bipolar transistor and base voltage difference is made to be approximately the negative temperature coefficient voltage changed with temperature linearity, then the linearization voltage of a positive temperature coefficient (PTC) is superposed by reference voltage generation module, produce reference output voltage, therefore this bandgap voltage reference has better temperature characterisitic, can provide higher reference voltage precision.Bandgap voltage reference of the present invention does not adopt Resistance model for prediction, so can more compatible non-resistances or the not high technique of Resistance model for prediction precision well, and such as Standard Digital CMOS etc.

Accompanying drawing explanation

Fig. 1 is prior art bandgap voltage reference schematic diagram;

Fig. 2 is bandgap voltage reference structural representation of the present invention;

Fig. 3 is order current generation module structural representation;

Fig. 4 is reference voltage generation module structural representation;

Fig. 5 is that bandgap voltage reference output voltage of the present invention varies with temperature oscillogram;

Fig. 6 is bandgap voltage reference output voltage PSRR oscillogram of the present invention.

Wherein, M1, M2, M3, MP1, MP2, MP3, MP4, MP5, MP6, MPN1, MPN2, MPN3, MPN4, MP7, MP8, MP9, MP10, MP11, MP12 are PMOS (P-Metal-Oxide-Semiconductor) pipe; MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8 are NMOS (N-Metal-Oxide-Semiconductor) pipe; T1, T2, T3, Q1 are PNP pipe (PNP transistor); R1, R2 are resistance; A1, OP are operational amplifier.

Specific embodiments

Below in conjunction with accompanying drawing and specific embodiment, the present invention is described in further detail.

For the drawback existing for traditional bandgap reference voltage source, the present invention proposes a kind of High-precision resistance-free band-gap reference voltage source with source compensated by using high-order curvature, physical circuit framework as shown in Figure 2, comprise the first current source module, second current source module, order current generation module, reference voltage generation module four parts.First current source module is for generation of positive temperature coefficient (PTC) electric current, and the second current source module is for generation of negative temperature parameter current.

Wherein, the first current source module produces the first bias voltage VB1 and is connected to the first input end of order current generation module and the first input end of reference voltage generation module; Second current source module produces the second input end that the second bias voltage VB2 is connected to order current generation module, and the 3rd bias voltage VB3 that order current generation module produces is connected to the second input end of reference voltage generating circuit; The output terminal output reference voltage VREF of reference voltage generation module.

In such scheme, order current generation module as shown in Figure 3, it is by 10 PMOS: (wherein MPN1, MPN2, MPN3, MPN4 use as PN junction for MP1, MP2, MP3, MP4, MP5, MP6, MPN1, MPN2, MPN3, MPN4, so its substrate electric potential connected mode can be described, other PMOS substrate electric potentials all connect supply voltage VIN), 4 NMOS tube: MN1, MN2, MN3, MN4, and an operational amplifier OP forms.Concrete annexation is: the grid of MP1 inputs the first bias voltage VB1 with the grid phase downlink connection of MP2, MP3, and source electrode connects supply voltage VIN, and drain electrode connects the grid of MN1 and the grid of drain electrode and MN2, and the source electrode of MN1 connects earth potential VSS; The source electrode of MN2 connects earth potential VSS, and drain electrode connects the substrate electric potential of the grid of the drain electrode of MP2 and MPN1, drain electrode, source electrode and MPN2, and the substrate of MPN1 connects earth potential; The grid of MPN2, drain electrode, source electrode are connected the reverse input end of the drain electrode that is connected to MP3 and operational amplifier OP; The source electrode of MP2, MP3 all connects supply voltage VIN; The in-phase input end of operational amplifier OP connects the grid of the drain electrode of MP4 and MPN3, drain electrode, source electrode, exports the grid that is connected to MP4, MP6 and connects supply voltage VIN as the source electrode of output the 3rd bias voltage VB3 of this module, MP4; The substrate electric potential of MPN3 is connected to the drain electrode of the grid of MPN4, drain electrode, source electrode and MP5, MN3, and the substrate of MPN4 is connected to earth potential; The grid of MP5 connects input second bias voltage VB2, and source electrode connects supply voltage VIN; The grid of MN3 connects the grid of MN4 and the drain electrode of drain electrode and MP6, and the source electrode of MN3 and MN4 connects earth potential; The source electrode of MP6 connects supply voltage VIN.

As shown in Figure 4, it is by 6 PMOS MP7, MP8, MP9, MP10, MP11, MP12 for said reference voltage generating module, 4 NMOS tube MN5, MN6, MN7, MN8, and a PNP bipolar transistor Q1 forms.Concrete annexation is: the grid of MP7 inputs the first bias voltage VB1 with the grid phase downlink connection of MP8, MP10, and source electrode connects supply voltage VIN, and drain electrode connects the grid of MN5 and the grid of drain electrode and MN6, MN7, and the source electrode of MN5 connects earth potential; The source electrode of MN6 connects earth potential, and drain electrode connects the drain electrode of MP11 and the grid of MN8; The grid of MP11 connects the drain electrode of MP8, MP9 and the emitter of Q1, and source electrode connects the source electrode of MP12 and the drain electrode of MP10, MN8, and the source electrode of MN8 connects earth potential; The grid of MP12 and the output terminal VREF of the drain electrode of drain electrode phase downlink connection MN7 as benchmark, the source electrode of MN7 connects earth potential; The source electrode of MP8, MP9, MP10 all connects supply voltage VIN, and the grid of MP9 connects input the 3rd bias voltage VB3; The base stage of Q1 is connected with collector and is connected to earth potential VSS.

The concrete structure of above-mentioned first current source module and the second current source module see related data, no longer can be described the circuit framework of these two modules at this, is only described some key principle used.Wherein the first current source module is by the V of two PNP transistor _eBvoltage difference produces PTAT voltage △ V _eB, and this voltage be added on the metal-oxide-semiconductor two ends that are operated in linear zone and produce μ V _t ^{^2}electric current; And the second current source module is by extracting metal-oxide-semiconductor threshold voltage, and extracted threshold voltage is added in the metal-oxide-semiconductor two ends that work in linear zone and produces μ V _tH ^{^2}electric current.Due to mobility [mu]=CT in metal-oxide-semiconductor ^-n, wherein C is constant coefficient, and n value is the constant of about 1.5; And V _tHfor the threshold voltage of NMOS tube, V _tH=V _tH0(1-λ T) raises linear reduction (V with temperature _tH0for the threshold voltage of metal-oxide-semiconductor during temperature 0K, λ is the absolute value temperature coefficient of NMOS tube threshold voltage); In addition linear increase is raised with temperature.Therefore in gap reference voltage source proposed by the invention, the first current source module produces positive temperature coefficient (PTC) electric current, and the second current source module produces negative temperature parameter current.

In above-mentioned order current generation module, the breadth length ratio of MP1, MP2, MP3 is identical, and grid all connects the first bias voltage VB1 again, and the electric current therefore flowing through them is also identical, so the electric current I that MP1, MP2, MP3 flow through ₁=K ₁μ V _t ^{^2}(K ₁for constant coefficient); And the grid of MP5 connects the second bias voltage VB2, so the electric current I that MP5 flows through ₂=K ₂μ V _tH ^{^2}(k ₂for constant coefficient); The breadth length ratio of transistor MP4, MP6 is identical in addition, and grid voltage is the 3rd bias voltage VB3, and the electric current therefore flowing through MP4, MP6 is also identical, is order current I ₃.Electric current and MN2 electric current in MP3 will be made like this to offset, and in MP4, electric current and MN3 electric current offset, thus the electric current flowing through MPN1 is provided by MP2, and the electric current flowing through MPN4 is provided by MP5.

Be below the principle of work of order current generation module: due to the clamping action of operational amplifier OP, make the in-phase input end of amplifier identical with reverse input end voltage, therefore VN=VP, simultaneously the order current I of the output terminal of OP again needed for control MP4 generation ₃; The grid of PMOS MPN1, MPN2, MPN3, MPN4, drain electrode, source electrode are connected as an input end again, and substrate is as another one input end, therefore a PN junction is formed, wherein one end of being connected of grid, drain electrode, source electrode is as the forward end of PN junction, substrate, as the backward end of PN junction, is therefore obtained by PN junction current-voltage correlation:

(wherein n, m are 1,2,3,4, the sequence number for MPN1 ~ MNPN4)

V again _mPN1+ V _mPN2=V _mPN3+ V _mPN4

Therefore can obtain

$I_3=\frac{{I_1}^{^2}}{I_2}=\frac{{K_1}^{^2}\mathrm{\μ}{V_T}^{^4}}{K_2{V_{\mathrm{TH}}}^{^2}}=K_3\frac{T^{4-n}}{{(1-\mathrm{\λT})}^2}$ (K ₃for constant coefficient)

Because λ is less, therefore

$\frac{1}{{(1-\mathrm{\λT})}^2}\≈{(1+\mathrm{\λT})}^2$

I ₃≈K ₃T ^4-n(1+λT) ²

So order current generation module produces high-order temperature coefficient current, this electric current may be used for compensating non-linear when high temperature of emitter bipolar transistor and base voltage difference VEB voltage, thus produce an approximate voltage VEB with temperature linearity change, for the generation of reference voltage lays the foundation.

PMOS MPN1, MPN2, MPN3, MPN4 are connected into PN junction by order current generation module of the present invention in addition, tradition is replaced to adopt BJT (Bipolar Junction Transistor) to produce order current, not only substantially reduce the area of chip design, and this circuit also overcomes employing traditional B JT base current to the adverse effect of order current generation module.

The electric current that first current source module and order current generation module produce is carried out current mirror to said reference voltage generating module and superposition is input in PNP bipolar transistor, thus flow into Q ₁electric current

$I_{Q1}={\mathrm{AI}}_1+B{I}_3=A{T}^{2-n}+B{K}_3{T}^{4-n}{(1+\mathrm{\λT})}^2=A{T}^{2-n}[1+\frac{B{K}_3{T}^2{(1+\mathrm{\λT})}^2}{A}]$

And

$\begin{array}{c}{V}_{\mathrm{EBQ}1}=V_T\ln \left[I_{Q1}{T}^{-\mathrm{\η}}\mathrm{Eexp}\left(\frac{V_{G0}}{V_T}\right)\right]\\ =V_{G0}+V_T\ln \mathrm{AE}-(\mathrm{\η}+n-2)V_T\ln T+V_T\ln [1+\frac{{\mathrm{BK}}_3{T}^2{(1+\mathrm{\λT})}^2}{A}]\end{array}$

Again

ln(1+x)≈x-x ^{^2}/2

$\begin{array}{c}{V}_{\mathrm{EBQ}1}\≈V_{G0}+V_T\ln \mathrm{AE}-(\mathrm{\η}+n-2)V_T\ln T+\frac{\mathrm{KB}{K}_3{T}^2{(1+\mathrm{\λT})}^{2}T}{\mathrm{qA}}[1-\frac{B{K}_3{T}^2{(1+\mathrm{\λT})}^2}{2A}]\\ \≈V_{G0}+V_T\ln \mathrm{AE}-(\mathrm{\η}+n-2)V_T\ln T+\frac{\mathrm{KB}{K}_3}{2q{A}^2}[2A{T}^3+4\mathrm{A\λ}{T}^4+(2A{\mathrm{\λ}}^2-B{K}_3)T^5]\end{array}$

Wherein V _g0for the band gap voltage of silicon during temperature 0K; η is the constant coefficient of value about 3.5; A, B are the mirroring ratios of current mirror, can arrange by changing MP8, MP9 breadth length ratio; K ₃for constant coefficient, can be arranged by MP1, MP3, MP4, MP5 breadth length ratio changed in order current generation module; E is temperature independent constant.Due to V _eBQ1in formula, last is the high-order term such as cube item, biquadratic item, five items comprising temperature.Therefore V is come from _tthe non-linear of lnT can be offset by reasonably arranging MP1, MP3, MP4, MP5 breadth length ratio in the breadth length ratio parameter of MP8, MP9 and order current generation module, thus makes V _eBQ1voltage becomes the approximate voltage reduced with temperature linearity.

In this reference voltage generation module, transistor MP10, MN6, MN7 flow through electric current and are μ V _t ^{^2}the image current of electric current, the electric current therefore flowing through MP11 and MP12 is also μ V _t ^{^2}the constant coefficient of electric current doubly.

So

$I_{\mathrm{MP}11}=M_1\mathrm{\μ}{V_T}^{^2}=\frac{\mathrm{\μ}{C}_{\mathrm{OX}}}{2}{\left(\frac{W}{L}\right)}_{\mathrm{MP}11}{(V_{\mathrm{GSMP}11}-V_{\mathrm{THP}})}^2$ (M ₁for constant coefficient)

$I_{\mathrm{MP}12}=M_2\mathrm{\μ}{V_T}^{^2}=\frac{\mathrm{\μ}{C}_{\mathrm{OX}}}{2}{\left(\frac{W}{L}\right)}_{\mathrm{MP}12}{(V_{\mathrm{GSMP}12}-V_{\mathrm{THP}})}^2$ (M ₂for constant coefficient)

Therefore

$V_{\mathrm{GSMP}11}=\frac{2M_1}{C_{\mathrm{OX}}}{\left(\frac{L}{W}\right)}_{\mathrm{MP}11}{V}_T+V_{\mathrm{THP}}$

$V_{\mathrm{GSMP}12}=\frac{2M_2}{C_{\mathrm{OX}}}{\left(\frac{L}{W}\right)}_{\mathrm{MP}12}{V}_T+V_{\mathrm{THP}}$

Again

VREF＝V _BEQ1+V _GSMP11-V _GSMP12

So

$\mathrm{VREF}=V_{\mathrm{BEQ}1}+\frac{2}{C_{\mathrm{OX}}}[M_1{\left(\frac{L}{W}\right)}_{\mathrm{MP}11}-M_2{\left(\frac{L}{W}\right)}_{\mathrm{MP}12}]V_T$

Therefore by rationally arranging the breadth length ratio of M1, M2 and MP11, MP12, can finally make so finally obtain an approximate not temperature variant reference voltage V REF.

In this module, the effect of MP8 is used to generation feedback loop, and for the current balance type on Duo Tiaozhi road, this negative feedback simultaneously also increases the PSRR (Power Supply Rejection Ratio) of reference circuit.

High precision non-resistance band gap reference proposed by the invention, shown by hspice emulation, in temperature range from-40 DEG C to 100 DEG C, its temperature coefficient only has 4.2ppm/ DEG C, as shown in Figure 5.Input voltage is from 2.4V to 5V, and its bandgap voltage reference variation range only has 1mV.When input voltage 3V, 25 DEG C and without low frequency PSRR when plug-in capacitor up to 56dB, as shown in Figure 6.

Those of ordinary skill in the art will appreciate that, embodiment described here is that protection scope of the present invention is not limited to so special statement and embodiment in order to help reader understanding's principle of the present invention.Those of ordinary skill in the art can make various other various concrete distortion and combination of not departing from essence of the present invention according to these technology enlightenment disclosed by the invention, and these distortion and combination are still in protection scope of the present invention.

Claims (1)

1., with the Bandgap Reference Without Resistors of source compensated by using high-order curvature, comprise the first current source module, the second current source module, order current generation module and reference voltage generation module; First current source module is for generation of positive temperature coefficient (PTC) electric current, and the second current source module is for generation of negative temperature parameter current;

Wherein, the first bias voltage that the first current source module produces is connected to the first input end of order current generation module and the first input end of reference voltage generation module; The second bias voltage that second current source module produces is connected to the second input end of order current generation module, and the 3rd bias voltage that order current generation module produces is connected to the second input end of reference voltage generation module; The output terminal output reference voltage of reference voltage generation module;

Described order current generation module comprises, PMOS: MP1, MP2, MP3, MP4, MP5, MP6, MPN1, MPN2, MPN3, MPN4, NMOS tube: MN1, MN2, MN3, MN4, and operational amplifier; Wherein: the grid of MP1 inputs the first bias voltage with the grid phase downlink connection of MP2, MP3, source electrode connects supply voltage, and drain electrode connects the grid of MN1 and the grid of drain electrode and MN2, and the source electrode of MN1 connects earth potential; The source electrode of MN2 connects earth potential, and drain electrode connects the substrate electric potential of the grid of the drain electrode of MP2 and MPN1, drain electrode, source electrode and MPN2, and the substrate of MPN1 connects earth potential; The grid of MPN2, drain electrode, source electrode are connected and are connected to the drain electrode of MP3 and the reverse input end of operational amplifier; The source electrode of MP2, MP3 all connects supply voltage; The in-phase input end of operational amplifier connects the grid of the drain electrode of MP4 and MPN3, drain electrode, source electrode, export be connected to MP4, MP6 grid as output the 3rd bias voltage of this module, the source electrode of MP4 connects supply voltage; The substrate electric potential of MPN3 is connected to the drain electrode of the grid of MPN4, drain electrode, source electrode and MP5, MN3, and the substrate of MPN4 is connected to earth potential; The grid of MP5 connects input second bias voltage, and source electrode connects supply voltage; The grid of MN3 connects the grid of MN4 and the drain electrode of drain electrode and MP6, and the source electrode of MN3 and MN4 connects earth potential; The source electrode of MP6 connects supply voltage;

Described reference voltage generation module comprises, PMOS: MP7, MP8, MP9, MP10, MP11, MP12, NMOS tube: MN5, MN6, MN7, MN8, and PNP pipe: Q1; Wherein, the grid of MP7 inputs the first bias voltage with the grid phase downlink connection of MP8, MP10, and source electrode connects supply voltage, and drain electrode connects the grid of MN5 and the grid of drain electrode and MN6, MN7, and the source electrode of MN5 connects earth potential; The source electrode of MN6 connects earth potential, and drain electrode connects the drain electrode of MP11 and the grid of MN8; The grid of MP11 connects the drain electrode of MP8, MP9 and the emitter of Q1, and source electrode connects the source electrode of MP12 and the drain electrode of MP10, MN8, and the source electrode of MN8 connects earth potential; The grid of MP12 and the output terminal of the drain electrode of drain electrode phase downlink connection MN7 as reference voltage generation module, the source electrode of MN7 connects earth potential; The source electrode of MP8, MP9, MP10 all connects supply voltage, and the grid of MP9 connects input the 3rd bias voltage; The base stage of Q1 is connected with collector and is connected to earth potential.