CN102122190B - Voltage reference source circuit and method for generating voltage reference source - Google Patents

Abstract

The invention relates to an integrated circuit and discloses a voltage reference source circuit and a method for generating a voltage reference source. The method comprises the following steps of: generating a self-adaption nonlinear PTAT (positive temperature coefficient) current through a high-order temperature coefficient compensation circuit; converting the current into a self-adaption nonlinear PTAT voltage and then superposing the voltage with a first-order reference voltage; and generating the reference voltage approximate to zero-temperature coefficient, as the voltage reference source. The self-adaption nonlinear PTAT voltage counteracts the nonlinear negative temperature coefficient in the first-order reference voltage, so the voltage reference source has lower temperature coefficient. In addition, the structure is simple, the compensation branch stability is better and the influence on the initial precision of the voltage reference source is small.

Description

Voltage reference source circuit

Technical field

The present invention relates to integrated circuit, particularly the voltage-reference in integrated circuit.

Background technology

Band gap voltage reference source is one of IP circuit important in Analogous Integrated Electronic Circuits and hybrid digital-analog integrated circuit design.Its Main Function is at low pressure difference linear voltage regulator (Low Dropout Regulator, be called for short " LDO "), DC-DC (DC-to-dc conversion), analog to digital converter (Analog DigitalConverter, be called for short " ADC ")/digital to analog converter (Digital Analog Converter, be called for short " DAC ") and system level chip (System on Chip, be called for short " SoC ") provide stable voltage or electric current in system, in fine measuring instrument, be also widely used simultaneously.

Existing band gap voltage reference source is based on two poor Δ V of transistor base-emitter voltage _bEproduce positive temperature coefficient (PTC) voltage and transistor base and emitter voltage both end voltage V _bEthe principle of negative temperature coefficient linear superposition.Along with improving constantly of accuracy requirement in circuit design, due to residual certain temperature coefficient still after the linear compensation of reference voltage, its index temperature coefficient is difficult to meet the requirement of high performance analog circuit.Therefore adopt high-order temperature compensated technology to realize the reference voltage of lower temperature coefficient, high-order temperature compensated is generally the reference circuit that utilizes extra high-order compensation circuit to produce non-linear positive temperature coefficient (PTC) voltage and single order reference voltage to superpose to realize low-temperature coefficient.

Specifically, in current a kind of scheme, adopt the number of the PMOS pipe (P type metal-oxide-semiconductor) in digital switch control access calibration circuit, regulated the equivalent channel length of point pressure pipe and control tube, thereby obtain the reference voltage of low-temperature coefficient.Although this band gap voltage reference source circuit can reach lower nonlinear temperature coefficient, as: simulation result 10.6ppm/ ℃.But due to the impact of operational amplifier offset voltage and temperature coefficient thereof, while application in High Definition Systems, will inevitably produce serious influence to the temperature coefficient of reference voltage and precision.Meanwhile, obtain accurate reference voltage, carry out more careful raceway groove regulation and control with regard to increasing the quantity of switch.This has also increased the complicacy of whole system steering logic and the quantity of chip limb.

In current another kind of scheme, produce single order, second order, the three positive temperature characterisitic electric currents in rank by design, after passing ratio stack, be converted to non-linear positive temperature characterisitic voltage, thereby non-linear negative temperature coefficient in reference voltage is offset.Its emulation Optimal Temperature coefficient is 0.7ppm/ ℃, although this structure can realize the reference voltage that temperature coefficient is sub-1ppm/ ℃ magnitude, but its temperature coefficient stability is along with the variation of process corner, the positive temperature characterisitic electric current of high-order has greatly changed, because its ratio is fixed, therefore the non-linear positive temperature characterisitic after its stack is compared with ideal value very large deviation can be occurred, cannot carry out the compensation of high-order self-adaptive temperature, and due to the non-ideal characteristic of amplifier, can make reference voltage temperature coefficient further degenerate, also can affect the precision of output voltage simultaneously.

Summary of the invention

The object of the present invention is to provide a kind of voltage reference source circuit and method for generating voltage reference source, realize and there is ultralow temperature coefficient and the comparatively stable voltage-reference of temperature coefficient with better simply structure.

For solving the problems of the technologies described above, embodiments of the present invention provide a kind of voltage reference source circuit, comprise:

Benchmark core circuit, for generating positive temperature coefficient (PTC) electric current;

High-order tc compensation circuit, for generating that size of current varies with temperature and the non-linear positive temperature coefficient (PTC) electric current that changes;

Reference voltage output circuit, be positive temperature coefficient (PTC) voltage for the positive temperature coefficient (PTC) current conversion that benchmark core circuit is generated, and a negative temperature coefficient voltage and positive temperature coefficient (PTC) voltage are superposeed, obtain single order reference voltage, be non-linear positive temperature coefficient (PTC) voltage by the non-linear positive temperature coefficient (PTC) current conversion of high-order tc compensation circuit evolving, and non-linear positive temperature coefficient (PTC) voltage and the single order reference voltage of conversion are superposeed, obtain voltage-reference.

Embodiments of the present invention also provide a kind of method for generating voltage reference source, comprise following steps:

Generate positive temperature coefficient (PTC) electric current and negative temperature coefficient voltage;

Be positive temperature coefficient (PTC) voltage by the positive temperature coefficient (PTC) current conversion of generation, and the positive temperature coefficient (PTC) voltage after the negative temperature coefficient voltage of generation and conversion is superposeed, obtain single order reference voltage;

Generate that size of current varies with temperature and the non-linear positive temperature coefficient (PTC) electric current that changes;

Be non-linear positive temperature coefficient (PTC) voltage by the non-linear positive temperature coefficient (PTC) current conversion generating, and non-linear positive temperature coefficient (PTC) voltage and the single order reference voltage of conversion are superposeed, obtain voltage-reference.

Compared with prior art, the key distinction and effect thereof are embodiment of the present invention:

Produce a kind of self-adaptation nonlinear PTAT (positive temperature coefficient (PTC)) electric current by high-order tc compensation circuit, after being converted into a self-adaptation nonlinear PTAT voltage, this electric current superposes with single order reference voltage, produce a kind of reference voltage of approximate zero temperature coefficient, as voltage-reference.Because this nonlinear adaptive PTAT voltage is offset the non-linear negative temperature coefficient in single order reference voltage, thereby make voltage-reference there is lower temperature coefficient.That is to say, high-order temperature compensated technology, having retained on the basis of single order benchmark primary characteristic, has self-adaptation nonlinear tc compensation characteristic, has greatly improved the temperature coefficient of voltage-reference.And, be simple in structurely easy to integratedly, compensation branch road stability is better, and less to the initial Accuracy of voltage-reference.

Further, utilize the base-emitter voltage difference of two triodes, generate positive temperature coefficient (PTC) electric current; Utilize the base-emitter of a triode, generate negative temperature coefficient voltage; Utilize a PMOS pipe to generate non-linear positive temperature coefficient (PTC) electric current.Further guaranteed of the present invention simple in structure, be easy to realize.

Further, voltage reference source circuit also comprises feedback biasing loop, is used to the benchmark core circuit that generates positive temperature coefficient (PTC) electric current that bias voltage and electric current are provided, and forms feedback control loop with this benchmark core circuit.Because this feedback biasing loop can provide stable DC point, therefore can guarantee the steady operation of circuit.

Accompanying drawing explanation

Fig. 1 is according to the schematic diagram of the voltage reference source circuit of first embodiment of the invention;

Fig. 2 is according to the schematic diagram of the voltage reference source circuit of second embodiment of the invention;

Fig. 3 is the concrete structure figure according to the voltage reference source circuit of second embodiment of the invention;

Fig. 4 is the concrete structure figure that realizes current branch according to the use one PTAT electric current in second embodiment of the invention;

Fig. 5 is according to the non-linear PTAT current diagram of the high-order tc compensation circuit evolving in second embodiment of the invention;

Fig. 6 is according to the effect temperature compensation schematic diagram reaching in second embodiment of the invention;

Fig. 7 is the method for generating voltage reference source process flow diagram according to third embodiment of the invention.

Embodiment

In the following description, in order to make reader understand the application better, many ins and outs have been proposed.But, persons of ordinary skill in the art may appreciate that even without these ins and outs and the many variations based on following embodiment and modification, also can realize the each claim of the application technical scheme required for protection.

For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, embodiments of the present invention are described in further detail.

Core of the present invention is, in voltage reference source circuit, comprises:

Benchmark core circuit, for generating positive temperature coefficient (PTC) electric current;

High-order tc compensation circuit, for generating that size of current varies with temperature and the non-linear positive temperature coefficient (PTC) electric current that changes;

Reference voltage output circuit, be positive temperature coefficient (PTC) voltage for the positive temperature coefficient (PTC) current conversion that this benchmark core circuit is generated, and a negative temperature coefficient voltage and described positive temperature coefficient (PTC) voltage that this reference voltage output circuit is generated superpose, obtain single order reference voltage, be non-linear positive temperature coefficient (PTC) voltage by the non-linear positive temperature coefficient (PTC) current conversion of described high-order tc compensation circuit evolving, and described non-linear positive temperature coefficient (PTC) voltage and the described single order reference voltage of conversion are superposeed, obtain voltage-reference.

First embodiment of the invention relates to a kind of voltage reference source circuit.In the present embodiment, by obtaining single order reference voltage after positive temperature coefficient (PTC) voltage and the stack of negative temperature coefficient voltage, and utilize a PMOS pipe to produce non-linear positive temperature coefficient (PTC) electric current, after being converted into self-adaptation nonlinear PTAT (positive temperature coefficient (PTC)) voltage, this electric current superposes with single order reference voltage, produce a kind of reference voltage of approximate zero temperature coefficient, using the reference voltage producing as voltage-reference.

Specifically as shown in Figure 1, this voltage reference source circuit comprises:

Benchmark core circuit 101, for generating positive temperature coefficient (PTC) electric current.Specifically, benchmark core circuit is by utilizing the base-emitter voltage difference delta V of two triodes _bE, generate positive temperature coefficient (PTC) electric current.

Reference voltage output circuit 102, is positive temperature coefficient (PTC) voltage for the positive temperature coefficient (PTC) current conversion that benchmark core circuit is generated, and a negative temperature coefficient voltage and positive temperature coefficient (PTC) voltage is superposeed, and obtains single order reference voltage.Wherein, reference voltage output circuit can be utilized the base-emitter of a triode, generates negative temperature coefficient voltage.

High-order tc compensation circuit 103, for generating that size of current varies with temperature and the non-linear positive temperature coefficient (PTC) electric current that changes.This high-order tc compensation circuit can be by utilizing a PMOS pipe to generate non-linear positive temperature coefficient (PTC) electric current.

Reference voltage output circuit 102 is also for being non-linear positive temperature coefficient (PTC) voltage by the non-linear positive temperature coefficient (PTC) current conversion of high-order tc compensation circuit evolving, and non-linear positive temperature coefficient (PTC) voltage and the single order reference voltage of conversion are superposeed, obtain voltage-reference.Certainly, it will be appreciated by those skilled in the art that, the nonlinear temperature characteristic of the non-linear positive temperature coefficient (PTC) voltage after conversion, the temperature characterisitic of the negative temperature coefficient voltage generating with reference voltage output circuit 102 circuit working temperature range planted agent is approximate identical, so that realize preferably the reference voltage of ultralow temperature coefficient characteristics.

In the present embodiment, produce a kind of self-adaptation nonlinear PTAT (positive temperature coefficient (PTC)) electric current by high-order tc compensation circuit, after being converted into a self-adaptation nonlinear PTAT voltage, this electric current superposes with single order reference voltage, produce a kind of reference voltage of approximate zero temperature coefficient, as voltage-reference.Because this nonlinear adaptive PTAT voltage is offset the non-linear negative temperature coefficient of the negative temperature coefficient voltage generating, thereby make reference voltage there is lower temperature coefficient.That is to say, high-order temperature compensated technology, having retained on the basis of single order benchmark primary characteristic, has self-adaptation nonlinear tc compensation characteristic, has greatly improved reference voltage temperature coefficient.And, be easy to integratedly due to simple in structure, compensation branch road stability is better, and less to the initial Accuracy of reference voltage.

Second embodiment of the invention relates to a kind of voltage reference source circuit.Present embodiment, on the basis of the first embodiment, has been carried out supplementing in details.

Specifically, the voltage reference source circuit in present embodiment also comprises feedback biasing loop 104 and start-up circuit 105.This feedback biasing loop is used to benchmark core circuit that bias voltage and electric current are provided, and forms feedback control loop with benchmark core circuit; This start-up circuit is used for starting benchmark core circuit, as shown in Figure 2.Below the concrete composition structure of the benchmark core circuit 101 in present embodiment, reference voltage output circuit 102, high-order tc compensation circuit 103 and feedback biasing loop 104 is described.

As shown in Figure 3, benchmark core circuit 101 is made up of 2 triodes, resistance, 2 NMOS pipes (N-type metal-oxide-semiconductor), 4 PMOS pipes.Specifically, benchmark core circuit 101 is by triode Q1, Q2; Resistance R 1; NMOS manages MN3, MN4; PMOS pipe MP4～MP7 forms jointly.Wherein Q1 is 1 with the ratio of the area of the emitter junction of Q2: N.MN3 and MN4 form current-mirror structure, the source potential of two NMOS pipes is equated, thereby in resistance R 1, produce Δ VBE pressure drop, thereby in benchmark core circuit, produce a PTAT electric current being directly proportional to absolute temperature.MP4～MP7 forms cascade Cascode current mirror, and the PTAT electric current producing in benchmark core circuit carries out proportional transmission by PMOS (MP4～MP7) Cascode current mirror.Wherein, MP4 and MP6 source electrode are all connected to supply voltage, the drain electrode of MP4 is connected to the source electrode of MP5, the drain electrode of MP6 is connected to the source electrode of MP7, the drain electrode of MP5 is connected to the drain electrode of MN3, the drain electrode of MP7 is connected to the drain electrode of MN4, the grid of MN3 and MN4 is connected, the source electrode of MN3 is connected with the emitter of Q1, the grid of MN4 is connected with drain electrode, and source electrode is connected with one end of R1, and an other end of this R1 is connected to the emitter of Q2, the base stage of Q1 is connected with collector and is connected to circuit potential minimum GND, and the base stage of Q2 is connected with collector and is connected to circuit potential minimum GND.

As shown in Figure 3, feedback biasing loop 104 is made up of 2 triodes, 2 NMOS pipes, 3 PMOS pipes.Specifically, feedback biasing loop is by triode Q4, Q5; NMOS manages MN1, MN2, PMOS pipe MP1～MP3 composition.The mode of biasing circuit by automatic biasing provides bias voltage and electric current for the PMOS Cascode current mirror in benchmark core circuit 101.Feedback biasing loop 104 forms feedback control loop with benchmark core circuit 101 simultaneously.Wherein, the base stage of Q4 is connected with collector and is connected to circuit potential minimum GND, the base stage of Q5 is connected with collector and is connected to circuit potential minimum GND, the grid of MN1 is connected to the grid of MN4, the source electrode of MN1 is connected with the emitter of Q5, the drain electrode of MN1 is connected to grid and the drain electrode of MP1, the grid of MN2 is connected with the drain electrode of described MN3, the source electrode of MN2 is connected with Q4 emitter, the drain electrode of MN2 is connected with the drain terminal of MP3, the grid of MP1 is connected with drain electrode, and the grid of MP1 is connected to the grid of MP5 and MP7, the source electrode of MP1 is connected with supply voltage, MP2 drain and gate is connected with drain electrode with the source electrode of MP3 respectively, and the grid of MP2 is connected to the grid of MP4 and MP6, the source electrode of MP2 is connected to supply voltage, the grid of MP3 is connected with the grid of MP1.MN3 → MN1 → MP1 → MP7 → MN4 → MN3 is regenerative feedback loop, MN3 → MN1 → MP1 → MP2 → MP6 → MN4 → MN3, and these two loops of MN3 → MN2 → MP2 → MP6 → MN4 → MN3 are feedback loop.As long as make feedback loop gain be greater than regenerative feedback loop gain, reference circuit just can steady operation.

As shown in Figure 3, reference voltage output circuit 102 is made up of a triode, a resistance, 2 PMOS pipes.Specifically, reference voltage output circuit 102 is by triode Q3; Resistance R 2, PMOS manages MP8, and MP9 forms, MP8, MP9 forms Cascode current mirror.Triode Q3 is that diode B-C knot short circuit is diode connected mode, produces a voltage V with negative temperature coefficient (IPTAT) _eBmP8, the PTAT current delivery that the PMOS Cascode current mirror that MP9 forms produces benchmark core circuit 101 is on resistance R 2, and the PTAT electric current that benchmark core circuit 101 is produced is converted into the PTAT voltage with positive temperature coefficient (PTC), therefore this PTAT voltage and the V with IPTAT characteristic _eBthe single order reference voltage of superimposed generation lower temperature coefficient.Wherein, the grid of MP8 is connected with the grid of described MP2, the source electrode of MP8 is connected with supply voltage, the drain electrode of MP8 is connected with the source electrode of MP9, the grid of MP9 is connected with the grid of MP1, the drain electrode of MP9 is connected with one end of R2, and the other end of R2 is connected with the emitter of Q3, and the base stage of Q3 is connected with collector and is connected to circuit potential minimum GND.

As shown in Figure 3, high-order tc compensation circuit 103 by a PMOS manage, a N metal-oxide-semiconductor and forming with the temperature characterisitic of positive temperature coefficient (PTC) or the current branch of zero-temperature coefficient characteristic.Specifically, high-order tc compensation circuit 103 is made up of PMOS pipe MPC, diode type of attachment NMOS MN6 and a current branch I with uniform temperature coefficient feature (T).Wherein, the grid of MN6 is connected with drain electrode, and the source electrode of MN6 is connected to circuit potential minimum GND, current branch is injected in the MN6 with diode connected mode, the source electrode of MPC is connected to the drain electrode of M N6, and the grid of MPC is connected with the emitter of Q3, and the drain electrode of MPC is connected to the drain electrode of described MP9.This I (T) is the electric current of PTAT electric current or zero-temperature coefficient characteristic, the mode that realizes this current branch I (T) with a PTAT electric current as shown in Figure 4, the PTAT electric current that 2 PMOS pipes (MP10, MP11) can be realized is as this current branch I (T), be that MP10 is connected in cascode mode with MP11, by the positive temperature coefficient (PTC) current mirror generating in described benchmark core circuit in described current branch.Along with the continuous rising of temperature, because PMOS MPC pipe source voltage terminal raises, grid terminal potential declines, thereby the electric current in this PMOS pipe is raise along with the rising of temperature, and this electric current has non-linear PTAT characteristic

As shown in Figure 3, the R2 two ends stack of the voltage that various temperature characterisitics are different in reference voltage output circuit 102 produces reference voltage.The non-linear PTAT electric current being produced by high-order tc compensation circuit 103 is injected in reference voltage output circuit 102, on R2, form a non-linear PTAT voltage, the ultralow temperature coefficient reference voltage of output after this voltage and the stack of single order reference voltage, as voltage-reference.Produce non-linear positive temperature coefficient (PTC) electric current by flexible Application one PMOS pipe, on the resistance of this electric current in reference voltage output circuit 102, be superposed to non-linear positive temperature coefficient (PTC) voltage, and this voltage is along with its nonlinear characteristic grow of increase of temperature, the remaining amount of nonlinearity of single order reference voltage temperature is effectively offset, thereby realized extremely low temperature coefficient.

Start-up circuit 105 in present embodiment adds for benchmark core circuit 101 is normally worked after circuit powers on, various informative owing to starting, and present embodiment is not caused to the impact of essence, does not repeat them here.

It should be noted that, in circuit structure as shown in Figure 3, the substrate of each PMOS pipe both can be connected with own source electrode, can also be connected to supply voltage, and NMOS pipe substrate is connected to circuit minimum level GND.

Take the circuit structure shown in Fig. 3 as example, the technique effect that can reach for present embodiment is below made a concrete analysis of.

The ratio of supposing the emitter junction area of Q1 and Q2 is 1: N, and first compensation phase reference voltage expression formula is:

$V_{\mathrm{ref}0}=V_{\mathrm{EB}3}+\frac{R_2}{R_1}\·V_T\ln N=V_{\mathrm{EB}3}+{\mathrm{mV}}_T\ln N---\left(1\right)$

Wherein, V _t=KT/q is thermal voltage, and K is Boltzmann constant, and T is absolute temperature, and q is electronic charge.M is resistance ratio R ₂/ R ₁.Consider V _bEnon-linear:

$V_{\mathrm{EB}}\left(T\right)=V_{G0}\left(T\right)-(V_{G0}-V_{\mathrm{EB}0})\frac{T}{T_0}-V_T(\mathrm{\γ}-\mathrm{\α})\ln \frac{T}{T_0}---\left(2\right)$

V in formula 2 _g0for the band gap voltage of silicon materials under 0K, representative value is 1.205V, normal temperature T ₀=300K, γ, α are respectively the coefficient relevant with collector current index temperature coefficient to triode base hole mobility.Therefore single order reference voltage can be expressed as:

$V_{\mathrm{ref}}^{\′}=V_{G0}-(V_{G0}-V_{\mathrm{EB}3})\frac{T}{T_0}+{\mathrm{mV}}_T\ln N-(\mathrm{\γ}-\mathrm{\α})V_T\ln \frac{T}{T_0}---\left(3\right)$

Therefore single order reference voltage has and has stronger non-linear negative temperature characteristic in middle high-temperature region.

Consider the electric current in MPC:

$I_{\mathrm{MPC}}=\frac{1}{2}{\mathrm{\β}}_{\mathrm{MPC}}{(\sqrt{\frac{{2I}_{\mathrm{PTAT}}}{{\mathrm{\β}}_{\mathrm{MN}6}}}+V_{\mathrm{THN}}-V_{\mathrm{EB}3}-V_{\mathrm{THP}})}^2\≈\frac{1}{2}{\mathrm{\β}}_{\mathrm{MPC}}{(\sqrt{\frac{{2I}_{\mathrm{PTAT}}}{{\mathrm{\β}}_{\mathrm{MN}6}}}-V_{\mathrm{EB}3})}^2---\left(4\right)$

Wherein, β _mPCand β _mN6represent respectively gain factor (β=μ C of PMOS pipe MPC and NMOS pipe MN6 _oxw/L), V _tHN, V _tHPbe respectively the threshold voltage of NMOS pipe and PMOS pipe.Due to I _refthere is the PTAT of presenting characteristic, V _eB3there is non-linear negative temperature characteristic, therefore I _mPCthere is non-linear PTAT characteristic.

Bring V into _eBtemperature characterisitic is further analyzed.Utilize (1+x) ^α≈ 1+ α x+O (x ²) obtain:

$I_{\mathrm{MPC}}=I_{\mathrm{mpc}0}+\sqrt{{2I}_{\mathrm{mpc}0}{\mathrm{\β}}_{\mathrm{MPC}}\mathrm{\κ}}{V}_T(\mathrm{\γ}-\mathrm{\α})\ln \frac{T}{T_0}---\left(5\right)$

Wherein I _mpc0pTAT linear current during for T=T0 in PMOS pipe MPC, κ is current delivery coefficient.In above formula, Section 2 is non-linear PTAT electric current, and this electric current is injected into the voltage that is converted into non-linear PTAT on the electric current stack resistance of reference voltage output circuit:

$V_{\mathrm{NL}}=R_3\·\sqrt{2I_{\mathrm{MPC}0}{\mathrm{\β}}_{\mathrm{MPC}}\mathrm{\κ}}(\mathrm{\γ}-\mathrm{\α})V_T\ln \frac{T}{T_0}---\left(6\right)$

This voltage output node with the V ' of non-linear negative temperature coefficient _refbe added, thereby greatly decayed the non-linear IPTAT voltage of single order reference voltage as shown in (3) formula, therefore obtain the reference voltage that temperature coefficient is very low.As shown in Figure 5, the effect temperature compensation reaching as shown in Figure 6 for the non-linear PTAT electric current of the high-order tc compensation circuit evolving in present embodiment.

Simulation result shows, after high-order compensation, the temperature coefficient of voltage-reference is reduced to 0.3ppm/ ℃, by optimizing temperature coefficient and stability thereof, temperature coefficient is at 3.4ppm/ ℃, and along with metal-oxide-semiconductor process corner changes, voltage-reference deviation maximal value is no more than 7.6ppm/ ℃.

It should be noted that, present embodiment is a kind of concrete implementation, and in actual applications, each circuit can also be other implementation structure.Such as the triode comprising in each circuit can replace with the metal-oxide-semiconductor of working group subthreshold region, realizes with full metal-oxide-semiconductor.

Third embodiment of the invention relates to a kind of method for generating voltage reference source, and idiographic flow as shown in Figure 7.

In step 701, generate positive temperature coefficient (PTC) electric current and negative temperature coefficient voltage.Specifically, it is poor to utilize the base-emitter voltage difference of two triodes or be operated in the gate source voltage of subthreshold region metal-oxide-semiconductor, generates linear positive temperature coefficient (PTC) electric current; Utilize the base-emitter of a triode, generate negative temperature coefficient voltage, or utilize and be operated in subthreshold region metal-oxide-semiconductor gate source voltage, generate nonlinear negative temperature parameter current.

In step 702, be positive temperature coefficient (PTC) voltage by the positive temperature coefficient (PTC) current conversion of generation, and the positive temperature coefficient (PTC) voltage after the negative temperature coefficient voltage of generation and conversion is superposeed, obtain single order reference voltage.

In step 703, generate that size of current varies with temperature and the non-linear positive temperature coefficient (PTC) electric current that changes.Such as, can utilize PMOS pipe to generate that size of current varies with temperature and the non-linear positive temperature coefficient (PTC) electric current that changes.While being operated in saturation region due to metal-oxide-semiconductor, its electric current and gate source voltage have square law relationship, therefore, can utilize this characteristic to realize a kind of non-linear positive temperature coefficient (PTC) electric current.

In step 704, be non-linear positive temperature coefficient (PTC) voltage by the non-linear positive temperature coefficient (PTC) current conversion generating, and non-linear positive temperature coefficient (PTC) voltage and the single order reference voltage of conversion are superposeed, obtain voltage-reference.

Be not difficult to find, present embodiment is the method embodiment corresponding with the first embodiment, present embodiment can with the enforcement of working in coordination of the first embodiment.The correlation technique details of mentioning in the first embodiment is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in present embodiment also can be applicable in the first embodiment.

Present embodiment all can realize in modes such as software, hardware, firmwares.No matter the present invention realizes with software, hardware or firmware mode, instruction code can be stored in the storer of computer-accessible of any type (for example permanent or revisable, volatibility or non-volatile, solid-state or non-solid-state, fixing or removable medium etc.).Equally, storer can be for example programmable logic array (Programmable Array Logic, be called for short " PAL "), random access memory (Random Access Memory, be called for short " RAM "), programmable read only memory (Programmable Read Only Memory, be called for short " PROM "), ROM (read-only memory) (Read-Only Memory, be called for short " ROM "), Electrically Erasable Read Only Memory (Electrically Erasable Programmable ROM, be called for short " EEPROM "), disk, CD, digital versatile disc (Digital Versatile Disc, be called for short " DVD ") etc.

Due in embodiments of the present invention, by nonlinear adaptive PTAT voltage, the non-linear negative temperature coefficient in single order reference voltage is offset, thereby make voltage-reference there is lower temperature coefficient.And, be simple in structurely easy to integratedly, compensation branch road stability is better, and less to the initial Accuracy of voltage-reference.In addition, in the time that voltage reference source circuit also comprises feedback biasing loop, because this feedback biasing loop can provide stable DC point, therefore can guarantee the steady operation of circuit.

Although pass through with reference to some of the preferred embodiment of the invention, the present invention is illustrated and described, but those of ordinary skill in the art should be understood that and can do various changes to it in the form and details, and without departing from the spirit and scope of the present invention.

Claims (8)

1. a voltage reference source circuit, is characterized in that, comprises:

Benchmark core circuit, for generating positive temperature coefficient (PTC) electric current;

High-order tc compensation circuit, for generating that size of current varies with temperature and the non-linear positive temperature coefficient (PTC) electric current that changes;

Reference voltage output circuit, be positive temperature coefficient (PTC) voltage for the positive temperature coefficient (PTC) current conversion that described benchmark core circuit is generated, and a negative temperature coefficient voltage and described positive temperature coefficient (PTC) voltage that this reference voltage output circuit is generated superpose, obtain single order reference voltage, be non-linear positive temperature coefficient (PTC) voltage by the non-linear positive temperature coefficient (PTC) current conversion of described high-order tc compensation circuit evolving, and described non-linear positive temperature coefficient (PTC) voltage and the described single order reference voltage of conversion are superposeed, obtain voltage-reference;

Described benchmark core circuit is made up of 2 triode Q1, Q2,1 resistance R 1,2 NMOS pipes MN3, MN4,4 PMOS pipe MP4, MP5, MP6, MP7; Wherein, Q1 is 1:N with the ratio of the area of the emitter junction of Q2, and 2 NMOS pipes form current-mirror structure, and 4 PMOS pipes form cascade Cascode current mirror;

Wherein, MP4 and MP6 source electrode are all connected to supply voltage, the drain electrode of MP4 is connected to the source electrode of MP5, the drain electrode of MP6 is connected to the source electrode of MP7, the drain electrode of MP5 is connected to the drain electrode of MN3, the drain electrode of MP7 is connected to the drain electrode of MN4, the grid of MN3 and MN4 is connected, the source electrode of MN3 is connected with the emitter of Q1, the grid of MN4 is connected with drain electrode, and source electrode is connected with one end of R1, and an other end of this R1 is connected to the emitter of Q2, the base stage of Q1 is connected with collector and is connected to circuit potential minimum GND, and the base stage of Q2 is connected with collector and is connected to circuit potential minimum GND;

Described voltage reference source circuit also comprises feedback biasing loop, is used to described benchmark core circuit that bias voltage and electric current are provided;

Described feedback biasing loop is made up of 2 triode Q4, Q5,2 NMOS pipe MN1 and MN2,3 PMOS pipe MP1, MP2, MP3, described feedback biasing loop and described benchmark core circuit formation feedback control loop;

Wherein, the base stage of Q4 is connected with collector and is connected to circuit potential minimum GND, the base stage of Q5 is connected with collector and is connected to circuit potential minimum GND, the grid of MN1 is connected to the grid of described MN4, the source electrode of MN1 is connected with the emitter of Q5, the drain electrode of MN1 is connected to grid and the drain electrode of MP1, the grid of MN2 is connected with the drain electrode of described MN3, the source electrode of MN2 is connected with Q4 emitter, the drain electrode of MN2 is connected with the drain terminal of MP3, the grid of MP1 is connected with drain electrode, and the grid of MP1 is connected to the grid of described MP5 and described MP7, the source electrode of MP1 is connected with supply voltage, MP2 drain and gate is connected with drain electrode with the source electrode of MP3 respectively, and the grid of MP2 is connected to the grid of described MP4 and described MP6, the source electrode of MP2 is connected to supply voltage, the grid of MP3 is connected with the grid of MP1.

2. voltage reference source circuit according to claim 1, is characterized in that, described benchmark core circuit utilizes the base-emitter voltage difference of 2 triodes, generates described positive temperature coefficient (PTC) electric current.

3. voltage reference source circuit according to claim 1, is characterized in that, described reference voltage output circuit is utilized the base-emitter of 1 triode, generates described negative temperature coefficient voltage.

4. voltage reference source circuit according to claim 3, is characterized in that, described reference voltage output circuit is made up of 1 triode Q3,1 resistance R 2,2 PMOS pipes MP8, MP9;

Wherein, triode is that diode B-C knot short circuit is diode connected mode, for generating described negative temperature coefficient voltage; 2 PMOS pipes form Cascode current mirror, for the resistance to described reference voltage output circuit by the positive temperature coefficient (PTC) current delivery of described benchmark core circuit generation;

Wherein, the grid of MP8 is connected with the grid of described MP2, the source electrode of MP8 is connected with supply voltage, the drain electrode of MP8 is connected with the source electrode of MP9, the grid of MP9 is connected with the grid of described MP1, the drain electrode of MP9 is connected with one end of R2, and the other end of R2 is connected with the emitter of Q3, and the base stage of Q3 is connected with collector and is connected to circuit potential minimum GND.

5. voltage reference source circuit according to claim 4, is characterized in that, described high-order tc compensation circuit utilizes 1 PMOS pipe to generate described non-linear positive temperature coefficient (PTC) electric current.

6. voltage reference source circuit according to claim 5, it is characterized in that, described high-order tc compensation circuit is managed MN6 and is formed with the temperature characterisitic of positive temperature coefficient (PTC) or the current branch of zero-temperature coefficient characteristic by 1 PMOS pipe MPC, 1 NMOS;

Wherein, the grid of MN6 is connected with drain electrode, and the source electrode of MN6 is connected to circuit potential minimum GND, current branch is injected in the MN6 with diode connected mode, the source electrode of MPC is connected to the drain electrode of MN6, and the grid of MPC is connected with the emitter of described Q3, and the drain electrode of MPC is connected to the drain electrode of described MP9.

7. voltage reference source circuit according to claim 6, is characterized in that, the positive temperature coefficient (PTC) electric current in described current branch generates by 2 PMOS pipe MP10 and MP11;

Wherein, MP10 and MP11 by the positive temperature coefficient (PTC) current mirror generating in described benchmark core circuit in described current branch;

Wherein, the grid of MP10 is connected with the grid of described MP2, and the source electrode of MP10 is connected with supply voltage, and the drain electrode of MP10 is connected with the source electrode of MP11, and the grid of MP11 is connected with the grid of described MP1.

8. according to the voltage reference source circuit described in any one in claim 1 to 7, it is characterized in that, described voltage reference source circuit also comprises start-up circuit, for starting described benchmark core circuit.

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