CN210270647U - Reference current source circuit and chip based on temperature compensation - Google Patents
Reference current source circuit and chip based on temperature compensation Download PDFInfo
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- CN210270647U CN210270647U CN201921731594.8U CN201921731594U CN210270647U CN 210270647 U CN210270647 U CN 210270647U CN 201921731594 U CN201921731594 U CN 201921731594U CN 210270647 U CN210270647 U CN 210270647U
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Abstract
The utility model provides a benchmark current source circuit and chip based on temperature compensation, include: the device comprises a temperature compensation module, a current mirror module, a starting module and an output module; the starting module is used for starting the current mirror module; the temperature compensation module is used for adjusting the temperature coefficient of the reference current to provide temperature compensation; the current mirror module is used for generating reference current and mirroring the adjusted reference current to the output module; the output module is used for outputting reference current; the temperature compensation module comprises a sliding rheostat and two N-type MOS tubes which are sequentially connected, and the temperature compensation module enables the grid-source voltage difference of the two N-type MOS tubes not to be zero by adjusting the resistance value of the sliding rheostat and the channel width-length ratio of the two N-type MOS tubes so as to adjust the temperature coefficient of the reference current. The utility model discloses under the equal emulation condition, have the compensation effect better to temperature coefficient voltage, reduce the consumption of whole circuit.
Description
Technical Field
The utility model relates to an integrated circuit design field indicates a reference current source circuit and chip based on temperature compensation especially.
Background
The current source is an indispensable module in the analog integrated circuit, and its value is usually obtained by dividing a voltage by a resistor, which often has a large temperature coefficient, while some reference current source circuits dedicated to temperature processing have a complicated structure and a large area.
The reference current source circuit is widely applied to various analog circuits, however, the value of the current source changes with the temperature change, the existing current temperature compensation technology is relatively complex, and has more design variables, and the existing reference current source circuit can strongly influence the temperature coefficient of the current when the output current value is calibrated.
In order to minimize the variation of the generated current source with temperature, it is necessary to provide a reference current source circuit having a simple structure and temperature compensation.
Disclosure of Invention
The utility model aims at providing a benchmark current source circuit and chip based on temperature compensation realizes having the compensation effect better to temperature coefficient voltage under the equal emulation condition, reduces the consumption of whole circuit.
The utility model provides a technical scheme as follows:
the utility model provides a benchmark current source circuit based on temperature compensation, include:
the device comprises a temperature compensation module, a current mirror module, a starting module and an output module;
the starting module is used for starting the current mirror module;
the temperature compensation module is used for adjusting the temperature coefficient of the reference current to provide temperature compensation;
the current mirror module is used for generating reference current and mirroring the adjusted reference current to the output module;
the output module is used for outputting the reference current;
the temperature compensation module comprises a sliding rheostat and two N-type MOS tubes which are sequentially connected, and the temperature compensation module enables the grid-source voltage difference of the two N-type MOS tubes not to be zero by adjusting the resistance value of the sliding rheostat and the channel width-length ratio of the two N-type MOS tubes so as to adjust the temperature coefficient of the reference current.
Furthermore, the current mirror module comprises a first P-type MOS tube and a second P-type MOS tube, the output module comprises a third P-type MOS tube, and the physical sizes of the first P-type MOS tube, the second P-type MOS tube and the third P-type MOS tube are the same;
the source electrodes of the first P-type MOS tube, the second P-type MOS tube and the third P-type MOS tube are connected with a power supply voltage, and the first P-type MOS tube, the second P-type MOS tube and the third P-type MOS tube share a grid electrode;
the drain electrodes of the first P-type MOS tube and the second P-type MOS tube are respectively connected with the starting module and the temperature compensation module;
and the drain electrode of the third P-type MOS tube outputs the reference current.
Further, the starting module comprises a first N-type MOS tube;
the grid electrode of the first N-type MOS tube is in short circuit with the drain electrode of the first N-type MOS tube;
the drain electrode of the first N-type MOS tube is respectively connected with the grid electrode and the drain electrode of the first P-type MOS tube;
the source electrode of the first N-type MOS tube is connected with the drain electrode of the second P-type MOS tube;
and the drain electrode and the source electrode of the first N-type MOS tube are respectively connected with the temperature compensation module.
Further, the temperature compensation module comprises a biasing unit, the sliding rheostat and two N-type MOS tubes which are connected in sequence;
the drain electrode of the second N-type MOS tube is respectively connected with the drain electrode of the second P-type MOS tube and the source electrode of the first N-type MOS tube;
the drain electrode of the third N-type MOS tube is respectively connected with the drain electrode of the first P-type MOS tube and the drain electrode of the first N-type MOS tube;
the second N-type MOS tube and the third N-type MOS tube share a grid electrode, and the grid electrode of the second N-type MOS tube is connected with the source electrode of the first N-type MOS tube;
the source electrode of the second N-type MOS tube is connected with the biasing unit, the source electrode of the third N-type MOS tube is connected with the first end of the sliding rheostat, and the second end of the sliding rheostat is connected with the biasing unit;
the channel width-length ratio of the second N-type MOS tube is a first preset multiple of the channel width-length ratio of the third N-type MOS tube, and the first preset multiple is a positive integer.
Further, the bias unit comprises two P-type triodes which are connected in sequence;
the emitting electrode of the first P-type triode is connected with the source electrode of the second N-type MOS tube;
the emitter of the second P-type triode is connected with the second end of the sliding rheostat;
the first P-type triode and the second P-type triode share a base electrode and are connected with the common ground, the collector electrodes of the first P-type triode and the second P-type triode are respectively grounded, the effective area of the emitting area of the second P-type triode is a second preset multiple of the effective area of the emitting area of the first P-type triode, and the second preset multiple is a positive integer.
The utility model also provides a chip, the integration has the reference current source circuit based on temperature compensation, the reference current source circuit based on temperature compensation includes:
the device comprises a temperature compensation module, a current mirror module, a starting module and an output module;
the starting module is used for starting the current mirror module;
the temperature compensation module is used for adjusting the temperature coefficient of the reference current to provide temperature compensation;
the current mirror module is used for generating reference current and mirroring the adjusted reference current to the output module;
the output module is used for outputting the reference current;
the temperature compensation module comprises a sliding rheostat and two N-type MOS tubes which are sequentially connected, and the temperature compensation module enables the grid-source voltage difference of the two N-type MOS tubes not to be zero by adjusting the resistance value of the sliding rheostat and the channel width-length ratio of the two N-type MOS tubes so as to adjust the temperature coefficient of the reference current.
Furthermore, the current mirror module comprises a first P-type MOS tube and a second P-type MOS tube, the output module comprises a third P-type MOS tube, and the physical sizes of the first P-type MOS tube, the second P-type MOS tube and the third P-type MOS tube are the same;
the source electrodes of the first P-type MOS tube, the second P-type MOS tube and the third P-type MOS tube are connected with a power supply voltage, and the first P-type MOS tube, the second P-type MOS tube and the third P-type MOS tube share a grid electrode;
the drain electrodes of the first P-type MOS tube and the second P-type MOS tube are respectively connected with the starting module and the temperature compensation module;
and the drain electrode of the third P-type MOS tube outputs the reference current.
Further, the starting module comprises a first N-type MOS tube;
the grid electrode of the first N-type MOS tube is in short circuit with the drain electrode of the first N-type MOS tube;
the drain electrode of the first N-type MOS tube is respectively connected with the grid electrode and the drain electrode of the first P-type MOS tube;
the source electrode of the first N-type MOS tube is connected with the drain electrode of the second P-type MOS tube;
and the drain electrode and the source electrode of the first N-type MOS tube are respectively connected with the temperature compensation module.
Further, the temperature compensation module comprises a biasing unit, the sliding rheostat and two N-type MOS tubes which are connected in sequence;
the drain electrode of the second N-type MOS tube is respectively connected with the drain electrode of the second P-type MOS tube and the source electrode of the first N-type MOS tube;
the drain electrode of the third N-type MOS tube is respectively connected with the drain electrode of the first P-type MOS tube and the drain electrode of the first N-type MOS tube;
the second N-type MOS tube and the third N-type MOS tube share a grid electrode, and the grid electrode of the second N-type MOS tube is connected with the source electrode of the first N-type MOS tube;
the source electrode of the second N-type MOS tube is connected with the biasing unit, the source electrode of the third N-type MOS tube is connected with the first end of the sliding rheostat, and the second end of the sliding rheostat is connected with the biasing unit;
the channel width-length ratio of the second N-type MOS tube is a first preset multiple of the channel width-length ratio of the third N-type MOS tube, and the first preset multiple is a positive integer.
Further, the bias unit comprises two P-type triodes which are connected in sequence;
the emitting electrode of the first P-type triode is connected with the source electrode of the second N-type MOS tube;
the emitter of the second P-type triode is connected with the second end of the sliding rheostat;
the first P-type triode and the second P-type triode share a base electrode and are connected with the common ground, the collector electrodes of the first P-type triode and the second P-type triode are respectively grounded, the effective area of the emitting area of the second P-type triode is a second preset multiple of the effective area of the emitting area of the first P-type triode, and the second preset multiple is a positive integer.
Through the utility model provides a pair of benchmark current source circuit and chip based on temperature compensation can have the compensation effect better to temperature coefficient voltage under the equal simulation condition, reduces the consumption of whole circuit.
Drawings
The above features, technical features, advantages and implementations of a reference current source circuit and a chip based on temperature compensation will be further described in a clearly understandable manner with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of an embodiment of a reference current source circuit based on temperature compensation according to the present invention;
fig. 2 is a schematic structural diagram of another embodiment of the reference current source circuit based on temperature compensation according to the present invention.
Detailed Description
In order to more clearly illustrate embodiments of the present invention or technical solutions in the prior art, specific embodiments of the present invention will be described below with reference to the accompanying drawings. It is obvious that the drawings in the following description are only examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be obtained from these drawings without inventive effort.
For the sake of simplicity, only the parts relevant to the present invention are schematically shown in the drawings, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".
An embodiment of the present invention, as shown in fig. 1, is a reference current source circuit based on temperature compensation, including:
a temperature compensation module 110, a current mirror module 120, a start-up module 130, and an output module 140;
the starting module 130 is used for starting the current mirror module 120;
the temperature compensation module 110 is used for adjusting a temperature coefficient of the reference current (Iref) to provide temperature compensation;
the current mirror module 120 is configured to generate a reference current (Iref) and mirror the adjusted reference current (Iref) to the output module 140;
the output module 140 is configured to output a reference current (Iref);
the temperature compensation module 110 includes a sliding rheostat (R1) and two N-type MOS transistors connected in sequence, and the temperature compensation module 110 adjusts the temperature coefficient of the reference current (Iref) by adjusting the resistance of the sliding rheostat (R1) and the channel width-to-length ratio of the two N-type MOS transistors so that the gate-source voltage difference of the two N-type MOS transistors is not zero.
The utility model discloses an embodiment, a chip, the integration has the reference current source circuit based on temperature compensation, and the reference current source circuit based on temperature compensation includes:
a temperature compensation module 110, a current mirror module 120, a start-up module 130, and an output module 140;
the starting module 130 is used for starting the current mirror module 120;
the temperature compensation module 110 is used for adjusting a temperature coefficient of the reference current (Iref) to provide temperature compensation;
the current mirror module 120 is configured to generate a reference current (Iref) and mirror the adjusted reference current (Iref) to the output module 140;
the output module 140 is configured to output a reference current (Iref);
the temperature compensation module 110 includes a sliding rheostat (R1) and two N-type MOS transistors connected in sequence, and the temperature compensation module 110 adjusts the temperature coefficient of the reference current (Iref) by adjusting the resistance of the sliding rheostat (R1) and the channel width-to-length ratio of the two N-type MOS transistors so that the gate-source voltage difference of the two N-type MOS transistors is not zero.
Based on the foregoing embodiments, as shown in fig. 1 and fig. 2, the current mirror module 120 includes a first P-type MOS transistor (MP1) and a second P-type MOS transistor (MP0), the output module 140 includes a third P-type MOS transistor (MP2), and the physical sizes of the first P-type MOS transistor (MP1), the second P-type MOS transistor (MP0), and the third P-type MOS transistor (MP2) are the same;
the source electrodes (S) of the first P-type MOS tube (MP1), the second P-type MOS tube (MP0) and the third P-type MOS tube (MP2) are connected with a power supply voltage VDD, and the first P-type MOS tube (MP1), the second P-type MOS tube (MP0) and the third P-type MOS tube (MP2) share a grid electrode (G);
the drains (D) of the first P-type MOS transistor (MP1) and the second P-type MOS transistor (MP0) are respectively connected to the start module 130 and the temperature compensation module 110;
the drain electrode (D) of the third P-type MOS tube (MP2) outputs the reference current (Iref).
Based on the foregoing embodiment, the starting module 130 includes a first N-type MOS transistor (MNS);
the grid (G) of the first N-type MOS tube (MNS) is in short circuit with the drain (D) of the first N-type MOS tube (MNS);
the drain (D) of the first N-type MOS tube (MNS) is respectively connected with the grid (G) and the drain (D) of the first P-type MOS tube (MP 1);
the source electrode (S) of the first N-type MOS tube (MNS) is connected with the drain electrode (D) of the second P-type MOS tube (MP 0);
the drain (D) and the source (S) of the first N-type MOS transistor (MNS) are respectively connected to the temperature compensation module 110.
Based on the foregoing embodiment, the temperature compensation module 110 includes a bias unit, a sliding rheostat (R1) and two N-type MOS transistors connected in sequence;
the drain (D) of the second N-type MOS tube (MN0) is respectively connected with the drain (D) of the second P-type MOS tube (MP0) and the source (S) of the first N-type MOS tube (MNS);
the drain (D) of the third N-type MOS tube (MN1) is respectively connected with the drain (D) of the first P-type MOS tube (MP1) and the drain (D) of the first N-type MOS tube (MNS);
the second N-type MOS transistor (MN0) and the third N-type MOS transistor (MN1) share a grid (G), and the grid (G) of the second N-type MOS transistor (MN0) is connected with the source (S) of the first N-type MOS transistor (MNS);
the source electrode (S) of the second N-type MOS tube (MN0) is connected with the bias unit, the source electrode (S) of the third N-type MOS tube (MN1) is connected with the first end of the slide rheostat (R1), and the second end of the slide rheostat (R1) is connected with the bias unit;
the channel width-to-length ratio of the second N-type MOS transistor (MN0) is a first preset multiple of the channel width-to-length ratio of the third N-type MOS transistor (MN1), and the first preset multiple is a positive integer.
Based on the previous embodiment, the bias unit comprises two P-type triodes which are connected in sequence;
an emitter (E) of the first P-type triode (Q0) is connected with a source (S) of the second N-type MOS tube (MN 0);
the emitter (E) of the second P-type triode (Q1) is connected with the second end of the slide rheostat (R1);
the first P-type triode (Q0) and the second P-type triode (Q1) share a base (B) and are connected with the common ground, the collector electrodes (C) of the first P-type triode (Q0) and the second P-type triode (Q1) are respectively grounded, the effective area of the emitting area of the second P-type triode (Q1) is a second preset multiple of the effective area of the emitting area of the first P-type triode (Q0), and the second preset multiple is a positive integer.
Specifically, the first P-type MOS transistor (MP1), the second P-type MOS transistor (MP0), and the third P-type MOS transistor (MP2) are PMOS transistors, and constitute a current mirror circuit, and their physical sizes are the same, so that the currents flowing through the second P-type MOS transistor (MP0) and the third P-type MOS transistor (MP2) are equal, and the currents flowing through the second N-type MOS transistor (MN0) and the third N-type MOS transistor (MN1) are equal. Here, the first N-type MOS transistor (MNS) is used as a start-up circuit, and the third P-type MOS transistor (MP2) is used as an output to provide the reference current (Iref).
The width-to-length ratio (W/L) of the second N-type MOS transistor (MN0) is M times (i.e. the first preset multiple of the present invention) of the width-to-length ratio (W/L) of the third N-type MOS transistor (MN1), which makes the gate-source voltage difference (Vgs0-Vgs1) between the second N-type MOS transistor (MN0) and the third N-type MOS transistor (MN1) not zero, so that the following formula is provided:
Vgs0+Vbe0＝Vgs1+Vbe1+Iref×R1(1)
wherein, Vgs0Is the gate-source voltage, V, of the second N-type MOS transistor (MN0)be0Is the voltage of the emitter (E) and base (B) of the first P-type triode (Q0), Vgs1Is the gate-source voltage, V, of the third N-type MOS transistor (MN1)be1Is the voltage of the emitter (E) and the base (B) of a second P-type triode (Q1)refIs the reference current (Iref), and R1 is the resistance of the sliding varistor (R1).
The equation (1) above can be converted equally to the equation shown below:
from the above equation (2), it can be obtained that the magnitude of the reference current (Iref) output by the third P-type MOS transistor (MP2) does not depend on the voltage value of the power supply voltage VDDVDD.
Due to the fact that(Vgs0-Vgs1) And (V)be0-Vbe1) Are all first order PTAT voltages, R1The PTAT resistor, and the reference current (Iref) when the temperature coefficient is zero can be obtained by using the relationship between them as follows:
wherein, αVIs the voltage temperature coefficient, αRIs the temperature coefficient of resistance, T0Is the reference temperature, T is the actual temperature, R0Is a reference value of the sliding rheostat (R1).
When αV＝αRWhen, Iref＝V0÷R0A zero temperature coefficient is obtained.
While
Where k is boltzmann's constant and N is the ratio of the effective area of the emitter region between the second P-type transistor (Q1) and the first P-type transistor (Q0), i.e., N ═ WQ1÷WQ0Wherein W isQ1Is the effective area of the emitting region of the second P-type triode (Q1), WQ1Is the active area of the emitter region of the first P-type transistor (Q0).
Since the currents flowing through the second N-type MOS transistor (MN0) and the third N-type MOS transistor (MN1) are equal, the following formula is obtained:
wherein, is Δ VthIs the gate-source voltage difference between the second N-type MOS transistor (MN0) and the third N-type MOS transistor (MN1) (. mu.)n0Is at a reference temperature (T)0300K) mobility of electrons, αμIs a constant, Δ V, that can be approximated as 1.5thIs the difference of the threshold voltages generated by the second N-type MOS transistor (MN0) and the third N-type MOS transistor (MN1) due to the body effect.
ΔVthCan be expressed as follows:
where γ is the lining bias coefficient, φSIs the surface potential, NaIs the substrate doping concentration, niIs the intrinsic carrier concentration of silicon, Vs0Source (S) voltage, V, of second N-type MOS transistor (MN0)s1The source (S) voltage of the third N-type MOS transistor (MN1) and q is an electron charge.
Two markers were introduced as follows:
wherein, Cox is a gate oxide layer capacitance of a unit area, W is a gate width of the MOS transistor, L is an effective gate length of the MOS transistor, and M is a ratio of a width-length ratio of the second N-type MOS transistor (MN0) to a width-length ratio of the third N-type MOS transistor (MN1), that is, M is YMN0÷YMN1Wherein Y isMN0Is the width-to-length ratio, Y, of the second N-type MOS transistor (MN0)MN1Is the width-to-length ratio of the third N-type MOS transistor (MN 1).
Therefore, according to Δ VgsCan be expressed as follows:
thus, when T is equal to T0Only the first two terms of the Taylor expansion are considered in time, due to Δ Vth0/ΔVgs≤1，Φs0Is T0The surface potential at the moment, therefore Δ Vgs, can be reduced as follows:
thus, the reference current IrefCan be expressed as follows:
wherein the content of the first and second substances,
from the condition of zero temperature coefficient (dIref/dT is 0), Δ Vbe0And Δ Vgs0The following relationship should be satisfied:
due to DeltaVbe0The voltage is determined by the ratio N of the PNP transistors Q1 and Q0, thus Δ Vbe0Is independent of process variations and Δ Vgs0The voltage is determined by the electron mobility, thus Δ Vgs0Is related to the process corner.
In summary, the present embodiment can determine Δ V from the following equation and the reference current (Iref) Irefgs0And the numerical value of the ratio M of the width-to-length ratio of the second N-type MOS transistor (MN0) to the width-to-length ratio of the third N-type MOS transistor (MN 1):
wherein, gmIs transconductance, i.e. the partial derivative of the drain current of the MOS transistor to the gate-source voltage.
The numerical value of the ratio N of the effective areas of the emitting areas of the second P-type transistor (Q1) and the first P-type transistor (Q0) is determined by the following formula:
iteratively optimizing the channel width-length ratio W/L of the MOS tube grid, the values of a first preset multiple M and a second preset multiple N, wherein M and N are integers which are not zero, so that the following formula is satisfied:
the resistance value R1 of the slide rheostat (R1) can be calculated and determined by the above equation (9) and the following equation (15):
iref is the ratio of PTAT voltage to PTAT resistance, α is selected when designing the circuitV＝αRA current Iref of zero temperature coefficient can be obtained. According to the reference current source circuit based on temperature compensation, the relation between the PTAT (proportional to absolute temperature) voltage and the PTAT resistor is utilized to obtain the current which is independent of the temperature. The circuit has the advantages of simple structure, less design variables, simple design process, low temperature coefficient, small deviation along with process variation, capability of calibrating output current and less influence on the temperature coefficient. The current reference which does not change along with the process power supply voltage VDD and the temperature is realized by a simple circuit, the design parameters are few, and the design process is simple. The technical scheme of the invention utilizes the positive temperature characteristic of the linear region resistance of the third field effect transistor and the negative temperature characteristic of the mobility of the first field effect transistor and the second field effect transistor to be superposed and compensated by preset proportion weight, so that the invention can use a simple circuit to realize the temperature compensation of current reference, and simultaneously, the invention sets the channel width-length ratio of the second N-type MOS transistor (MN0) to be the first preset multiple M of the channel width-length ratio of the third N-type MOS transistor (MN1) to adjust the temperature coefficient of reference current (Iref). In addition, due to the adjustment of the resistance value of the sliding rheostat (R1), the proper reference source current can be obtained, and the temperature compensation of the current is realized.
As can be seen from the above formula and fig. 2, for the purpose of temperature compensation, it is necessary to design that the channel width-to-length ratio of the second N-type MOS transistor (MN0) is greater than the channel width-to-length ratio of the third N-type MOS transistor (MN1), and the ratio of the channel width-to-length ratio of the second N-type MOS transistor (MN0) divided by the channel width-to-length ratio of the third N-type MOS transistor (MN1) is a first predetermined multiple. The effective area of the emission area of the second P-type triode (Q1) is larger than that of the emission area of the first P-type triode (Q0), and the ratio of the effective area of the emission area of the second P-type triode (Q1) divided by the effective area of the emission area of the first P-type triode (Q0) is a second preset multiple, so that the circuit designed by the invention greatly enhances the compensation capability of positive and negative temperature coefficient voltage.
The circuit of the invention has the advantages that under the same simulation condition, namely the simulation process, the process angle, the power supply voltage VDD and the simulation temperature range are the same, the P-type MOS tubes are under the same physical size, namely the first P-type MOS tube (MP1), the second P-type MOS tube (MP0) and the third P-type MOS tube (MP2) have the same width-to-length ratio, so that the channel width-to-length ratio of the second N-type MOS tube (MN0) is the first preset multiple of the channel width-to-length ratio of the third N-type MOS tube (MN1), the effective area of the emitting area of the second P-type triode (Q1) is the second preset multiple of the effective area of the emitting area of the first P-type triode (Q0), the specific first preset multiple, the second preset multiple and the resistance value of the sliding rheostat (R1) can be calculated according to the formula, the circuit has the double positive temperature coefficient superposition effect, under the condition that the power consumption is not increased, the circuit has the better compensation effect on the negative temperature coefficient voltage, the circuit has excellent performance indexes, reduces the power consumption of the whole circuit to a certain extent by applying the circuit, and can be applied to chips with ultra-low power consumption.
It should be noted that the above embodiments can be freely combined as necessary. The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A reference current source circuit based on temperature compensation, comprising:
the device comprises a temperature compensation module, a current mirror module, a starting module and an output module;
the starting module is used for starting the current mirror module;
the temperature compensation module is used for adjusting the temperature coefficient of the reference current to provide temperature compensation;
the current mirror module is used for generating reference current and mirroring the adjusted reference current to the output module;
the output module is used for outputting the reference current;
the temperature compensation module comprises a sliding rheostat and two N-type MOS tubes which are sequentially connected, and the temperature compensation module enables the grid-source voltage difference of the two N-type MOS tubes not to be zero by adjusting the resistance value of the sliding rheostat and the channel width-length ratio of the two N-type MOS tubes so as to adjust the temperature coefficient of the reference current.
2. The temperature compensation based reference current source circuit of claim 1, wherein:
the current mirror module comprises a first P-type MOS tube and a second P-type MOS tube, the output module comprises a third P-type MOS tube, and the physical sizes of the first P-type MOS tube, the second P-type MOS tube and the third P-type MOS tube are the same;
the source electrodes of the first P-type MOS tube, the second P-type MOS tube and the third P-type MOS tube are connected with a power supply voltage, and the first P-type MOS tube, the second P-type MOS tube and the third P-type MOS tube share a grid electrode;
the drain electrodes of the first P-type MOS tube and the second P-type MOS tube are respectively connected with the starting module and the temperature compensation module;
and the drain electrode of the third P-type MOS tube outputs the reference current.
3. The temperature compensation based reference current source circuit of claim 2, wherein:
the starting module comprises a first N-type MOS tube;
the grid electrode of the first N-type MOS tube is in short circuit with the drain electrode of the first N-type MOS tube;
the drain electrode of the first N-type MOS tube is respectively connected with the grid electrode and the drain electrode of the first P-type MOS tube;
the source electrode of the first N-type MOS tube is connected with the drain electrode of the second P-type MOS tube;
and the drain electrode and the source electrode of the first N-type MOS tube are respectively connected with the temperature compensation module.
4. The temperature compensation based reference current source circuit of claim 3, wherein:
the temperature compensation module comprises a biasing unit, the sliding rheostat and two N-type MOS tubes which are connected in sequence;
the drain electrode of the second N-type MOS tube is respectively connected with the drain electrode of the second P-type MOS tube and the source electrode of the first N-type MOS tube;
the drain electrode of the third N-type MOS tube is respectively connected with the drain electrode of the first P-type MOS tube and the drain electrode of the first N-type MOS tube;
the second N-type MOS tube and the third N-type MOS tube share a grid electrode, and the grid electrode of the second N-type MOS tube is connected with the source electrode of the first N-type MOS tube;
the source electrode of the second N-type MOS tube is connected with the biasing unit, the source electrode of the third N-type MOS tube is connected with the first end of the sliding rheostat, and the second end of the sliding rheostat is connected with the biasing unit;
the channel width-length ratio of the second N-type MOS tube is a first preset multiple of the channel width-length ratio of the third N-type MOS tube, and the first preset multiple is a positive integer.
5. The temperature compensation based reference current source circuit of claim 4, wherein:
the bias unit comprises two P-type triodes which are connected in sequence;
the emitting electrode of the first P-type triode is connected with the source electrode of the second N-type MOS tube;
the emitter of the second P-type triode is connected with the second end of the sliding rheostat;
the first P-type triode and the second P-type triode share a base electrode and are connected with the common ground, the collector electrodes of the first P-type triode and the second P-type triode are respectively grounded, the effective area of the emitting area of the second P-type triode is a second preset multiple of the effective area of the emitting area of the first P-type triode, and the second preset multiple is a positive integer.
6. A chip integrated with the temperature compensation based reference current source circuit according to any one of claims 1 to 5, the temperature compensation based reference current source circuit comprising:
the device comprises a temperature compensation module, a current mirror module, a starting module and an output module;
the starting module is used for starting the current mirror module;
the temperature compensation module is used for adjusting the temperature coefficient of the reference current to provide temperature compensation;
the current mirror module is used for generating reference current and mirroring the adjusted reference current to the output module;
the output module is used for outputting the reference current;
the temperature compensation module comprises a sliding rheostat and two N-type MOS tubes which are sequentially connected, and the temperature compensation module enables the grid-source voltage difference of the two N-type MOS tubes not to be zero by adjusting the resistance value of the sliding rheostat and the channel width-length ratio of the two N-type MOS tubes so as to adjust the temperature coefficient of the reference current.
7. The chip of claim 6, wherein:
the current mirror module comprises a first P-type MOS tube and a second P-type MOS tube, the output module comprises a third P-type MOS tube, and the physical sizes of the first P-type MOS tube, the second P-type MOS tube and the third P-type MOS tube are the same;
the source electrodes of the first P-type MOS tube, the second P-type MOS tube and the third P-type MOS tube are connected with a power supply voltage, and the first P-type MOS tube, the second P-type MOS tube and the third P-type MOS tube share a grid electrode;
the drain electrodes of the first P-type MOS tube and the second P-type MOS tube are respectively connected with the starting module and the temperature compensation module;
and the drain electrode of the third P-type MOS tube outputs the reference current.
8. The chip of claim 7, wherein:
the starting module comprises a first N-type MOS tube;
the grid electrode of the first N-type MOS tube is in short circuit with the drain electrode of the first N-type MOS tube;
the drain electrode of the first N-type MOS tube is respectively connected with the grid electrode and the drain electrode of the first P-type MOS tube;
the source electrode of the first N-type MOS tube is connected with the drain electrode of the second P-type MOS tube;
and the drain electrode and the source electrode of the first N-type MOS tube are respectively connected with the temperature compensation module.
9. The chip of claim 8, wherein:
the temperature compensation module comprises a biasing unit, the sliding rheostat and two N-type MOS tubes which are connected in sequence;
the drain electrode of the second N-type MOS tube is respectively connected with the drain electrode of the second P-type MOS tube and the source electrode of the first N-type MOS tube;
the drain electrode of the third N-type MOS tube is respectively connected with the drain electrode of the first P-type MOS tube and the drain electrode of the first N-type MOS tube;
the second N-type MOS tube and the third N-type MOS tube share a grid electrode, and the grid electrode of the second N-type MOS tube is connected with the source electrode of the first N-type MOS tube;
the source electrode of the second N-type MOS tube is connected with the biasing unit, the source electrode of the third N-type MOS tube is connected with the first end of the sliding rheostat, and the second end of the sliding rheostat is connected with the biasing unit;
the channel width-length ratio of the second N-type MOS tube is a first preset multiple of the channel width-length ratio of the third N-type MOS tube, and the first preset multiple is a positive integer.
10. The chip of claim 9, wherein:
the bias unit comprises two P-type triodes which are connected in sequence;
the emitting electrode of the first P-type triode is connected with the source electrode of the second N-type MOS tube;
the emitter of the second P-type triode is connected with the second end of the sliding rheostat;
the first P-type triode and the second P-type triode share a base electrode and are connected with the common ground, the collector electrodes of the first P-type triode and the second P-type triode are respectively grounded, the effective area of the emitting area of the second P-type triode is a second preset multiple of the effective area of the emitting area of the first P-type triode, and the second preset multiple is a positive integer.
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| CN201921731594.8U CN210270647U (en) | 2019-10-16 | 2019-10-16 | Reference current source circuit and chip based on temperature compensation |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111522381A (en) * | 2020-04-15 | 2020-08-11 | 南京微盟电子有限公司 | Temperature coefficient adjustable current reference circuit and method |
| CN114546019A (en) * | 2021-08-24 | 2022-05-27 | 南京航空航天大学 | Temperature coefficient adjustable reference voltage source |
| CN115268553A (en) * | 2022-04-20 | 2022-11-01 | 长江存储科技有限责任公司 | Voltage supply circuit, three-dimensional memory device, peripheral circuit, and method for adjusting voltage supply circuit |
-
2019
- 2019-10-16 CN CN201921731594.8U patent/CN210270647U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111522381A (en) * | 2020-04-15 | 2020-08-11 | 南京微盟电子有限公司 | Temperature coefficient adjustable current reference circuit and method |
| CN111522381B (en) * | 2020-04-15 | 2022-04-08 | 南京微盟电子有限公司 | Temperature coefficient adjustable current reference circuit and method |
| CN114546019A (en) * | 2021-08-24 | 2022-05-27 | 南京航空航天大学 | Temperature coefficient adjustable reference voltage source |
| CN114546019B (en) * | 2021-08-24 | 2022-12-23 | 南京航空航天大学 | Temperature coefficient adjustable reference voltage source |
| CN115268553A (en) * | 2022-04-20 | 2022-11-01 | 长江存储科技有限责任公司 | Voltage supply circuit, three-dimensional memory device, peripheral circuit, and method for adjusting voltage supply circuit |
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