CN114546019B - Temperature coefficient adjustable reference voltage source - Google Patents
Temperature coefficient adjustable reference voltage source Download PDFInfo
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- CN114546019B CN114546019B CN202110976555.XA CN202110976555A CN114546019B CN 114546019 B CN114546019 B CN 114546019B CN 202110976555 A CN202110976555 A CN 202110976555A CN 114546019 B CN114546019 B CN 114546019B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
Abstract
The invention discloses a reference voltage source circuit with an adjustable temperature coefficient. The reference voltage source circuit comprises a first current generation circuit and a second voltage regulation circuit, wherein the first current generation circuit mainly comprises four NPN (negative-positive-negative) tubes, a PMOS (P-channel metal oxide semiconductor) tube, two resistors and two variable resistors; the second circuit of voltage regulating circuit mainly comprises two NPN tubes, five PMOS tubes, three resistors and a variable resistor. The invention has the characteristic of adjustable temperature coefficient, and can well meet the use requirements of different temperature coefficient bias voltages of various analog radio frequency circuits.
Description
Technical Field
The invention belongs to the technical field of reference voltage source circuit design, and relates to a temperature coefficient adjustable reference voltage source for a simulation radio frequency circuit.
Background
The reference voltage source and the reference current source are important components of the analog radio frequency circuit and provide bias for the whole circuit. The reference is generated in order to obtain a dc voltage or current independent of temperature and power supply. The performance of many analog rf circuits is affected by the reference, for example, the bias current of the differential pair is generated by the reference, which affects the noise, voltage gain, etc. of the differential pair; stable benchmarks are also needed in AD/DA systems to determine the full range of their inputs or outputs.
For most analog rf circuits, the conventional reference for determining temperature characteristics is usually selected from three forms: (1) a temperature independent reference; (2) Gm of some transistors remains unchanged, the benchmark for constant Gm characteristics; and (3) a Proportional To Absolute Temperature (PTAT) reference. The three references have single temperature characteristics and limited application range. As in high-speed frequency divider circuits, the operating frequency is extremely sensitive to temperature and bias current. In a wider frequency range, the frequency divider needs larger current when working at high frequency and high temperature, so that the reference independent of temperature cannot meet the use requirement. If the PTAT reference is adopted, the lower the temperature, the smaller the current is, the current is reduced too much at low temperature, and the direct-current operating point of the frequency divider deviates from a normal operating area. Therefore, the traditional standard is difficult to meet the requirement of a high-speed circuit, and has single form and poor universality.
Disclosure of Invention
The invention solves the technical problems that: the defects of the prior art are overcome, and the reference voltage source with the adjustable temperature coefficient is provided, so that the positive temperature coefficient, the negative temperature coefficient and the reference which does not change along with the temperature can be realized, and the use requirements of different analog radio frequency circuits are met. The circuit has simple structure and strong universality.
The technical solution of the invention is as follows:
a reference voltage source with adjustable temperature coefficient comprises a first path of current generation circuit and a second path of voltage regulation circuit;
the first path of current generation circuit comprises an NPN tube Q1, an NPN tube Q2, an NPN tube Q3, an NPN tube Q4, a PMOS tube M1, a resistor R1, a variable resistor R2, a variable resistor R3 and a resistor R4; the second circuit of voltage regulating circuit comprises an NPN tube Q5, an NPN tube Q6, a PMOS tube M2, a PMOS tube M3, a PMOS tube M4, a PMOS tube M5, a PMOS tube M6, a resistor R5, a resistor R6, a variable resistor R7 and a variable resistor R8;
the base and collector of the NPN transistor Q1 and the base of the NPN transistor Q2 are connected together and are connected to a power supply V through a resistor R1 DD The emitter of the NPN tube Q1 is simultaneously connected to the collector of the NPN tube Q3 and the base of the NPN tube Q4; the collector of the NPN transistor Q2 is simultaneously connected to the drain of the PMOS transistor M1, the gate of the PMOS transistor M2 and the drain of the PMOS transistor M3, and the emitter of the NPN transistor Q2 is simultaneously connected to the base of the NPN transistor Q3 and the collector of the NPN transistor Q4 and is connected to the ground GND through the variable resistor R3; the emitter of the NPN tube Q3 is connected to the ground GND; the emitter of the NPN tube Q4 is connected to the ground GND through the variable resistor R2; the source electrode of the PMOS tube M1 is connected to a power supply V through a resistor R4 DD ；
The collector of the NPN transistor Q5 is connected to the drain of the PMOS transistor M2, the drain of the PMOS transistor M5 and the gate of the PMOS transistor M6 at the same time, the base of the NPN transistor Q5 is connected to the base of the NPN transistor Q6, the collector of the NPN transistor Q6 and the drain of the PMOS transistor M6 at the same time, and the base of the NPN transistor Q5 is connected to the base of the NPN transistor Q6, the collector of the NPN transistor Q6 and the drain of the PMOS transistor M6 at the same timeAs a voltage output terminal V of the whole circuit BG (ii) a The emitter of the NPN tube Q5 is connected to the ground GND through a variable resistor R7; the emitter of the NPN tube Q6 is connected to the ground GND through the variable resistor R8; the source electrode of the PMOS tube M2 is connected to a power supply V through a resistor R5 DD (ii) a The grid electrode of the PMOS tube M3 is connected to the input end of the control signal S, and the source electrode of the PMOS tube M3 is connected to the drain electrode of the PMOS tube M4 and the grid electrode of the PMOS tube M5; the grid electrode of the PMOS tube M4 is connected to the input end of the control signal SN, and the source electrode of the PMOS tube M4 is connected to the power supply V DD (ii) a The source electrode of the PMOS tube M5 is connected to a power supply V through a resistor R6 DD (ii) a The source electrode of the PMOS tube M6 is connected to a power supply V DD 。
Further, the parameters of the NPN transistors Q1, Q2, Q3 and Q4 are the same, and the number of the NPN transistors connected in parallel between the NPN transistors Q1 and Q4 is 8 times that of the NPN transistors Q2 and Q3.
Further, the resistances of the resistor R4, the resistor R5 and the resistor R6 are equal, and the parameters of the PMOS transistor M1, the PMOS transistor M2 and the PMOS transistor M5 are completely the same.
Further, the resistance of the variable resistor R8 needs to be changed along with the variable resistor R7 to keep the resistance consistent, and the parameters of the NPN transistor Q5 and the NPN transistor Q6 are completely consistent.
Compared with the traditional design scheme, the reference voltage source with the adjustable temperature coefficient has the advantages that:
the reference voltage source with adjustable temperature coefficient is realized by adopting a special structure, and the voltage reference with positive temperature coefficient, negative temperature coefficient and no temperature change can be obtained by changing the variable resistor. The universality is strong, and the requirement of most high-speed circuits on reference voltage can be met.
The temperature coefficient adjustable range can be expanded by conveniently switching between two gears through S, SN. Meanwhile, a plurality of switchable branches can be connected in parallel as required, so that the adjustment of multiple gears is realized.
The variable resistor can be realized in various modes such as combination of a resistor string and a switch MOS tube, and the variable resistor is simple in structure and easy to control. The whole circuit area of the voltage source is small, the special structure of the voltage source enables the expandability to be strong, the chip area is small while multi-mode selectable stable voltage is provided, and the cost is reduced.
Drawings
Fig. 1 is a schematic diagram of a wideband monolithically integrated low noise amplifier circuit according to the present invention. In the figure: 100: first way current generation circuit, 200: and the second path of voltage regulating circuit.
FIGS. 2-4 are schematic diagrams of simulation of positive temperature coefficient, negative temperature coefficient and reference voltage which does not change with temperature respectively realized in a temperature range of-55 ℃ to 125 ℃ by changing a control signal S \ SN and adjusting the resistance values of variable resistors R2, R3 and R7.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings.
As shown in fig. 1, the bias reference voltage source with adjustable temperature coefficient according to the present invention includes two parts, namely a first path of current generating circuit 100 and a second path of voltage regulating circuit 200, and the specific circuit structure and connection relationship are described as follows.
The first path of current generation circuit 100 includes an NPN transistor Q1, an NPN transistor Q2, an NPN transistor Q3, an NPN transistor Q4, a PMOS transistor M1, a resistor R1, a variable resistor R2, a variable resistor R3, and a resistor R4. The base and collector of the NPN transistor Q1 and the base of the NPN transistor Q2 are connected together and are connected to a power supply V through a resistor R1 DD The emitter of the NPN transistor Q1 is connected to the collector of the NPN transistor Q3 and the base of the NPN transistor Q4 at the same time; the collector of the NPN transistor Q2 is simultaneously connected to the drain of the PMOS transistor M1, the gate of the PMOS transistor M2 and the drain of the PMOS transistor M3, and the emitter of the NPN transistor Q2 is simultaneously connected to the base of the NPN transistor Q3 and the collector of the NPN transistor Q4 and is connected to the ground GND through the variable resistor R3; the emitter of the NPN tube Q3 is connected to the ground GND; the emitter of the NPN tube Q4 is connected to the ground GND through the variable resistor R2; the source electrode of the PMOS tube M1 is connected to a power supply V through a resistor R4 DD 。
The second voltage regulating circuit 200 includes an NPN transistor Q5, an NPN transistor Q6, a PMOS transistor M2, a PMOS transistor M3, a PMOS transistor M4, a PMOS transistor M5, a PMOS transistor M6, a resistor R5, a resistor R6, a variable resistor R7, and a variable resistor R8. The collector of the NPN transistor Q5 is simultaneously connected with the drain of the PMOS transistor M2, the drain of the PMOS transistor M5 and the gate of the PMOS transistor M6, the base of the NPN transistor Q5 is connected with the base of the NPN transistor Q6, the collector of the NPN transistor Q6 and the PMOS transistorM6 drain electrode as the voltage output end V of the whole circuit BG (ii) a The emitter of the NPN tube Q5 is connected to the ground GND through a variable resistor R7; the emitter of the NPN tube Q6 is connected to the ground GND through the variable resistor R8; the source electrode of the PMOS tube M2 is connected to a power supply V through a resistor R5 DD (ii) a The grid electrode of the PMOS tube M3 is connected to the input end of the control signal S, and the source electrode of the PMOS tube M3 is connected to the drain electrode of the PMOS tube M4 and the grid electrode of the PMOS tube M5; the grid electrode of the PMOS tube M4 is connected to the input end of the control signal SN, and the source electrode of the PMOS tube M4 is connected to the power supply V DD (ii) a The source electrode of the PMOS tube M5 is connected to a power supply V through a resistor R6 DD (ii) a The source electrode of the PMOS tube M6 is connected to a power supply V DD 。
In the invention, the parameters of the NPN tubes Q1, Q2, Q3 and Q4 are the same, and the number of the parallel-connected NPN tubes of the NPN tubes Q1 and Q4 is 8 times of that of the NPN tubes Q2 and Q3. The resistance values of the resistor R4, the resistor R5 and the resistor R6 are equal; parameters of the PMOS tube M1, the PMOS tube M2 and the PMOS tube M5 are identical. The resistance value of the variable resistor R8 needs to be changed along with the variable resistor R7, and the resistance values are kept consistent; the parameters of the NPN transistor Q5 and the NPN transistor Q6 are completely the same.
The variable resistors R2, R3, R7 and R8 can be realized by a plurality of methods such as a resistor series-parallel multi-way switch and the like. Supply voltage V DD It was 3.3V.
Setting currents flowing through NPN tubes Q1 and Q2 as I1 and I respectively; the currents flowing through the variable resistors R2, R3 and R7 are respectively I2, I3 and I7; base-emitter voltages of NPN tubes Q1, Q2, Q3, Q4 and Q5 are respectively V be 1、V be 2、V be 3、V be 4、V be 5; the number of the unit tubes of the NPN tubes Q2 and Q3 connected in parallel is m; the number of unit tubes of the NPN tubes Q1 and Q4 connected in parallel is 8m; the base voltage of NPN tube Q1 is V ref 。
Can write the base voltage V of the Q1 of the NPN tube ref The expression of (a) is as follows:
base voltage V of NPN tube Q1 ref Another expression of (a) is as follows:
according to the formulas (1) and (2):
the parameters of unit tubes of NPN tubes Q1, Q2, Q3 and Q4 are all the same, so that the saturation currents are equal to I S =I S1 =I S2 =I S3 =I S4 . The currents flowing through the unit tubes of the NPN tubes Q1, Q2, Q3 and Q4 are respectively
、
、
、
. Thus, equation (3) can be written as:
according to the formula
The expression for the current I can be written as follows:
s, SN is a pair of inverted control signals, when S is "1" and SN is "0", PMOS transistor M3 is turned off, PMOS transistor M4 is turned on, and the gate of PMOS transistor M5 is connected to V DD Is turned off; when S is 0 and SN is 1, the PMOS tube M3 is opened, the PMOS tube M4 is closed, and the grid electrode of the PMOS tube M5 is connected with the grid electrode of the PMOS tube M1.
The current I7 is a mirror image current of I, and parameters of PMOS tubes M1, M2 and M5 are consistent, when S is '1' and SN is '0': i7= I; when S is "0" and SN is "1": i7=2I.
The final band gap voltage V can be written BG The expression of (a) is as follows:
the formula (5) can be obtained:
k =1 when S is "1"; k =2 when S is "0". The temperature coefficients of the resistance and the current in the formula (7) are mutually offset, and only V T 、V be 3、V be 5 includes the temperature coefficient, V BG The temperature deviation can be obtained by:
wherein k is Boltzmann's constantNumber, q is the electron charge amount, V T Voltage equivalent for temperature:
，E g is the bandgap energy of silicon. When V is be The value can be calculated when K is 750mV and T is 300 degrees K:
，
. The first term of equation (8) is known as positive temperature coefficient, the latter two terms are known as negative temperature coefficient, and can be obtained in the following formula:
from the above formula, V is known BG The positive, negative and large of the temperature coefficient can be adjusted by changing the control signal S \ SN and adjusting the resistance values of the variable resistors R2, R3 and R7. Meanwhile, the formula (5) shows that the magnitude of the current I3 can be changed by adjusting the resistance value of the variable resistor R3.
The grid indexes of the PMOS tubes M2 and M5 can be respectively changed into different multiples of the PMOS tube M1 so as to meet the design requirement, and when the PMOS tubes M2 and M5 are changed, the resistors R5 and R6 are required to be simultaneously changed into corresponding multiples of the resistor R4 so as to ensure the stability of the mirror current.
All the resistors, NPN tubes and PMOS tubes are of the same type, so that temperature coefficient deviation caused by the process is eliminated.
Schematic diagrams of simulation of positive temperature coefficient, negative temperature coefficient and reference voltage which does not change along with the temperature within the temperature range of-55 ℃ to 125 ℃ are shown in fig. 2, 3 and 4 by changing a control signal S \ SN and adjusting the resistance values of variable resistors R2, R3 and R7, wherein the horizontal axis is temperature, the unit is centigrade, and the vertical axis is voltage, and the unit is volt (V).
The three diagrams of fig. 2 to fig. 4 are only simulation schematic diagrams of the circuit function, and can adjust the control signal S \ SN and the resistances of the variable resistors R2, R3 and R7 according to actual needs, so as to realize reference voltages with different temperature coefficients within the temperature range of-55 ℃ to 125 ℃.
Those skilled in the art will appreciate that the details of the invention not described in detail in the specification are within the skill of those skilled in the art. Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various changes or modifications within the scope of the appended claims.
Claims (4)
1. A reference voltage source with adjustable temperature coefficient is characterized in that: the circuit comprises a first path of current generating circuit (100) and a second path of voltage regulating circuit (200);
the first path of current generation circuit (100) comprises an NPN tube Q1, an NPN tube Q2, an NPN tube Q3, an NPN tube Q4, a PMOS tube M1, a resistor R1, a variable resistor R2, a variable resistor R3 and a resistor R4; the second voltage regulating circuit (200) comprises an NPN tube Q5, an NPN tube Q6, a PMOS tube M2, a PMOS tube M3, a PMOS tube M4, a PMOS tube M5, a PMOS tube M6, a resistor R5, a resistor R6, a variable resistor R7 and a variable resistor R8;
the base and collector of the NPN transistor Q1 and the base of the NPN transistor Q2 are connected together and are connected to a power supply V through a resistor R1 DD The emitter of the NPN tube Q1 is simultaneously connected to the collector of the NPN tube Q3 and the base of the NPN tube Q4; a collector of the NPN transistor Q2 is connected to the drain of the PMOS transistor M1, the gate of the PMOS transistor M2, and the drain of the PMOS transistor M3, and an emitter of the NPN transistor Q2 is connected to the base of the NPN transistor Q3 and the collector of the NPN transistor Q4, and is connected to ground GND through the variable resistor R3; the emitter of the NPN tube Q3 is connected to the ground GND; the emitter of the NPN tube Q4 is connected to the ground GND through the variable resistor R2; the source electrode of the PMOS tube M1 is connected to a power supply V through a resistor R4 DD ；
The collector of the NPN transistor Q5 is simultaneously connected to the drain of the PMOS transistor M2, the drain of the PMOS transistor M5 and the gate of the PMOS transistor M6, the base of the NPN transistor Q5 is connected to the base of the NPN transistor Q6, the collector of the NPN transistor Q6 and the drain of the PMOS transistor M6, and simultaneously serves as the voltage output end V of the whole circuit BG (ii) a The emitter of the NPN tube Q5 is connected to the ground GND through the variable resistor R7; the emitter of the NPN tube Q6 is connected to the ground GND through the variable resistor R8; the source electrode of the PMOS tube M2 is connected to a power supply V through a resistor R5 DD (ii) a The grid electrode of the PMOS tube M3 is connected to the input end of the control signal S, and the source electrode of the PMOS tube M3 is connected to the drain electrode of the PMOS tube M4 and the grid electrode of the PMOS tube M5; the grid electrode of the PMOS tube M4 is connected to the input end of the control signal SN, and the source electrode of the PMOS tube M4 is connected to the power supply V DD (ii) a The source electrode of the PMOS tube M5 is connected to a power supply V through a resistor R6 DD (ii) a The source electrode of the PMOS tube M6 is connected to a power supply V DD ；
The port S/SN is set as follows according to the requirement: s is connected to a power supply V DD SN is connected to ground GND; or S is connected to ground GND, SN is connected to power supply V DD 。
2. The adjustable-temperature-coefficient reference voltage source of claim 1, wherein: the parameters of the NPN transistors Q1, Q2, Q3 and Q4 are the same, and the number of the NPN transistors connected in parallel between the NPN transistors Q1 and Q4 is 8 times that of the NPN transistors Q2 and Q3.
3. The adjustable temperature coefficient reference voltage source of claim 1, wherein: the resistances of the resistor R4, the resistor R5 and the resistor R6 are equal, and the parameters of the PMOS tube M1, the PMOS tube M2 and the PMOS tube M5 are completely the same.
4. The adjustable temperature coefficient reference voltage source of claim 1, wherein: the resistance value of the variable resistor R8 needs to be changed along with the variable resistor R7, the resistance values are kept consistent, and the parameters of the NPN tube Q5 and the NPN tube Q6 are completely consistent.
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| CN114995569B (en) * | 2022-06-07 | 2024-02-27 | 思瑞浦微电子科技（苏州）股份有限公司 | Reference voltage calibration circuit and calibration method |
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