CN103246311A - Non-resistor band-gap reference voltage source with high-order curvature compensation - Google Patents

Non-resistor band-gap reference voltage source with high-order curvature compensation Download PDF

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CN103246311A
CN103246311A CN2013101954525A CN201310195452A CN103246311A CN 103246311 A CN103246311 A CN 103246311A CN 2013101954525 A CN2013101954525 A CN 2013101954525A CN 201310195452 A CN201310195452 A CN 201310195452A CN 103246311 A CN103246311 A CN 103246311A
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drain
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CN103246311B (en
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明鑫
李涅
张庆岭
苟超
张晓敏
周泽坤
王卓
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电子科技大学
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Abstract

The invention relates to a reference voltage source and discloses a non-resistor band-gap reference voltage source with high-order curvature compensation. According to the technical scheme, the reference voltage source comprises a first current source module, a second current source module, a high-order current generating module and a reference voltage generation module. A first bias voltage generated by the first current source module is connected with one input end of the high-order current generating module and one input end of the reference voltage generation module. A second bias voltage generated by the second current source module is connected with the other input end of the high-order current generating module, a third bias voltage generated by the high-order current generating module is connected with the other input end of the reference voltage generation module, and an output end of the reference voltage generation module outputs a reference voltage. According to the non-resistor band-gap reference voltage source, the high-order curvature compensation method is used, so that the band-gap reference voltage source of the low-voltage coefficient is obtained.

Description

带有高阶曲率补偿的无电阻带隙基准电压源技术领域 No resistance bandgap voltage reference Field curvature compensation Higher Order

[0001 ] 本发明涉及一种基准电压源,属于模拟集成电路技术领域。 [0001] The present invention relates to a reference voltage source, it belongs to the field of analog integrated circuit technology.

背景技术 Background technique

[0002] 在模拟集成电路或混合信号设计领域,基准电压源是非常重要且常用的模块,应用在模拟与数字转换器、功率转换器、功率放大器等电路中,它的作用是为系统提供一个不随温度及供电电压变化的电压基准。 [0002] In the analog integrated circuit or mixed signal design, a reference voltage source is a very important and common modules, with application of the analog-digital converter, the power converter, power amplifier and other circuits, its role is to provide a system for the the reference voltage does not vary with temperature and supply voltage variations.

[0003] 传统的基准电压源通常依靠带隙基准电路产生,如图1所示,其包括误差放大器Al,PMOS管Ml、M2和M3构成的镜像电流源,电阻RU R2以及PNP管Tl、T2、T3。 [0003] The conventional reference voltage source typically rely on generating a bandgap reference circuit, shown in Figure 1, which includes an error amplifier Al, PMOS tube of Ml, M2 and M3, the current mirror configuration, the resistance RU R2 and a PNP transistor Tl, T2 , T3. 则根据双极型晶体管的电压电流特性得到基准输出电压Vkef Vkef reference voltage output is obtained in accordance with voltage-current characteristic of the bipolar transistor

[0004] [0004]

Figure CN103246311AD00031

[0005] 其中Vebq3是双极型晶体管T3的发射极与基极电压差 [0005] wherein Vebq3 an emitter and the base voltage of bipolar transistor T3, the difference

Figure CN103246311AD00032

Κ是波尔兹曼常数,Q是单位电荷的电量,T是温度。 Κ is the Boltzmann constant, Q is the unit of electricity charge, T is the temperature.

[0006] 虽然警 [0006] Although police

Figure CN103246311AD00033

为温度的一阶项,但电压Vebq3的温度特性是呈非线性的,因此现有 For the first-order term of the temperature, but the temperature characteristic of the voltage non-linear Vebq3 it is therefore conventional

技术的带隙基准电压源的温度特性并不能达到很好的效果,需要采用其他的补偿方式来达到更高的基准电压精度。 Bandgap reference voltage source, and the temperature characteristics of art does not achieve good results, we need additional compensation to achieve higher accuracy of the reference voltage. 另外,由于现有技术的带隙基准电压源需要借助电阻实现,在一些特定的工艺中,例如标准数字CMOS (Complementary Metal-Oxide-Semiconductor)工艺往往没有电阻模型或者电阻模型并不可靠,因此无法使用传统架构来设计基准源。 Further, since the band gap reference voltage source required by the prior art to achieve resistance, in certain processes, such as standard digital CMOS (Complementary Metal-Oxide-Semiconductor) process is often no electrical resistance or resistance model model is not reliable, and therefore not the use of traditional architecture design reference source. 虽然现有技术中有以产生高阶电流来补偿带隙基准电压源的技术,但上述缺点依然存在,且温度特性并不够理想。 While the prior art has to generate a high-order current is compensated with a voltage reference technique, but still the above drawbacks, and the temperature characteristic and is not ideal.

发明内容 SUMMARY

[0007] 本发明所要解决的技术问题,就是提供一种带有高阶曲率补偿的无电阻带隙基准电压源,采用高阶曲率补偿方法,获得更低温度系数的带隙基准电压源。 [0007] The present invention solves the technical problem is to provide no resistance bandgap voltage reference with one kind of higher order curvature compensation, higher order curvature compensation method, to obtain a lower bandgap voltage reference temperature coefficient.

[0008] 本发明解决所述技术问题,采用的技术方案是,带有高阶曲率补偿的无电阻带隙基准电压源,包括第一电流源模块、第二电流源模块、高阶电流产生模块和基准电压产生模块;其中,第一电流源模块产生的第一偏置电压连接到高阶电流产生模块的一个输入端和基准电压产生模块的一个输入端;第二电流源模块产生的第二偏置电压连接到高阶电流产生模块的另一个输入端,高阶电流产生模块产生第三偏置电压连接到基到准电压产生模块的另一个输入端;基准电压产生模块的输出端输出基准电压。 [0008] The present invention solves the technical problem, the technical solution adopted is no resistance bandgap reference voltage source having higher order curvature compensation module comprises a first current source, a second current source module, the high-order current generating modules and a reference voltage generating module; wherein a first bias voltage to generate a first current source connected to the high-order module generates a current input terminal and a reference voltage generating module input module; a second module to generate a second current source a bias voltage generating module connected to the high-order current input terminal of the other, high-order current generation module generates the other input terminal connected to the third bias voltage generating reference voltage to the base of the module; generating a reference voltage output terminal of the reference module Voltage.

[0009] 具体的,所述高阶电流产生模块包括,PMOS管:MP1、MP2、MP3、MP4、MP5、MP6、MPN1、MPN2、MPN3、MPN4, NMOS 管:MN1、MN2、MN3、MN4,以及运算放大器;其中:MP1 的栅极与MP2、MP3的栅极相连连接输入第一偏置电压,源极连接电源电压,漏极连接丽I的栅极和漏极以及丽2的栅极,丽I的源极连接地电位;丽2的源极连接地电位,漏极连接MP2的漏极以及MPNl的栅极、漏极、源极和MPN2的衬底电位,MPNl的衬底连接地电位;MPN2的栅极、漏极、源极相连连接到MP3的漏极以及运算放大器的反向输入端;MP2、MP3的源极均连接电源电压;运算放大器的同相输入端连接MP4的漏极以及MPN3的栅极、漏极、源极,输出连接到MP4、MP6的栅极作为该模块的输出第三偏置电压,MP4的源极连接电源电压;MPN3的衬底电位连接到MPN4的栅极、漏极、源极以及MP5、丽3的漏极,MPN4的衬底连接到地电位;MP5的 [0009] Specifically, the module comprises a high-order current is generated, the PMOS tube: MP1, MP2, MP3, MP4, MP5, MP6, MPN1, MPN2, MPN3, MPN4, NMOS tube: MN1, MN2, MN3, MN4, and an operational amplifier; wherein: MP1 and the gate of MP2, MP3 is connected to the gate input connected to a first bias voltage, a source connected to a power supply voltage, a drain connected to the gate and the drain and gate of Korea Korea I 2, Li source I is connected to a ground potential; Li potential source 2 is connected, the drain connected to the drain and the substrate potential of the MP2 MPNl gate, drain, source and MPN2, the potential of the substrate is connected to MPNl; MPN2 gate, a drain, a source connected to the inverting input terminal connected to the drain of MP3 and an operational amplifier; a source of MP2, MP3 are both connected to a power supply voltage; inverting input terminal of the operational amplifier is connected to the drain of MP4 and MPN3 gate, a drain, a source, connected to the output MP4, MP6 gate as the output of the third module of the bias voltage source is connected to a power supply voltage MP4; MPN3 substrate potential is connected to the gate MPN4, a drain, a source, and MP5, Li drain, MPN4 substrate 3 is connected to a ground potential; of MP5 极连接输入第二偏置电压,源极连接电源电压;MN3的栅极连接MN4的栅极和漏极以及MP6的漏极,丽3以及MN4的源极连接地电位;MP6的源极连接电源电压。 Second bias voltage connected to the input electrode, a source electrode connected to a power supply voltage; a gate and a drain connected to the gate of MN3 and the drain of MP6 and MN4, MN4, and the potential of the source electrode 3 Li connectively; MP6 power source connected Voltage.

[0010] 具体的,所述基准电压产生模块包括,PMOS管:MP7、MP8、MP9、MP10、MPlU MP12,NMOS管:丽5、MN6、丽7、MN8,以及PNP管:Q1 ;其中,MP7的栅极与MP8、MP10的栅极相连连接输入第一偏置电压,源极连电源电压,漏极连接丽5的栅极和漏极以及MN6、丽7的栅极,丽5的源极连接地电位;MN6的源极连接地电位,漏极连接MPll的漏极以及MN8的栅极;MP11的栅极连接MP8、MP9的漏极以及Ql的发射极,源极连接MP12的源极以及MP10、MN8的漏极,MN8的源极连接地电位;MP12的栅极与漏极相连连接MN7的漏极作为基准电压产生模块的输出端,丽7的源极连接地电位;MP8、MP9、MP10的源极均连接电源电压,MP9的栅极连接输入第三偏置电压;Q1的基极与集电极相连并连接到地电位。 [0010] Specifically, the reference voltage generating module comprises, the PMOS tube: MP7, MP8, MP9, MP10, MPlU MP12, NMOS tube: Li 5, MN6, Korea 7, MN8, and a PNP transistor: Ql; wherein, MP7 the gate of MP8, MP10 is connected to the gate input connected to a first bias voltage, a source connected a power supply voltage, a drain connected to the drain and gate of Korea and the gate of MN6 5, 7 Li, the source electrode 5 Li connecting a ground potential; MN6 source is connected to ground potential, a drain and a gate connected to the drain of MN8 of MPll; MP11 is connected to the gate of MP8, MP9 emitter of Ql and the drain electrode, a source electrode connected to the source of MP12 and MP10, the drain of MN8, MN8 source connected to a ground potential; MP12 is connected to the gate and drain connected to the drain of MN7 output terminal as the reference voltage generating module, Li source 7 is connected to ground potential; MP8, MP9, MP10 are connected to the power source voltage, a gate connected to the input of the third bias voltage MP9; Ql is connected to the collector and base connected to ground potential.

[0011] 本发明的有益效果是,由于采用高阶曲率补偿,使得双极型晶体管的发射极与基极电压差近似为一个随温度线性变化的负温度系数电压,然后通过基准电压产生模块叠加一个正温度系数的线性化电压,产生基准输出电压,因此该带隙基准电压源具有更好的温度特性,能够提供更高的基准电压精度。 [0011] Advantageous effects of the present invention is that, due to the higher order curvature compensation, so that the emitter and the base voltage of the bipolar transistor is approximately the difference between a negative temperature coefficient voltage varies linearly with temperature, and then superimposed by the reference voltage generation module a linear positive temperature coefficient of voltage, generating a reference output voltage, and therefore the band gap reference voltage source having better temperature characteristic, to provide higher accuracy of a reference voltage. 本发明的带隙基准电压源未采用电阻模型,所以能够很好地兼容一些无电阻或者电阻模型精度不高的工艺,例如标准数字CMOS工艺等。 Bandgap reference voltage source according to the present invention does not employ a resistor model can be highly compatible with some of the resistance or non-resistance model accuracy is not high technology, such as a standard digital CMOS process or the like.

附图说明 BRIEF DESCRIPTION

[0012] 图1为现有技术带隙基准电压源示意图; [0012] FIG. 1 is a prior art schematic diagram of a bandgap reference voltage source;

[0013] 图2为本发明的带隙基准电压源结构示意图; [0013] The bandgap reference voltage source structure of Figure 2 is a schematic view of the present disclosure;

[0014] 图3为闻阶电流广生|旲块结构不意图; [0014] FIG. 3 is a smell order current Kwong Sang | Dae block structure is not intended;

[0015] 图4为基准电压产生模块结构示意图; [0015] Fig 4 a schematic view of a module structure generating a reference voltage;

[0016] 图5为本发明带隙基准电压源输出电压随温度变化波形图; [0016] Figure 5 band-gap reference voltage source the output voltage changes with temperature waveform diagram of the present invention;

[0017] 图6为本发明带隙基准电压源输出电压PSRR波形图。 [0017] FIG. 6 bandgap reference voltage source PSRR output voltage waveform diagram of the present invention.

[0018]其中,MUM2, M3, MPK MP2, MP3, MP4,MP5, MP6,MPNU MPN2, MPN3, MPN4,MP7, MP8,MP9、MP10、MPl1、MP12 为PMOS (P-Metal-Oxide-Semiconductor)管;MN1、MN2、MN3、MN4、MN5、MN6、MN7、MN8 为NMOS (N-Metal-Oxide-Semiconductor)管;T1、Τ2、Τ3、Ql 为PNP 管(PNP型晶体管);R1、R2为电阻;A1、OP为运算放大器。 [0018] wherein, MUM2, M3, MPK MP2, MP3, MP4, MP5, MP6, MPNU MPN2, MPN3, MPN4, MP7, MP8, MP9, MP10, MPl1, MP12 is a PMOS (P-Metal-Oxide-Semiconductor) tube ; MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8 of NMOS (N-Metal-Oxide-Semiconductor) pipe; T1, Τ2, Τ3, Ql is a PNP transistor (PNP transistor); R1, R2 is a resistor ; A1, oP an operational amplifier.

具体实施方案 Specific embodiments

[0019] 下面结合附图和具体的实施例对本发明作进一步详细描述。 Drawings and specific embodiments of the present invention will be further described in detail [0019] below in conjunction.

[0020] 针对传统带隙基准电压源所存在的弊端,本发明提出了一种带有高阶曲率补偿的高精度无电阻带隙基准电压源,具体电路架构如图2所示,包括第一电流源模块,第二电流源模块,高阶电流产生模块、基准电压产生模块四个部分。 [0020] for the shortcomings of traditional bandgap reference voltage source is present, the present invention proposes a High Precision Higher Order curvature compensation resistor no bandgap reference voltage source, the specific circuit structure shown in Figure 2, comprises a first current source module, the second current source module, a high-order current generation module, a reference voltage generating section four modules. 其中第一电流源模块产生第一偏置电压VBl连接到高阶电流产生模块的一个输入端和基准电压产生模块的一个输入端;第二电流源模块产生第二偏置电压VB2连接到高阶电流产生模块的另一个输入端,而高阶电流产生模块产生第三偏置电压VB3连接到基到准电压产生电路的另一个输入端;基准电压产生模块的输出端输出基准电压VREF。 Wherein the first module generates a first current source connected to the bias voltage VBl to generate a high-order current input terminal and a reference voltage generating module input module; a second current source module generates a second bias voltage VB2 is connected to the high-order current generating the other input terminal of the module, the high-order current generation module generates another input terminal connected to the third bias voltage VB3 to the base reference voltage generating circuit; a reference voltage generating module output terminal reference voltage VREF.

[0021] 上述方案中高阶电流产生模块如图3所示,其由10个? [0021] The high-order current is generated in the embodiment shown in Figure 3 module, which is composed of 10? 1©5管:1^1、1^2、1^3、1^4、MP5、MP6、MPN1、MPN2、MPN3、MPN4 (其中MPN1、MPN2、MPN3、MPN4 作为PN 结使用,所以会描述其衬底电位连接方式,其他PMOS管衬底电位均连接电源电压VIN),4个NMOS管:丽1、丽2、丽3、MN4,以及一个运算放大器OP组成。 Tube 1 © 5: 1 ^ 1,1 ^ 2,1 ^ 3,1 ^ 4, MP5, MP6, MPN1, MPN2, MPN3, MPN4 (wherein MPN1, MPN2, MPN3, MPN4 used as a PN junction, so the description thereof will be a substrate potential connection, other PMOS transistor are connected to the substrate potential supply voltage VIN), 4 two NMOS tube: 1 Li, Li 2, Li 3, MN4, and a composition of the operational amplifier OP. 具体连接关系为:MP1的栅极与MP2、MP3的栅极相连连接输入第一偏置电压VBl,源极连接电源电压VIN,漏极连接丽I的栅极和漏极以及丽2的栅极,丽I的源极连接地电位VSS ;丽2的源极连接地电位VSS,漏极连接MP2的漏极以及MPNl的栅极、漏极、源极和MPN2的衬底电位,MPNl的衬底连接地电位;MPN2的栅极、漏极、源极相连连接到MP3的漏极以及运算放大器OP的反向输入端;MP2、MP3的源极均连接电源电压VIN ;运算放大器OP的同相输入端连接MP4的漏极以及MPN3的栅极、漏极、源极,输出连接到MP4、MP6的栅极作为该模块的输出第三偏置电压VB3,MP4的源极连接电源电压VIN ;MPN3的衬底电位连接到MPN4的栅极、漏极、源极以及MP5、MN3的漏极,MPN4的衬底连接到地电位;MP5的栅极连接输入第二偏置电压VB2,源极连接电源电压VIN ;丽3的栅极连接MN4的栅极和漏极以及MP6的漏极,丽3以及MN4的 DETAILED connection relationship: MP1 and the gate of MP2, MP3 is connected to the gate input connected to a first bias voltage VBl, a source connected to the supply voltage VIN, the drain connected to the gate and the drain and gate Li I Li 2 , I Li source potential VSS is connected to ground; Li 2 gate source potential VSS is connected to ground, a drain connected to the drain of MP2 and MPNl, a drain, source and substrate potential of MPN2, MPNl substrate connecting a ground potential; MPN2 a gate, a drain, a source connected to an inverting input terminal connected to the drain of MP3 and an operational amplifier OP; source MP2, MP3 are both connected to the VIN voltage supply; inverting input terminal of the operational amplifier OP with and a gate connected to the drain of MP4 MPN3, a drain, a source, connected to the output MP4, MP6 gate as the third bias voltage VB3 output of the module, the source electrode connected to a power supply voltage MP4 VIN; MPN3 liner the potential of the gate connected to the bottom MPN4, a drain, a source, and MP5, the drain of MN3, MPN4 substrate connected to ground potential; MP5 second input connected to the gate bias voltage VB2, and a source connected to the power supply voltage VIN ; Li gate 3 and the gate and drain connected to the drain of MP6 and MN4, MN4 is 3, and Li 极连接地电位;MP6的源极连接电源电压VIN。 It is connected to ground potential; MP6 is connected to the power source voltage VIN.

[0022] 上述基准电压产生模块如图4所示,其由6个? [0022] The reference voltage generating module shown in FIG. 4, which is a 6? ]\«)5管1^7、]\^8、]\^9、]\^10、]\^11、MP12,4个NMOS管丽5、MN6、丽7、MN8,以及一个PNP双极型晶体管Ql组成。 ] \ «) 5 1 ^ 7,] \ ^ 8,] \ ^ 9,] \ ^ 10,] \ ^ 11, MP12,4 a NMOS transistor Korea 5, MN6, Korea 7, MN8, and a PNP-bis transistor Ql electrode composition. 具体连接关系为:MP7的栅极与MP8、MPlO的栅极相连连接输入第一偏置电压VB1,源极连电源电压VIN,漏极连接丽5的栅极和漏极以及MN6、丽7的栅极,丽5的源极连接地电位;MN6的源极连接地电位,漏极连接MPll的漏极以及MN8的栅极;MP11的栅极连接MP8、MP9的漏极以及Ql的发射极,源极连接MP12的源极以及MP10、MN8的漏极,MN8的源极连接地电位;MP12的栅极与漏极相连连接丽7的漏极作为基准的输出端VREF,丽7的源极连接地电位;MP8、MP9、MPlO的源极均连接电源电压VIN,MP9的栅极连接输入第三偏置电压VB3 ;Q1的基极与集电极相连连接到地电位VSS。 DETAILED connection relationship: MP7 and the gate of MP8, MPlO gate connected to a first input connected to a bias voltage VB1, a source connected power voltage VIN, the drain connected to the gate and drain of Korea 5 and MN6, Korea 7 the gate, the source 5 is connected Li ground potential; MN6 is connected to a ground potential source, a drain and a gate connected to the drain of MN8 of MPll; MP11 is connected to the gate of MP8, MP9 emitter electrode of Ql and the drain, a source electrode connected to the source of MP12 and MP10, the drain of MN8, MN8 source connected to a ground potential; MP12 is connected to the gate and drain connected to the drain 7 Li as a reference output terminal VREF, the source electrode 7 is connected to Li ground potential; MP8, MP9, MPlO are connected to the power source voltage VIN, a gate connected to the input of the third bias voltage VB3 MP9; Ql base connected to the collector is connected to the ground potential VSS.

[0023] 上述第一电流源模块与第二电流源模块的具体结构可以参见相关资料,在此不再对这两个模块的电路架构进行描述,只对用到的一些关键性原理进行说明。 [0023] The specific configuration of the first current source module and the second current source module can be found in the relevant information, which is not the circuit structure of these two modules will be described, only some of the key principles of the use will be described. 其中第一电流源模块通过两个PNP晶体管的Veb电压差产生PTAT电压Λ Veb,并将该电压加于工作在线性区的MOS管两端而产生μ Vt 2电流;而第二电流源模块通过提取MOS管阈值电压,并将所提取出的阈值电压加在工作于线性区的MOS管两端而产生UVra2电流。 Wherein a first current source module is generated by a voltage difference Veb two PNP transistor PTAT voltage Λ Veb, and the voltage applied to generate μ Vt 2 across the current MOS transistor operating in the linear region; and a second current source module extracting the threshold voltage of the MOS transistor, and the threshold voltage of the proposed extraction is applied to both ends MOS transistor operating in the linear region is generated UVra2 current. 由于在MOS管中迁移率y=CT_n,其中C为常系数,η值为1.5左右的常数;而Vth为NMOS管的阈值电压,Vth=Vtho (1-λ Τ)随温度升高线性减小(V.为温度OK时MOS管的阈值电压,λ为NMOS管阈 Since the mobility of the MOS transistor y = CT_n, where C is a constant coefficient, η is a constant of about 1.5; Vth is the threshold voltage of the NMOS transistor, Vth = Vtho (1-λ Τ) decreases linearly with increasing temperature threshold voltage (V. when the temperature is OK MOS pipe, λ is the NMOS transistor threshold

值电压的温度系数绝对值);另外 Value of the voltage temperature coefficient of the absolute value); in addition

Figure CN103246311AD00051

,随温度升高线性增大。 , Increases linearly with increasing temperature. 因此本发明所提出的隙 Thus the present invention proposed gap

基准电压源中第一电流源模块产生正温度系数电流,而第二电流源模块产生负温度系数电流。 A reference voltage source generating a first current source module positive temperature coefficient current and the second current source generates a negative temperature coefficient current block. [0024] 上述高阶电流产生模块中MP1、MP2、MP3的宽长比相同,又栅极均连接第一偏置电压VB1,因此流过他们的电流也相同,所以MP1、MP2、MP3上流过的电流I1=K1U Vt 2 (K1为常系数);而MP5的栅极连接第二偏置电压VB2,所以MP5上流过的电流I2=K2U Vra2(k2为常系数);另外晶体管MP4、MP6的宽长比相同,且栅极电压均为第三偏置电压VB3,因此流过MP4、MP6的电流也相同,均为高阶电流I3。 [0024] The current generating high-order module MP1, MP2, MP3 same width to length ratio, and a first gate bias voltage VBl are connected, the current flowing through them is the same, the MP1, MP2, MP3 flows a current I1 = K1U Vt 2 (K1 is a constant coefficient); MP5 and a gate connected to a second bias voltage VB2, the current flowing through it MP5 I2 = K2U Vra2 (k2 is a constant coefficients); Moreover transistors MP4, MP6 of the same aspect ratio, and the gate voltage of the third bias voltage VB3 are, flowing through MP4, MP6 same current, are high-order current I3. 这样就会使MP3中电流和丽2电流对消,MP4中电流和丽3电流对消,从而流过MPNl的电流由MP2提供,流过MPN4的电流由MP5提供。 This will cause the current MP3 and Li 2 current cancellation, MP4 and Li 3 current cancellation currents, so the current flowing through MPNl provided by the MP2, the current flowing through MPN4 provided by MP5.

[0025] 以下为高阶电流产生模块的工作原理:由于运算放大器OP的钳位作用,使得运放的同相输入端与反向输入端电压相同,因此VN=VP,同时OP的输出端又控制MP4产生所需的高阶电流I3 ;又PMOS管MPN1、MPN2、MPN3、MPN4的栅极、漏极、源极相连作为一个输入端,而衬底作为另外一个输入端,因此形成一个PN结,其中栅极、漏极、源极相连的一端作为PN结的正向端,衬底作为PN结的反向端,因此由PN结电流电压关系得: [0025] The following working principle of generation of high-order current module: since the clamping action of the operational amplifier OP, so that the operational amplifier noninverting input terminal and inverting input terminal voltage of the same, so VN = VP, while an output terminal OP and control MP4 produce the desired high-order current I3; and PMOS transistors MPN1, MPN2, MPN3, MPN4 gate, a drain, a source connected as the input terminal, while the substrate as a further input terminal, thus forming a PN junction, wherein the forward end of a gate, a drain, a source connected to one end of a PN junction, PN junction substrate as the opposite end, by a PN junction thus obtained current-voltage relationship:

[0026] [0026]

Figure CN103246311AD00061

其中n、m 为1、2、3、4,为MPNl 〜MNPN4 的序号) Wherein n, m is 1, 2, ~MNPN4 the number of MPNl)

[0027]又 VMPN1+VmPN2_VmPN3+VmPN4 [0027] and VMPN1 + VmPN2_VmPN3 + VmPN4

[0028] 因此可得 [0028] Accordingly available

[0029] [0029]

Figure CN103246311AD00062

(K3 为常系数) (K3 is a constant coefficient)

[0030] 由于λ较小,因此 [0030] Due to the small λ, so

[0031] [0031]

Figure CN103246311AD00063

[0033] 所以高阶电流产生模块产生高阶温度系数电流,该电流可以用于补偿双极型晶体管发射极与基极电压差VEB电压在高温时的非线性,从而产生一个近似随温度线性变化的电压VEB,为基准电压的产生奠定基础。 [0033] Therefore, high-order current generation module generates order temperature coefficient current, which can be used to compensate for the bipolar transistor emitter-base voltage VEB difference voltage non-linear at high temperature, resulting in an approximately linear variation with temperature voltage VEB, lay the foundation for generating a reference voltage.

[0034] 另外本发明的高阶电流产生模块将PMOS管ΜΡΝ1、ΜΡΝ2、ΜΡΝ3、ΜΡΝ4连接成PN结,来代替传统采用BJT (Bipolar Junction Transistor)来产生高阶电流,不但大大减小了芯片设计的面积,并且该电路也克服了采用传统BJT基极电流对高阶电流产生模块的不利影响。 [0034] Further according to the present invention produces high-order current module PMOS transistor ΜΡΝ1, ΜΡΝ2, ΜΡΝ3, ΜΡΝ4 connected PN junction, instead of the traditional use of BJT (Bipolar Junction Transistor) to generate a high-order current, not only greatly reduce the chip design area, and the circuit also overcomes the conventional BJT base current generating high-order current module adverse effects.

[0035] 上述基准电压产生模块将第一电流源模块以及高阶电流产生模块产生的电流进行电流镜像并叠加输入到PNP双极型晶体管中,从而流入到Q1的电流 [0035] The reference voltage generating module, and a first current source module generates a current order current generated by the current mirror module, and superimposes the input to the PNP bipolar transistor, whereby the current flowing into Q1

[0036] [0036]

Figure CN103246311AD00064
Figure CN103246311AD00071

[0044] 其中Vetl为温度OK时硅的带隙电压;η为值3.5左右的常系数'K、B均为电流镜的镜像比例,可以通过改变ΜΡ8、ΜΡ9宽长比进行设置;Κ3为常系数,可以通过改变高阶电流产生模块中的ΜΡ1、ΜΡ3、ΜΡ4、ΜΡ5宽长比进行设置;Ε为与温度无关的常量。 [0044] wherein the temperature is OK when Vetl silicon bandgap voltage; [eta] value of about 3.5 for the constant coefficient 'K, B are the current mirror ratio of the mirror can ΜΡ8, ΜΡ9 aspect ratio set by the changing; normally Kappa3 factor, can be produced by changing the high-order current module ΜΡ1, ΜΡ3, ΜΡ4, ΜΡ5 aspect ratio set; Epsilon temperature-independent constant. 由于Vebqi公式中最后一项是包括温度的三次方项、四次方项、五次项等高次项。 As the last of which was Vebqi formula including temperature cubic term, to the fourth item, item five high-order terms. 因此来自于VTlnT的非线性可以通过合理的设置MP8、MP9的宽长比参数以及高阶电流产生模块中MP1、MP3、MP4、MP5宽长比进行抵消,从而使Vebqi电压成为一个近似随温度线性减小的电压。 Thus from VTlnT nonlinearity can MP8, MP9 width to length ratio parameter generation module MP1 and reasonable order current setting, MP3, MP4, MP5 offsetting aspect ratio, so that a voltage is Vebqi approximately linearly with temperature reduced voltage.

[0045] 该基准电压产生模块中晶体管MP10、MN6、丽7流过电流均为μ V;2电流的镜像电流,因此流过MPll和ΜΡ12的电流也为μ V;2电流的常系数倍。 [0045] The reference voltage generating module transistors MP10, MN6, the current flowing through Li 7 are μ V; a second current mirror current, and thus MPll current also flows through ΜΡ12 μ V; constant factor times the second current.

[0046] 所以 [0046] Therefore,

Figure CN103246311AD00072

[0049] 因此 [0049] Therefore

Figure CN103246311AD00073

[0054] 所以 [0054] Therefore,

[0055] [0055]

Figure CN103246311AD00074

[0056] 因此通过合理设置Ml、M2以及MP11、MP12的宽长比,可以最终使 [0056] Therefore, by setting a reasonable Ml, M2 and aspect ratio MP11, MP12 can eventually

Figure CN103246311AD00075

,所 , The

以最终得到一个近似不随温度变化的基准电压VREF。 To obtain a final temperature of approximately not change with the reference voltage VREF.

[0057] 该模块中MP8的作用是用来产生一个负反馈环路,用于多条之路的电流平衡,同时该负反馈也增大了基准电路的PSRR (Power Supply Rejection Ratio)。 [0057] The action module MP8 is used to generate a negative feedback loop for current balancing of a plurality of paths, while the negative feedback also increases the reference circuit PSRR (Power Supply Rejection Ratio).

[0058] 本发明所提出的高精度无电阻带隙基准源,通过hspice仿真表明,在温度范围从-40V至100°C,其温度系数仅有4.2ppm/°C,如图5所示。 [0058] The present invention is made with high accuracy without the bandgap reference resistor, by hspice simulation shows, from -40V to 100 ° C, the temperature coefficient of only 4.2ppm / ° C in a temperature range, as shown in FIG. 输入电压从2.4V至5V,其带隙基准电压变化范围仅有lmV。 Input voltage range from 2.4V to 5V, the bandgap reference voltage which varies only lmV. 在输入电压3V、25°C且无外挂电容的情况下低频PSRR高达56dB,如图6所示。 When the input voltage of 3V, 25 ° C and the case where no plug capacitance low PSRR up 56dB, as shown in FIG.

[0059] 本领域的普通技术人员将会意识到,这里所述的实施例是为了帮助读者理解本发明的原理,本发明的保护范围并不局限于这样的特别陈述和实施例。 [0059] Those of ordinary skill in the art will appreciate that the embodiments described herein are to aid the reader in understanding the principles of the present invention, the scope of the present invention is not limited to such embodiments and specifically stated. 本领域的普通技术人员可以根据本发明公开的这些技术启示做出各种不脱离本发明实质的其它各种具体变形和组合,这些变形和组合仍然在本发明的保护范围内。 Those of ordinary skill in the art can make various modifications and other various concrete compositions of the present invention without departing from the spirit of techniques according to teachings of the present disclosure, it is still within the scope of the present invention such variations and combinations.

Claims (3)

1.带有高阶曲率补偿的无电阻带隙基准电压源,包括第一电流源模块、第二电流源模块、高阶电流产生模块和基准电压产生模块;其中,第一电流源模块产生的第一偏置电压连接到高阶电流产生模块的一个输入端和基准电压产生模块的一个输入端;第二电流源模块产生的第二偏置电压连接到高阶电流产生模块的另一个输入端,高阶电流产生模块产生第三偏置电压连接到基到准电压产生模块的另一个输入端;基准电压产生模块的输出端输出基准电压。 1. No resistance bandgap reference voltage source having higher order curvature compensation module comprises a first current source, a second current source module, a high-order current generation module and a reference voltage generating module; wherein the module generates a first current source a first bias voltage to generate a high-order current is connected to the input terminal and the reference voltage input of a module generating module; a second bias voltage to generate a second current source module is connected to the high-order module of the current generating the other input terminal , high-order current generation module generates another input terminal connected to the third bias voltage generating reference voltage to the base of the module; reference voltage generating module output terminal reference voltage.
2.根据权利要求1所述的带有高阶曲率补偿的无电阻带隙基准电压源,其特征在于,所述高阶电流产生模块包括,PMOS 管:MP1、MP2、MP3、MP4、MP5、MP6、MPNl、MPN2、MPN3、MPN4,NMOS管:丽1、丽2、丽3、MN4,以及运算放大器;其中:MP1的栅极与MP2、MP3的栅极相连连接输入第一偏置电压,源极连接电源电压,漏极连接丽I的栅极和漏极以及丽2的栅极,丽I的源极连接地电位;丽2的源极连接地电位,漏极连接MP2的漏极以及MPNl的栅极、漏极、源极和MPN2的衬底电位,MPNl的衬底连接地电位;MPN2的栅极、漏极、源极相连连接到MP3的漏极以及运算放大器的反向输入端;MP2、MP3的源极均连接电源电压;运算放大器的同相输入端连接MP4的漏极以及MPN3的栅极、漏极、源极,输出连接到MP4、MP6的栅极作为该模块的输出第三偏置电压,MP4的源极连接电源电压;MPN3的衬底电位连接到MPN4的栅 The resistance free voltage reference with a bandgap higher order curvature compensation according to claim 1, wherein said module comprises a high-order current is generated, the PMOS tube: MP1, MP2, MP3, MP4, MP5, MP6, MPNl, MPN2, MPN3, MPN4, NMOS tube: 1 Li, Li 2, Li 3, MN4, and an operational amplifier; wherein: MPl gate and MP2, MP3 is connected to the gate input connected to a first bias voltage, a source connected to a power supply voltage, a drain connected to the gate and the drain and gate of Korea Korea I 2, I Li potential of the source electrode is connected to ground; Li source 2 is connected to a ground potential, and a drain connected to the drain of MP2 MPNl gate, the drain, source and substrate potential of MPN2, MPNl substrate is connected to ground potential; MPN2 a gate, a drain, a source connected to an inverting input terminal connected to the drain of MP3 operational amplifier the first output of the operational amplifier inverting input terminal connected to a drain and a gate MPN3 MP4, a drain, a source, connected to the output MP4, MP6 gate as the module;; source MP2, MP3 are both connected to a supply voltage three bias voltage source is connected to a power supply voltage MP4; MPN3 substrate potential is connected to the gate of MPN4 极、漏极、源极以及MP5、MN3的漏极,MPN4的衬底连接到地电位;MP5的栅极连接输入第二偏置电压,源极连接电源电压;丽3的栅极连接MN4的栅极和漏极以及MP6的漏极,丽3以及MN4的源极连接地电位;MP6的源极连接电源电压。 , A drain, a source, and MP5, the drain of MN3, MPN4 substrate connected to ground potential; MP5 is connected to the gate of a second bias voltage input, a source connected to a power supply voltage; a gate connected MN4 of Li 3 and a drain gate and the drain of MP6, 3 and Li source MN4 is connected to ground potential; MP6 is connected to a supply voltage source.
3.根据权利要求1所述的带有高阶曲率补偿的无电阻带隙基准电压源,其特征在于,所述基准电压产生模块包括,PMOS 管:MP7、MP8、MP9、MP10、MP11、MP12,NMOS 管:MN5、MN6、MN7、MN8,以及PNP管:Q1 ;其中,MP7的栅极与MP8、MPlO的栅极相连连接输入第一偏置电压,源极连电源电压,漏极连接丽5的栅极和漏极以及MN6、丽7的栅极,丽5的源极连接地电位;MN6的源极连接地电位,漏极连接MPll的漏极以及MN8的栅极;MP11的栅极连接MP8、MP9的漏极以及Ql的发射极,源极连接MP12的源极以及MP10、MN8的漏极,MN8的源极连接地电位;MP12的栅极与漏极相连连接MN7的漏极作为基准电压产生模块的输出端,MN7的源极连接地电位;MP8、MP9、MP10的源极均连接电源电压,MP9的栅极连接输入第三偏置电压;Ql的基极与集电极相连并·连接到地电位。 The resistance free voltage reference with a bandgap higher order curvature compensation according to claim 1, wherein said reference voltage generating module comprises, the PMOS tube: MP7, MP8, MP9, MP10, MP11, MP12 , the NMOS tube: MN5, MN6, MN7, MN8, and a PNP transistor: Q1; wherein, the gate of MP7 and MP8, MPlO gate connected to a first input connected to a bias voltage, a source connected a power supply voltage, a drain connected Li and the drain potential of the gate 5 and the gate of MN6, 7 Li, the source 5 is connected to Korea; potential, a drain connected to the drain and the gate of MN6, MN8 MPll a source connected to ground; the gate of MP11 emitter connected MP8, MP9, and the drain electrode of Ql, a source connected to a source of MP12 and MP10, the drain of MN8, MN8 source connected to a ground potential; MP12 is connected to the gate and drain connected to the drain of MN7 as reference voltage generating module output terminal, a source electrode connected to the ground potential MN7; MP8, MP9, MP10 are connected to a source of supply voltage, a gate connected to the input of the third bias voltage MP9; of Ql, and the base connected to the collector · connected to ground potential.
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