CN103246311A - Non-resistor band-gap reference voltage source with high-order curvature compensation - Google Patents

Abstract

The invention relates to a reference voltage source and discloses a non-resistor band-gap reference voltage source with high-order curvature compensation. According to the technical scheme, the reference voltage source comprises a first current source module, a second current source module, a high-order current generating module and a reference voltage generation module. A first bias voltage generated by the first current source module is connected with one input end of the high-order current generating module and one input end of the reference voltage generation module. A second bias voltage generated by the second current source module is connected with the other input end of the high-order current generating module, a third bias voltage generated by the high-order current generating module is connected with the other input end of the reference voltage generation module, and an output end of the reference voltage generation module outputs a reference voltage. According to the non-resistor band-gap reference voltage source, the high-order curvature compensation method is used, so that the band-gap reference voltage source of the low-voltage coefficient is obtained.

Description

The Bandgap Reference Without Resistors that has the high-order curvature compensation

Technical field

The present invention relates to a kind of reference voltage source, belong to the Analogous Integrated Electronic Circuits technical field.

Background technology

In Analogous Integrated Electronic Circuits or mixed-signal designs field, reference voltage source is module very important and commonly used, be applied in the circuit such as simulation and digital quantizer, power converter, power amplifier, its effect is to provide a voltage reference that does not change with temperature and supply voltage for system.

Traditional reference voltage source relies on band-gap reference circuit to produce usually, and as shown in Figure 1, it comprises error amplifier A1, the mirror current source that PMOS pipe M1, M2 and M3 constitute, resistance R 1, R2 and PNP pipe T1, T2, T3.Then the voltage-current characteristic according to bipolar transistor obtains the benchmark output voltage V _REF

$V_{\mathrm{REF}}=V_{\mathrm{EBQ}3}+\frac{R_2}{R_1}{V}_T\ln N$

V wherein _EBQ3Be emitter and the base voltage difference of bipolar transistor T3; K is Boltzmann constant, and q is the electric weight of unit charge, and T is temperature.

Though

LnN is the single order item of temperature, but voltage V _EBQ3Temperature characterisitic be to be nonlinear, so the temperature characterisitic of the bandgap voltage reference of prior art can not reach good effect, needs to adopt other compensation way to reach higher reference voltage precision.In addition, because the bandgap voltage reference of prior art need be realized by resistance, in some specific technologies, standard digital CMOS(Complementary Metal-Oxide-Semiconductor for example) technology does not often have Resistance model for prediction or Resistance model for prediction and unreliable, therefore can't use conventional architectures to come the design basis source.Though have to produce the technology that the high-order electric current comes compensation band gap reference voltage source in the prior art, above-mentioned shortcoming still exists, and temperature characterisitic and not ideal enough.

Summary of the invention

Technical matters to be solved by this invention just provides a kind of Bandgap Reference Without Resistors that has the high-order curvature compensation, adopts the high-order curvature compensation method, obtains the more bandgap voltage reference of low-temperature coefficient.

The present invention solve the technical problem, and the technical scheme of employing is, has the Bandgap Reference Without Resistors of high-order curvature compensation, comprises first current source module, second current source module, high-order current generating module and reference voltage generation module; Wherein, first bias voltage that produces of first current source module is connected to input end of high-order current generating module and an input end of reference voltage generation module; Second bias voltage that second current source module produces is connected to another input end of high-order current generating module, and the high-order current generating module produces the 3rd bias voltage and is connected to base to another input end of accurate voltage generating module; The output terminal output reference voltage of reference voltage generation module.

Concrete, described high-order current generating module comprises, the PMOS pipe: MP1, MP2, MP3, MP4, MP5, MP6, MPN1, MPN2, MPN3, MPN4, NMOS pipe: MN1, MN2, MN3, MN4, and operational amplifier; Wherein: the grid of MP1 is imported first bias voltage with the grid phase downlink connection of MP2, MP3, and source electrode connects supply voltage, and drain electrode connects the grid of MN1 and the grid of drain electrode and MN2, and the source electrode of MN1 connects earth potential; The source electrode of MN2 connects earth potential, the substrate electric potential of the drain electrode of drain electrode connection MP2 and grid, drain electrode, source electrode and the MPN2 of MPN1, and the substrate of MPN1 connects earth potential; The grid of MPN2, drain electrode, source electrode are connected to the drain electrode of MP3 and the reverse input end of operational amplifier; The source electrode of MP2, MP3 all connects supply voltage; The in-phase input end of operational amplifier connects the drain electrode of MP4 and grid, drain electrode, the source electrode of MPN3, and output is connected to the grid of MP4, MP6 as output the 3rd bias voltage of this module, and the source electrode of MP4 connects supply voltage; The substrate electric potential of MPN3 is connected to grid, drain electrode, source electrode and the MP5 of MPN4, the drain electrode of MN3, and the substrate of MPN4 is connected to earth potential; The grid of MP5 connects input second bias voltage, and source electrode connects supply voltage; The grid of MN3 connects the grid of MN4 and the drain electrode of drain electrode and MP6, and the source electrode of MN3 and MN4 connects earth potential; The source electrode of MP6 connects supply voltage.

Concrete, described reference voltage generation module comprises, the PMOS pipe: MP7, MP8, MP9, MP10, MP11, MP12, NMOS pipe: MN5, MN6, MN7, MN8, and PNP pipe: Q1; Wherein, the grid of MP7 is imported first bias voltage with the grid phase downlink connection of MP8, MP10, and source electrode connects supply voltage, and drain electrode connects the grid of MN5 and the grid of drain electrode and MN6, MN7, and the source electrode of MN5 connects earth potential; The source electrode of MN6 connects earth potential, and drain electrode connects the drain electrode of MP11 and the grid of MN8; The grid of MP11 connects the drain electrode of MP8, MP9 and the emitter of Q1, and source electrode connects the source electrode of MP12 and the drain electrode of MP10, MN8, and the source electrode of MN8 connects earth potential; The drain electrode of the grid of MP12 and drain electrode phase downlink connection MN7 is as the output terminal of reference voltage generation module, and the source electrode of MN7 connects earth potential; The source electrode of MP8, MP9, MP10 all connects supply voltage, and the grid of MP9 connects input the 3rd bias voltage; The base stage of Q1 links to each other with collector and is connected to earth potential.

The invention has the beneficial effects as follows, owing to adopt the high-order curvature compensation, make emitter and the base voltage difference of bipolar transistor be approximately a negative temperature coefficient voltage that changes with temperature linearity, pass through the linearization voltage of a positive temperature coefficient (PTC) of reference voltage generation module stack then, produce the benchmark output voltage, therefore this bandgap voltage reference has better temperature characterisitic, and higher reference voltage precision can be provided.Bandgap voltage reference of the present invention does not adopt Resistance model for prediction, so can be well more compatible non-resistances or the not high technology of Resistance model for prediction precision, for example standard digital CMOS technology etc.

Description of drawings

Fig. 1 is prior art bandgap voltage reference synoptic diagram;

Fig. 2 is bandgap voltage reference structural representation of the present invention;

Fig. 3 is high-order current generating module structural representation;

Fig. 4 is reference voltage generation module structural representation;

Fig. 5 varies with temperature oscillogram for bandgap voltage reference output voltage of the present invention;

Fig. 6 is bandgap voltage reference output voltage PSRR oscillogram of the present invention.

Wherein, M1, M2, M3, MP1, MP2, MP3, MP4, MP5, MP6, MPN1, MPN2, MPN3, MPN4, MP7, MP8, MP9, MP10, MP11, MP12 are PMOS(P-Metal-Oxide-Semiconductor) pipe; MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8 are NMOS(N-Metal-Oxide-Semiconductor) pipe; T1, T2, T3, Q1 are PNP pipe (PNP transistor); R1, R2 are resistance; A1, OP are operational amplifier.

Specific embodiments

Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail.

At the existing drawback of traditional bandgap voltage reference, the present invention proposes a kind of high precision Bandgap Reference Without Resistors that has the high-order curvature compensation, the physical circuit framework as shown in Figure 2, comprise first current source module, second current source module, high-order current generating module, four parts of reference voltage generation module.Wherein first current source module produces the first bias voltage VB1 and is connected to input end of high-order current generating module and an input end of reference voltage generation module; Second current source module produces another input end that the second bias voltage VB2 is connected to the high-order current generating module, and the high-order current generating module produces the 3rd bias voltage VB3 and is connected to base to another input end of accurate voltage generation circuit; The output terminal output reference voltage VREF of reference voltage generation module.

The high-order current generating module as shown in Figure 3 in the such scheme, it is managed by 10 PMOS: MP1, MP2, MP3, MP4, MP5, MP6, MPN1, MPN2, MPN3, MPN4(wherein MPN1, MPN2, MPN3, MPN4 use as PN junction, so can describe its substrate electric potential connected mode, other PMOS pipe substrate electric potentials all connect supply voltage VIN), 4 NMOS pipes: MN1, MN2, MN3, MN4, and an operational amplifier OP forms.Concrete annexation is: the grid of MP1 is imported the first bias voltage VB1 with the grid phase downlink connection of MP2, MP3, and source electrode connects supply voltage VIN, and drain electrode connects the grid of MN1 and the grid of drain electrode and MN2, and the source electrode of MN1 connects earth potential VSS; The source electrode of MN2 connects earth potential VSS, the substrate electric potential of the drain electrode of drain electrode connection MP2 and grid, drain electrode, source electrode and the MPN2 of MPN1, and the substrate of MPN1 connects earth potential; The grid of MPN2, drain electrode, source electrode are connected to the drain electrode of MP3 and the reverse input end of operational amplifier OP; The source electrode of MP2, MP3 all connects supply voltage VIN; The in-phase input end of operational amplifier OP connects the drain electrode of MP4 and grid, drain electrode, the source electrode of MPN3, and output is connected to the grid of MP4, MP6 as output the 3rd bias voltage VB3 of this module, and the source electrode of MP4 connects supply voltage VIN; The substrate electric potential of MPN3 is connected to grid, drain electrode, source electrode and the MP5 of MPN4, the drain electrode of MN3, and the substrate of MPN4 is connected to earth potential; The grid of MP5 connects the input second bias voltage VB2, and source electrode connects supply voltage VIN; The grid of MN3 connects the grid of MN4 and the drain electrode of drain electrode and MP6, and the source electrode of MN3 and MN4 connects earth potential; The source electrode of MP6 connects supply voltage VIN.

The said reference voltage generating module as shown in Figure 4, it is by 6 PMOS pipe MP7, MP8, MP9, MP10, MP11, MP12,4 NMOS pipes MN5, MN6, MN7, MN8, and a PNP bipolar transistor Q1 forms.Concrete annexation is: the grid of MP7 is imported the first bias voltage VB1 with the grid phase downlink connection of MP8, MP10, and source electrode connects supply voltage VIN, and drain electrode connects the grid of MN5 and the grid of drain electrode and MN6, MN7, and the source electrode of MN5 connects earth potential; The source electrode of MN6 connects earth potential, and drain electrode connects the drain electrode of MP11 and the grid of MN8; The grid of MP11 connects the drain electrode of MP8, MP9 and the emitter of Q1, and source electrode connects the source electrode of MP12 and the drain electrode of MP10, MN8, and the source electrode of MN8 connects earth potential; The drain electrode of the grid of MP12 and drain electrode phase downlink connection MN7 is as the output terminal VREF of benchmark, and the source electrode of MN7 connects earth potential; The source electrode of MP8, MP9, MP10 all connects supply voltage VIN, and the grid of MP9 connects input the 3rd bias voltage VB3; The base stage of Q1 links to each other with collector and is connected to earth potential VSS.

The concrete structure of above-mentioned first current source module and second current source module can no longer be described the circuit framework of these two modules at this referring to related data, only some key principles of using is described.Wherein first current source module is by two transistorized V of PNP _EBVoltage difference produces PTAT voltage △ V _EB, and this voltage is added on the metal-oxide-semiconductor two ends that are operated in linear zone and produces μ V _T ^{^2}Electric current; And second current source module passes through to extract the metal-oxide-semiconductor threshold voltage, and the threshold voltage that extracts is added in the metal-oxide-semiconductor two ends that work in linear zone and produces μ V _TH ^{^2}Electric current.Because mobility [mu]=CT in metal-oxide-semiconductor ^-n, wherein C is constant coefficient, the n value is about 1.5 constant; And V _THBe the threshold voltage of NMOS pipe, V _TH=V _TH0(1-λ T) reduces (V with temperature rising linearity _TH0The threshold voltage of metal-oxide-semiconductor during for temperature 0K, λ is the absolute value temperature coefficient of NMOS pipe threshold voltage); In addition

Increase with the temperature rising is linear.So first current source module produces the positive temperature coefficient (PTC) electric current in the crack reference voltage source proposed by the invention, and second current source module produces negative temperature parameter current.

The breadth length ratio of MP1, MP2, MP3 is identical in the above-mentioned high-order current generating module, and grid all connects the first bias voltage VB1 again, and the electric current that therefore flows through them is also identical, so the electric current I that flows through on MP1, MP2, the MP3 ₁=K ₁μ V _T ^{^2}(K ₁Be constant coefficient); And the grid of MP5 connects the second bias voltage VB2, so the electric current I that flows through on the MP5 ₂=K ₂μ V _TH ^{^2}(k ₂Be constant coefficient); The breadth length ratio of transistor MP4, MP6 is identical in addition, and grid voltage is the 3rd bias voltage VB3, and the electric current that therefore flows through MP4, MP6 is also identical, is the high-order electric current I ₃Will make like this that electric current and MN2 electric current offset among the MP3, electric current and MN3 electric current offset among the MP4, thereby the electric current that flows through MPN1 is provided by MP2, and the electric current that flows through MPN4 is provided by MP5.

Below be the principle of work of high-order current generating module: because the clamping action of operational amplifier OP makes that the in-phase input end of amplifier is identical with reverse input end voltage, so VN=VP, the output terminal of OP is controlled MP4 again and is produced required high-order electric current I simultaneously ₃The grid of PMOS pipe MPN1, MPN2, MPN3, MPN4, drain electrode, source electrode link to each other as an input end again, and substrate is as the another one input end, therefore form a PN junction, wherein the end that links to each other of grid, drain electrode, source electrode is as the forward end of PN junction, therefore substrate is got by the PN junction current-voltage correlation as the backward end of PN junction:

(wherein n, m are 1,2,3,4, are the sequence number of MPN1～MNPN4)

V again _MPN1+ V _MPN2=V _MPN3+ V _MPN4

Therefore can get

$I_3=\frac{{I_1}^{^2}}{I_2}=\frac{{{\mathrm{<figure-callout\; id="1"\; label="K"\; filenames="HDA00003236635300011.png,HDA00003236635300021.png"\; state="\{\{state\}\}">K</figure-callout>}}_1}^{^2}\mathrm{\&mu;}{V_T}^{^4}}{K_2{V_{\mathrm{TH}}}^{^2}}=K_3\frac{T^{4-n}}{{(1-\mathrm{\&lambda;T})}^2}$ (K ₃Be constant coefficient)

Because λ is less, therefore

$\frac{1}{{(1-\mathrm{\&lambda;T})}^2}\&ap;{(1+\mathrm{\&lambda;T})}^2$

I ₃≈K ₃T ^4-n(1+λT) ²

So the high-order current generating module produces high-order temperature coefficient electric current, this electric current can be used for non-linear when high temperature of compensation emitter bipolar transistor and base voltage difference VEB voltage, thereby produce an approximate voltage VEB who changes with temperature linearity, for the generation of reference voltage lays the foundation.

In addition high-order current generating module of the present invention with PMOS manage MPN1, MPN2, MPN3, MPN4 connect into PN junction, replace tradition to adopt BJT(Bipolar Junction Transistor) produce the high-order electric current, not only reduced the area of chip design greatly, and this circuit has also overcome the adverse effect of employing traditional B JT base current to the high-order current generating module.

The said reference voltage generating module carries out the electric current of first current source module and the generation of high-order current generating module current mirror and superposes being input in the PNP bipolar transistor, thereby flow into Q ₁Electric current

${\mathrm{<figure-callout\; id="1"\; label="I\; Q"\; filenames="HDA00003236635300011.png,HDA00003236635300021.png"\; state="\{\{state\}\}">I</figure-callout>}}_Q={\mathrm{<figure-callout\; id="1"\; label="AI"\; filenames="HDA00003236635300011.png,HDA00003236635300021.png"\; state="\{\{state\}\}">AI</figure-callout>}}_1+{\mathrm{BI}}_3={\mathrm{AT}}^{2-n}+{\mathrm{BK}}_3{T}^{4-n}{(1+\mathrm{\&lambda;T})}^2={\mathrm{AT}}^{2-n}[1+\frac{{\mathrm{BK}}_3{T}^2{(1+\mathrm{\&lambda;T})}^2}{A}]$

And

$V_{\mathrm{<figure-callout\; id="1"\; label="EBQ"\; filenames="HDA00003236635300011.png,HDA00003236635300021.png"\; state="\{\{state\}\}">EBQ</figure-callout>}1}=V_T\ln \left[I_{Q1}{T}^{-\mathrm{\&eta;}}\mathrm{Eexp}\left(\frac{V_{\mathrm{Go}}}{V_T}\right)\right]$

$=V_{G0}+V_T\ln \mathrm{AE}-(\mathrm{\&eta;}+n-2)V_T\ln T+V_T\ln [1+\frac{{\mathrm{BK}}_3{T}^2{(1+\mathrm{\&lambda;T})}^2}{A}]$

Again

ln(1+x)≈x-x ^{^2}/2

${\mathrm{<figure-callout\; id="1"\; label="V\; EBQ"\; filenames="HDA00003236635300011.png,HDA00003236635300021.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{EBQ}}\&ap;V_{G0}+V_T\ln \mathrm{AE}-(\mathrm{\&eta;}+n-2)V_T\ln T+\frac{\mathrm{KB}{K}_3{T}^2{(1+\mathrm{\&lambda;T})}^{2}T}{\mathrm{qA}}[1-\frac{{\mathrm{BK}}_3{T}^2{(1+\mathrm{\&lambda;T})}^2}{2A}]$

$\&ap;V_{G0}+V_T\ln \mathrm{AE}-(\mathrm{\&eta;}+n-2)V_T\ln T+\frac{\mathrm{KB}{K}_3}{2q{A}^2}[2A{T}^3+4\mathrm{A\&lambda;}{T}^4+(2A{\mathrm{\&lambda;}}^2-{\mathrm{BK}}_3)T^5]$

V wherein _G0The band gap voltage of silicon during for temperature 0K; η is the constant coefficient of value about 3.5; A, B are the mirror image ratio of current mirror, can arrange by change MP8, MP9 breadth length ratio; K ₃Be constant coefficient, can arrange by MP1, MP3, MP4, the MP5 breadth length ratio that changes in the high-order current generating module; E is temperature independent constant.Because V _EBQ1Last is cube item, biquadratic item, five high-order terms such as item that comprise temperature in the formula.Therefore come from V _TLnT non-linear can be by MP8, MP9 reasonably be set the breadth length ratio parameter and the high-order current generating module in MP1, MP3, MP4, MP5 breadth length ratio offset, thereby make V _EBQ1Voltage becomes an approximate voltage that reduces with temperature linearity.

Transistor MP10, MN6, MN7 flow through electric current and are μ V in this reference voltage generation module _T ^{^2}The image current of electric current, the electric current that therefore flows through MP11 and MP12 also is μ V _T ^{^2}The constant coefficient of electric current doubly.

So

$I_{\mathrm{MP}11}={\mathrm{<figure-callout\; id="1"\; label="M"\; filenames="HDA00003236635300011.png,HDA00003236635300021.png"\; state="\{\{state\}\}">M</figure-callout>}}_1\mathrm{\&mu;}{V_T}^{^2}=\frac{\mathrm{\&mu;}{C}_{\mathrm{OX}}}{2}{\left(\frac{W}{L}\right)}_{\mathrm{MP}11}{(V_{\mathrm{GSMP}11}-V_{\mathrm{THP}})}^2$ (M ₁Be constant coefficient)

${\mathrm{<figure-callout\; id="12"\; label="I\; MP"\; filenames="HDA00003236635300021.png"\; state="\{\{state\}\}">I</figure-callout>}}_{\mathrm{MP}}=M_2\mathrm{\&mu;}{V_T}^{^2}=\frac{\mathrm{\&mu;}{C}_{\mathrm{OX}}}{2}{\left(\frac{W}{L}\right)}_{\mathrm{MP}12}{(V_{\mathrm{GSMP}12}-V_{\mathrm{THP}})}^2$ (M ₂Be constant coefficient)

Therefore

$V_{\mathrm{GSMP}11}=\frac{{2M}_1}{C_{\mathrm{OX}}}{\left(\frac{L}{W}\right)}_{\mathrm{MP}11}{V}_T+V_{\mathrm{THP}}$

$V_{\mathrm{<figure-callout\; id="12"\; label="GSMP"\; filenames="HDA00003236635300021.png"\; state="\{\{state\}\}">GSMP</figure-callout>}12}=\frac{{2M}_2}{C_{\mathrm{OX}}}{\left(\frac{L}{W}\right)}_{\mathrm{MP}12}{V}_T+V_{\mathrm{THP}}$

Again

VREF=V _BEQ1+V _GSMP11-V _GSMP12

So

$\mathrm{VREF}={\mathrm{<figure-callout\; id="1"\; label="V\; BEQ"\; filenames="HDA00003236635300011.png,HDA00003236635300021.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{BEQ}}+\frac{2}{C_{\mathrm{OX}}}[M_1{\left(\frac{L}{W}\right)}_{\mathrm{MP}11}-M_2{\left(\frac{L}{W}\right)}_{\mathrm{MP}12}]V_T$

Therefore by the breadth length ratio of M1, M2 and MP11, MP12 rationally is set, can finally make So finally obtain an approximate not temperature variant reference voltage V REF.

The effect of MP8 is to produce a feedback loop in this module, is used for the current balance type on many road, and this negative feedback has simultaneously also increased the PSRR(Power Supply Rejection Ratio of reference circuit).

High precision non-resistance band gap reference proposed by the invention shows by hspice emulation, and from-40 ℃ to 100 ℃, its temperature coefficient only has 4.2ppm/ ℃, as shown in Figure 5 in temperature range.Input voltage is from 2.4V to 5V, and its bandgap voltage reference variation range only has 1mV.Input voltage 3V, 25 ℃ and do not have under the situation of plug-in capacitor low frequency PSRR up to 56dB, as shown in Figure 6.

Those of ordinary skill in the art will appreciate that, embodiment described here is in order to help reader understanding's principle of the present invention, and protection scope of the present invention is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not break away from essence of the present invention according to these technology enlightenments disclosed by the invention, and these distortion and combination are still in protection scope of the present invention.

Claims (3)

1. the Bandgap Reference Without Resistors that has the high-order curvature compensation comprises first current source module, second current source module, high-order current generating module and reference voltage generation module; Wherein, first bias voltage that produces of first current source module is connected to input end of high-order current generating module and an input end of reference voltage generation module; Second bias voltage that second current source module produces is connected to another input end of high-order current generating module, and the high-order current generating module produces the 3rd bias voltage and is connected to base to another input end of accurate voltage generating module; The output terminal output reference voltage of reference voltage generation module.

2. the Bandgap Reference Without Resistors that has the high-order curvature compensation according to claim 1, it is characterized in that, described high-order current generating module comprises, PMOS pipe: MP1, MP2, MP3, MP4, MP5, MP6, MPN1, MPN2, MPN3, MPN4, NMOS pipe: MN1, MN2, MN3, MN4, and operational amplifier; Wherein: the grid of MP1 is imported first bias voltage with the grid phase downlink connection of MP2, MP3, and source electrode connects supply voltage, and drain electrode connects the grid of MN1 and the grid of drain electrode and MN2, and the source electrode of MN1 connects earth potential; The source electrode of MN2 connects earth potential, the substrate electric potential of the drain electrode of drain electrode connection MP2 and grid, drain electrode, source electrode and the MPN2 of MPN1, and the substrate of MPN1 connects earth potential; The grid of MPN2, drain electrode, source electrode are connected to the drain electrode of MP3 and the reverse input end of operational amplifier; The source electrode of MP2, MP3 all connects supply voltage; The in-phase input end of operational amplifier connects the drain electrode of MP4 and grid, drain electrode, the source electrode of MPN3, and output is connected to the grid of MP4, MP6 as output the 3rd bias voltage of this module, and the source electrode of MP4 connects supply voltage; The substrate electric potential of MPN3 is connected to grid, drain electrode, source electrode and the MP5 of MPN4, the drain electrode of MN3, and the substrate of MPN4 is connected to earth potential; The grid of MP5 connects input second bias voltage, and source electrode connects supply voltage; The grid of MN3 connects the grid of MN4 and the drain electrode of drain electrode and MP6, and the source electrode of MN3 and MN4 connects earth potential; The source electrode of MP6 connects supply voltage.

3. the Bandgap Reference Without Resistors that has the high-order curvature compensation according to claim 1, it is characterized in that described reference voltage generation module comprises, PMOS pipe: MP7, MP8, MP9, MP10, MP11, MP12, NMOS pipe: MN5, MN6, MN7, MN8, and PNP pipe: Q1; Wherein, the grid of MP7 is imported first bias voltage with the grid phase downlink connection of MP8, MP10, and source electrode connects supply voltage, and drain electrode connects the grid of MN5 and the grid of drain electrode and MN6, MN7, and the source electrode of MN5 connects earth potential; The source electrode of MN6 connects earth potential, and drain electrode connects the drain electrode of MP11 and the grid of MN8; The grid of MP11 connects the drain electrode of MP8, MP9 and the emitter of Q1, and source electrode connects the source electrode of MP12 and the drain electrode of MP10, MN8, and the source electrode of MN8 connects earth potential; The drain electrode of the grid of MP12 and drain electrode phase downlink connection MN7 is as the output terminal of reference voltage generation module, and the source electrode of MN7 connects earth potential; The source electrode of MP8, MP9, MP10 all connects supply voltage, and the grid of MP9 connects input the 3rd bias voltage; The base stage of Q1 links to each other with collector and is connected to earth potential.

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