CN104977969B - A kind of band-gap reference reference circuit of high PSRR source compensated by using high-order curvature - Google Patents

Abstract

The invention provides the band-gap reference reference circuit of a kind of high PSRR source compensated by using high-order curvature, including start-up circuit, front regulator circuit, band-gap reference circuit, low-temperature region piecewise linearity temperature-compensation circuit, high-temperature area and absolute temperature T^1.5The temperature-compensation circuit that is directly proportional, high-temperature area piecewise linearity temperature-compensation circuit.The present invention is by by low-temperature region piecewise linearity temperature-compensated current and high-temperature area and absolute temperature T^1.5The temperature-compensated current being directly proportional adds in traditional bandgap reference circuit, and takes high-temperature area piecewise linearity temperature-compensated current from traditional bandgap reference circuit away, thus obtains the reference voltage of source compensated by using high-order curvature；In adjustor technology joins the reference voltage of source compensated by using high-order curvature before negative feedback, thus obtain the band-gap reference reference circuit of high PSRR source compensated by using high-order curvature.

Description

A kind of band-gap reference reference circuit of high PSRR source compensated by using high-order curvature

Technical field

The present invention relates to microelectronics technology, be specifically related to the band gap base of a kind of high PSRR source compensated by using high-order curvature Quasi-reference circuit.

Background technology

Along with the development of integrated circuit, increasing functional module is integrated on same chip.Reference is as collection Become the requisite part of circuit chip, provide stable reference voltage or electric current, its temperature system for whole IC chip Number (TC, Temperature Coefficient) and PSRR (PSRR, Power Supply Rejection Ratio) It is largely fixed the quality of whole integrated circuit chip system performance.Thus, a high precision reference reference circuit requirement Output voltage has low-temperature coefficient and high PSRR characteristic.

Bandgap voltage reference owing to having that temperature performance is good, output voltage stabilization and the advantage such as low in energy consumption and by extensively Application, Fig. 1 gives a kind of conventional first order band-gap reference reference circuit, and resistance R1 is identical with resistance R2, PNP type triode Q2 emitter area is PNP type triode Q1 emitter area m times.The emitter base voltage V of PNP type triode Q1_EB1Tool There is negative temperature characteristic, emitter base voltage difference between PNP type triode Q1 and PNP type triode Q2 Wherein k is Boltzmann constant, and T is absolute temperature, and q is electron charge.The output bandgap voltage reference V of circuit shown in Fig. 1_REF's Expression formula isWherein V_EB2There is negative temperature coefficient,There is positive temperature Degree coefficient, the resistance of reasonably optimizing resistance R2, the resistance of resistance R3 and parameter m, in certain temperature range, just can obtain zero The band-gap reference reference voltage V of temperature coefficient_REF。

Single order band-gap reference reference voltage is made owing to PNP type triode emitter base voltage has nonlinear temperature Having higher temperature coefficient, the working power voltage of band-gap reference reference circuit shown in Fig. 1 is external power source VDD so that defeated Go out band-gap reference reference voltage and there is relatively low PSRR, thus constrain single order band-gap reference circuit at High Definition Systems In application.

Summary of the invention

The application is by providing the band-gap reference reference circuit of a kind of high PSRR source compensated by using high-order curvature, it is possible to significantly Reduce output voltage temperature coefficient, improve output voltage PSRR, thus obtain high-precision reference voltage.

The application is achieved by the following technical solutions:

The band-gap reference reference circuit of a kind of high PSRR source compensated by using high-order curvature, it is it is critical that include starting electricity Road, front regulator circuit, band-gap reference circuit, low-temperature region piecewise linearity temperature-compensation circuit, high-temperature area and absolute temperature T^1.5The temperature-compensation circuit that is directly proportional, high-temperature area piecewise linearity temperature-compensation circuit；

The enabling signal outfan of wherein said start-up circuit connect respectively described front regulator circuit, band-gap reference circuit, Low-temperature region piecewise linearity temperature-compensation circuit, high-temperature area and absolute temperature T^1.5The temperature-compensation circuit being directly proportional and height The enabling signal input of temperature area piecewise linearity temperature-compensation circuit, the signal output part of described band-gap reference circuit connects respectively Described front regulator circuit, low-temperature region piecewise linearity temperature-compensation circuit, high-temperature area and absolute temperature T^1.5The temperature being directly proportional Degree compensates circuit and the signal input part of high-temperature area piecewise linearity temperature-compensation circuit, the voltage of described front regulator circuit Signal output part connects described band-gap reference circuit, low-temperature region piecewise linearity temperature-compensation circuit, high-temperature area respectively with absolute Temperature T^1.5The temperature-compensation circuit being directly proportional and the working power voltage input of high-temperature area piecewise linearity temperature-compensation circuit End, the output voltage signal of described band-gap reference circuit connects the voltage signal inputs of described start-up circuit；

Described start-up circuit makes band-gap reference reference circuit normally work, produce bandgap voltage reference output, described before Regulator circuit is for improving the PSRR of band-gap reference reference circuit, the output voltage V of described front regulator circuit_REG As described band-gap reference circuit, low-temperature region piecewise linearity temperature-compensation circuit, high-temperature area and absolute temperature T^1.5It is directly proportional Temperature-compensation circuit and the working power voltage of high-temperature area piecewise linearity temperature-compensation circuit, described band-gap reference circuit The band gap reference voltage of generation low-temperature coefficient: positive temperature coefficient voltage V_PTATWith negative temperature coefficient voltage V_CTAT, described low-temperature space Territory piecewise linearity temperature-compensation circuit produces low-temperature space and has piecewise linear voltage V_{PC_Low}, described high-temperature area and definitely temperature Degree T^1.5The temperature-compensation circuit being directly proportional produces and absolute temperature T^1.5The voltage being directly proportionalDescribed high-temperature area segmentation Linear temperature compensation circuit produces high-temperature region and has piecewise linear voltage V_PC__High, described low-temperature region piecewise linearity temperature is mended Repay circuit, high-temperature area and absolute temperature T^1.5The temperature-compensation circuit being directly proportional and high-temperature area piecewise linearity temperature-compensating Circuit is for carrying out temperature-compensating to described band-gap reference circuit, it may be assumed that low-temperature space has piecewise linear voltage V_{PC_Low}, and Absolute temperature T^1.5The voltage being directly proportionalJoin in the band gap reference voltage that band-gap reference circuit produces, and from band gap base The bandgap voltage reference that quasi-circuit produces pumps except high-temperature region has piecewise linear voltage V_{PC_High}。

Start-up circuit only plays a role when band-gap reference reference circuit powers on, when band-gap reference reference circuit has started After, start-up circuit quits work, it is to avoid the start-up circuit impact on circuit below.

As the preferred technical scheme of one, described start-up circuit includes: PMOS Ms1, PMOS Ms2, NMOS tube Ms3, NMOS tube Ms4, NMOS tube Ms5, NMOS tube Ms6 and NMOS tube Ms7, the wherein source electrode of PMOS Ms1 and external power source VDD is connected, and the grid of PMOS Ms1 is connected with the source electrode of the drain electrode of PMOS Ms1 and PMOS Ms2, the grid of PMOS Ms2 Pole and the drain electrode of PMOS Ms2, the drain electrode of NMOS tube Ms3, the grid of NMOS tube Ms4, the grid of NMOS tube Ms5, NMOS tube Ms6 Grid and the grid of NMOS tube Ms7 be connected, the source electrode of NMOS tube Ms3 and the source electrode of NMOS tube Ms4, the source of NMOS tube Ms5 Pole, the source electrode of NMOS tube Ms6, the source electrode of NMOS tube Ms7 and outside ground wire GND are connected；

Described front regulator circuit includes: PMOS M1, PMOS M2, NMOS tube M3, NMOS tube M4, PMOS M5, NMOS tube M6, NMOS tube M7 and PMOS M8, wherein the source electrode of PMOS M1 is connected with external power source VDD, PMOS M1 Grid is connected with the drain electrode of drain electrode, the grid of PMOS M2, the drain electrode of NMOS tube Ms4 and NMOS tube M3 of PMOS M1, The grid of NMOS tube M3 and the grid of NMOS tube M6, the grid of NMOS tube M7, the drain electrode of NMOS tube M7 and the leakage of PMOS M8 The most connected, the source electrode of NMOS tube M3 and the source electrode of NMOS tube M4, the source electrode of NMOS tube M6, the source electrode of NMOS tube M7 and externally Line GND is connected, and the source electrode of PMOS M2 is connected with external power source VDD, the drain electrode of PMOS M2 and the drain electrode of NMOS tube M4, PMOS The source electrode of pipe M5, the source electrode of PMOS M8, the source electrode of PMOS M9, the source electrode of PMOS M10, the source electrode of PMOS M11, PMOS The source electrode of pipe M12, the source electrode of PMOS M17, the source electrode of PMOS M18, the source electrode of PMOS M19, the source electrode of PMOS M20, The source electrode of PMOS M26, the source electrode of PMOS M27, the source electrode of PMOS M25, the source electrode of PMOS M28, the source of PMOS M31 The source electrode of pole, the source electrode of PMOS M32, the source electrode of PMOS M33, the source electrode of PMOS M36 and PMOS M37 is connected, The drain electrode of PMOS M5 is connected with the drain electrode of the grid of NMOS tube M4 and NMOS tube M6；

Described band-gap reference circuit includes: PMOS M9, PMOS M10, PMOS M11, PMOS M36, PMOS M37, error amplifier A1, error amplifier A2, PNP type triode Q1, PNP type triode Q2, resistance R1, resistance R2 and electricity Resistance R3, the wherein drain electrode of the PMOS M9 reverse input end with error amplifier A1 and the emitter stage phase of PNP type triode Q1 Even, the grid of PMOS M9 and the grid of PMOS M10, the outfan of error amplifier A1, the drain electrode of NMOS tube Ms5, PMOS The grid of pipe M8, the grid of PMOS M12, the grid of PMOS M20, the grid of PMOS M28 and the grid of PMOS M36 It is connected, the drain electrode of PMOS M10 and the grid of PMOS M5, the positive input of error amplifier A1, error amplifier A2 Reverse input end and resistance R1 are connected, and the other end of resistance R1 is connected with the emitter stage of PNP type triode Q2, positive-negative-positive three pole The base stage of pipe Q1 and the colelctor electrode of PNP type triode Q1, the base stage of PNP type triode Q2, PNP type triode Q2 colelctor electrode with And outside ground wire GND is connected, the grid of PMOS M11 and the outfan of error amplifier A2, the drain electrode of NMOS tube Ms6, PMOS The grid of the grid of pipe M17, the grid of PMOS M31 and PMOS M37 is connected, and the drain electrode of PMOS M11 is amplified with error The positive input of device A2 and resistance R2 are connected, and the other end of resistance R2 is connected with outside ground wire GND, the leakage of PMOS M36 Pole and the drain electrode of PMOS M37, the grid of NMOS tube Ms3, the drain electrode of PMOS M19, the drain electrode of PMOS M25, NMOS tube M35 Drain electrode, the outfan V of band-gap reference reference circuit_REFAnd resistance R3 is connected, the other end of resistance R3 and outside ground wire GND It is connected；

Described low-temperature region piecewise linearity temperature-compensation circuit includes: PMOS M12, NMOS tube M13, NMOS tube M14, NMOS tube M15, NMOS tube M16, PMOS M17, PMOS M18 and PMOS M19, wherein the drain electrode of PMOS M12 with The grid of the drain electrode of NMOS tube M13, the grid of NMOS tube M13 and NMOS tube M14 is connected, the drain electrode of PMOS M17 and NMOS The grid of the drain electrode of pipe M14, the drain electrode of NMOS tube M15, the grid of NMOS tube M15 and NMOS tube M16 is connected, PMOS M18 Drain electrode be connected with the drain electrode of the grid of PMOS M18, the grid of PMOS M19 and NMOS tube M16, the source of NMOS tube M13 Pole is connected with the source electrode of NMOS tube M14, the source electrode of NMOS tube M15, the source electrode of NMOS tube M16 and outside ground wire GND；

Described high-temperature area and absolute temperature T^1.5The temperature-compensation circuit being directly proportional includes: PMOS M20, NMOS tube M21, NMOS tube M22, NMOS tube M23, NMOS tube M24, PMOS M25, PMOS M26 and PMOS M27, wherein PMOS The drain electrode of M20 is connected with the grid of the drain electrode of NMOS tube M21, the grid of NMOS tube M21 and NMOS tube M22, PMOS M26 Drain electrode and the grid of PMOS M26, the grid of PMOS M27, the grid of PMOS M25, the drain electrode of NMOS tube Ms7 and NMOS The drain electrode of pipe M23 is connected, the grid of NMOS tube M23 and the grid of NMOS tube M24, the drain electrode of NMOS tube M24 and PMOS M27 Drain electrode be connected, the source electrode of NMOS tube M23 is connected with the drain electrode of NMOS tube M22, the source electrode of NMOS tube M21 and NMOS tube M22 Source electrode, the source electrode of NMOS tube M24 and outside ground wire GND are connected；

Described high-temperature area piecewise linearity temperature-compensation circuit includes: PMOS M28, NMOS tube M29, NMOS tube M30, PMOS M31, PMOS M32, PMOS M33, NMOS tube M34 and NMOS tube M35, wherein the drain electrode of PMOS M28 with The grid of the drain electrode of NMOS tube M29, the grid of NMOS tube M29 and NMOS tube M30 is connected, the drain electrode of PMOS M31 and PMOS The drain electrode of the drain electrode of pipe M32, the grid of PMOS M32, the grid of PMOS M33 and NMOS tube M30 is connected, PMOS M33 Drain electrode be connected with the grid of the drain electrode of NMOS tube M34, the grid of NMOS tube M34 and NMOS tube M35, the source of NMOS tube M29 Pole is connected with the source electrode of NMOS tube M30, the source electrode of NMOS tube M34, the source electrode of NMOS tube M35 and outside ground wire GND.

Further, in described band-gap reference circuit, PMOS M9 and PMOS M10 have identical breadth length ratio, PMOS The drain current I of M10₁₀For:In formula, k is Boltzmann constant, and T is absolute temperature, and q is electron charge, R₁ For the resistance of resistance R1, N is the ratio of the PNP type triode Q2 emitter area with PNP type triode Q1；

The drain current I of PMOS M11₁₁For:In formula, V_EB1Emitter stage-base stage for PNP type triode Q1 Voltage, R₂Resistance for resistance R2；

In described low-temperature region piecewise linearity temperature-compensation circuit, NMOS tube M13 and NMOS tube M14 have identical wide length Ratio, NMOS tube M15 and NMOS tube M16 have identical breadth length ratio, the drain current I of PMOS M19₁₉At low-temperature space, there is temperature Piece wire characteristic, to compensate the emitter base voltage V of PNP type triode Q1_EB1The temperature high-order nonlinear of low-temperature region ?；

$I_{19}=\left\{\begin{array}{cc}{\mathrm{\&beta;}}_3({\mathrm{\&beta;}}_2\frac{V_{EB1}}{R_2}-{\mathrm{\&beta;}}_1\frac{kT}{{\mathrm{qR}}_1}\ln N)& T<T_{r1}\\ 0& T\&GreaterEqual;T_{r1}\end{array}\right.$

In formula, β₁For the ratio of PMOS M12 with the breadth length ratio of PMOS M10, β₂Width for PMOS M17 Yu PMOS M11 The ratio of long ratio, β₃For the ratio of PMOS M19 with the breadth length ratio of PMOS M18, V_EB1Emitter stage-base stage for PNP type triode Q1 Voltage, R₁For the resistance of resistance R1, R₂For the resistance of resistance R2, k is Boltzmann constant, and T is absolute temperature, and q is electronics electricity Lotus, N is the ratio of the PNP type triode Q2 emitter area with PNP type triode Q1, T_r1For reference temperature.

Further, in described high-temperature area and absolute temperature T^1.5In the temperature-compensation circuit being directly proportional PMOS M20 with PMOS M10 has identical breadth length ratio, and PMOS M26 and PMOS M27 have identical breadth length ratio, the width of PMOS M25 Long than the β being PMOS M26₈Times, NMOS tube M21, PMOS M20, PMOS M26, PMOS M27 and PMOS M25 are equal Being operated in saturation region, NMOS tube M22 is operated in deep linear zone, and NMOS tube M23 and NMOS tube M24 are operated in sub-threshold region, NMOS The breadth length ratio of pipe M23 is the β of NMOS tube M24₇Times, then the drain current I of PMOS M25₂₅For:

$I_{25}\&ap;{\mathrm{n\&beta;}}_8{\left(\frac{W}{L}\right)}_{22}\sqrt{2{\mathrm{\&mu;}}_n{C}_{ox}\ln N}\frac{ln\left({\mathrm{\&beta;}}_7\right)}{\sqrt{R_1{\left(\frac{W}{L}\right)}_{21}}}\frac{k^{1.5}}{q^{1.5}}{T}^{1.5}$

In formula, n is the non-ideal factor more than 1, β₈It is the ratio of the PMOS M25 breadth length ratio with PMOS M26,It is the breadth length ratio of NMOS tube M22, μ_nIt is electron mobility, C_oxBeing unit are gate oxide capacitance, N is positive-negative-positive three pole The ratio of pipe Q2 and the emitter area of PNP type triode Q1, β₇It is the ratio of the NMOS tube M23 breadth length ratio with NMOS tube M24, R₁For The resistance of resistance R1,Being the breadth length ratio of NMOS tube M21, k is Boltzmann constant, and T is absolute temperature, and q is electronics electricity Lotus, the drain current I of PMOS M25₂₅With absolute temperature T¹ _. ⁵It is directly proportional.

Further, in described high-temperature area piecewise linearity temperature-compensation circuit, the breadth length ratio of PMOS M28 is PMOS The β of pipe M10₄Times, NMOS tube M29 and NMOS tube M30 have identical breadth length ratio, and the breadth length ratio of PMOS M31 is PMOS M11 β₅Times, PMOS M32 and PMOS M33 have identical breadth length ratio, and the breadth length ratio of NMOS tube M35 is the β of NMOS tube M34₆ Times, the drain current I of NMOS tube M35₃₅There is temperature section linear characteristic in high-temperature region, to compensate sending out of PNP type triode Q1 Emitter-base voltage V_EB1The temperature high-order nonlinear item of high-temperature area；

$I_{35}=\left\{\begin{array}{cc}{\mathrm{\&beta;}}_6({\mathrm{\&beta;}}_4\frac{kT}{{\mathrm{qR}}_1}\ln N-{\mathrm{\&beta;}}_5\frac{V_{EB1}}{R_2})& T>T_{r2}\\ 0& T\&le;T_{r2}\end{array}\right.$

In formula, β₆It is the ratio of the NMOS tube M35 breadth length ratio with NMOS tube M34, β₄It it is the width of PMOS M28 and PMOS M10 The ratio of long ratio, k is Boltzmann constant, and T is absolute temperature, and q is electron charge, R₁For the resistance of resistance R1, N is positive-negative-positive three The ratio of pole pipe Q2 and the emitter area of PNP type triode Q1, β₅It is the ratio of the PMOS M31 breadth length ratio with PMOS M11, V_EB1For the emitter base voltage of PNP type triode Q1, R₂For the resistance of resistance R2, T_r2For reference temperature.

Further, the breadth length ratio of PMOS M36 is the β of PMOS M10₉Times, the breadth length ratio of PMOS M37 is PMOS The β of M11₁₀Times, the output voltage V of band-gap reference reference circuit_REFFor:

$V_{REF}=V_{PTAT}+V_{CTAT}+V_{PC\_Low}+V_{{\mathrm{PTAT}}^{3/2}}-V_{PC\_High}$

Wherein,

V_PTATFor positive temperature coefficient voltage,

V_CTATFor negative temperature coefficient voltage,

V_{PC_Low}For low-temperature space, there is piecewise linear voltage,

For with definitely temperature T¹ _. ⁵The voltage being directly proportional:

V_{PC_High}For high-temperature region, there is piecewise linear voltage,

In formula, β₉It is the ratio of the PMOS M36 breadth length ratio with PMOS M10, R₃Being the resistance of resistance R3, k is Boltzmann Constant, T is absolute temperature, and q is electron charge, R₁For the resistance of resistance R1, N is PNP type triode Q2 and PNP type triode Q1 The ratio of emitter area, β₁₀It is the ratio of the PMOS M37 breadth length ratio with PMOS M11, V_EB1Sending out for PNP type triode Q1 Emitter-base voltage, R₂For the resistance of resistance R2, β₁For the ratio of PMOS M12 with the breadth length ratio of PMOS M10, β₂For PMOS The ratio of M17 and the breadth length ratio of PMOS M11, β₃For the ratio of PMOS M19 with the breadth length ratio of PMOS M18, T_r1For reference temperature, N is the non-ideal factor more than 1, β₈It is the ratio of the PMOS M25 breadth length ratio with PMOS M26,It it is NMOS tube The breadth length ratio of M22, μ_nIt is electron mobility, C_oxIt is unit are gate oxide capacitance, β₇It is NMOS tube M23 and NMOS tube M24 The ratio of breadth length ratio,Being the breadth length ratio of NMOS tube M21, k is Boltzmann constant, and T is absolute temperature, and q is electronics electricity Lotus, β₆It is the ratio of the NMOS tube M35 breadth length ratio with NMOS tube M34, β₄It is the ratio of the PMOS M28 breadth length ratio with PMOS M10, β₅It is the ratio of the PMOS M31 breadth length ratio with PMOS M11, T_r2For reference temperature.

The band-gap reference reference circuit of the high PSRR source compensated by using high-order curvature of the present invention is by by low-temperature region segmentation Linear temperature compensation electric current I₁₉, high-temperature area and absolute temperature T^1.5The temperature-compensated current I being directly proportional₂₅Join traditional one In the band-gap reference reference circuit of rank, and take high-temperature area piecewise linearity temperature-compensating away from conventional first order band-gap reference reference circuit Electric current I₃₅, will the leakage current I of PMOS M19 in low-temperature region piecewise linearity temperature-compensation circuit₁₉With high-temperature area with exhausted To temperature T^1.5The leakage current I of PMOS M25 in the temperature-compensation circuit being directly proportional₂₅Join on resistance R3, at band-gap reference The outfan V of reference circuit_REFIn take the electric leakage of NMOS tube M35 flow through in high-temperature area piecewise linearity temperature-compensation circuit away Stream I₃₅, thus obtain the reference voltage of source compensated by using high-order curvature, use the reference voltage of the available less temperature coefficient of this technology；This Adjustor technology before one negative feedback is also joined in band-gap reference reference circuit, before will improving PSRR by invention The output voltage V of regulator circuit_REGAs band-gap reference circuit, low-temperature region piecewise linearity temperature-compensation circuit, high-temperature area With absolute temperature T^1.5The temperature-compensation circuit being directly proportional and the working power electricity of high-temperature area piecewise linearity temperature-compensation circuit Pressure, obtains the band-gap reference reference circuit of high PSRR source compensated by using high-order curvature.

Compared with prior art, the technical scheme that the application provides, the technique effect or the advantage that have be: can significantly drop Low output voltage temperature coefficient, improves output voltage PSRR, thus obtains high-precision reference voltage.

Accompanying drawing explanation

Fig. 1 is the principle schematic of conventional first order band-gap reference reference circuit；

Fig. 2 is the structure chart of the band-gap reference reference circuit of the high PSRR source compensated by using high-order curvature of the present invention；

Fig. 3 is the circuit diagram of the band-gap reference reference circuit of the high PSRR source compensated by using high-order curvature of the present invention；

Fig. 4 is single order band-gap reference reference circuit reference voltage curve chart；

Fig. 5 is the output voltage curve of the band-gap reference reference circuit of the high PSRR source compensated by using high-order curvature of the present invention Figure；

Fig. 6 is the output voltage temperature of the band-gap reference reference circuit of the high PSRR source compensated by using high-order curvature of the present invention Characteristic Simulation figure；

Fig. 7 is the output voltage power supply of the band-gap reference reference circuit of the high PSRR source compensated by using high-order curvature of the present invention Rejection ratio analogous diagram.

Detailed description of the invention

The embodiment of the present application is by providing the band-gap reference reference circuit of a kind of high PSRR source compensated by using high-order curvature, energy Enough it is substantially reduced output voltage temperature coefficient, improves output voltage PSRR, thus obtain high-precision reference voltage.

In order to be better understood from technique scheme, below in conjunction with Figure of description and specific embodiment, right Technique scheme is described in detail.

Embodiment

The band-gap reference reference circuit of a kind of high PSRR source compensated by using high-order curvature, as in figure 2 it is shown, include start-up circuit 1, front regulator circuit 2, band-gap reference circuit 3, low-temperature region piecewise linearity temperature-compensation circuit 4, high-temperature area and definitely temperature Degree T^1.5The temperature-compensation circuit 5 that is directly proportional, high-temperature area piecewise linearity temperature-compensation circuit 6；

The enabling signal outfan of wherein said start-up circuit 1 connects described front regulator circuit 2, band-gap reference circuit respectively 3, low-temperature region piecewise linearity temperature-compensation circuit 4, high-temperature area and absolute temperature T^1.5The temperature-compensation circuit 5 being directly proportional with And the enabling signal input of high-temperature area piecewise linearity temperature-compensation circuit 6, the signal output part of described band-gap reference circuit 3 Connect described front regulator circuit 2, low-temperature region piecewise linearity temperature-compensation circuit 4, high-temperature area and absolute temperature T respectively^1.5Become The temperature-compensation circuit 5 of direct ratio and the signal input part of high-temperature area piecewise linearity temperature-compensation circuit 6, described front adjustor The voltage signal output end of circuit 2 connects described band-gap reference circuit 3, low-temperature region piecewise linearity temperature-compensation circuit 4, height respectively Temperature area and absolute temperature T^1.5The temperature-compensation circuit 5 being directly proportional and the work of high-temperature area piecewise linearity temperature-compensation circuit 6 Making power voltage input terminal, the output voltage signal of described band-gap reference circuit 3 connects the voltage signal input of described start-up circuit 1 End；

Described start-up circuit 1 makes band-gap reference reference circuit normally work, produce bandgap voltage reference output, described before Regulator circuit 2 is for improving the PSRR of band-gap reference reference circuit, the output voltage of described front regulator circuit 2 V_REGAs described band-gap reference circuit 3, low-temperature region piecewise linearity temperature-compensation circuit 4, high-temperature area and absolute temperature T^1.5 The temperature-compensation circuit 5 being directly proportional and the working power voltage of high-temperature area piecewise linearity temperature-compensation circuit 6, described band gap Reference circuit 3 produces the band gap reference voltage of low-temperature coefficient: positive temperature coefficient voltage V_PTATWith negative temperature coefficient voltage V_CTAT, Described low-temperature region piecewise linearity temperature-compensation circuit 4 produces low-temperature space and has piecewise linear voltage V_{PC_Low}, described high-temperature region Territory and absolute temperature T^1.5The temperature-compensation circuit 5 being directly proportional produces and absolute temperature T^1.5The voltage being directly proportionalDescribed height Temperature area piecewise linearity temperature-compensation circuit 6 produces high-temperature region and has piecewise linear voltage V_{PC_High}, described low-temperature region divides Section linear temperature compensation circuit 4, high-temperature area and absolute temperature T^1.5The temperature-compensation circuit 5 being directly proportional and high-temperature area divide Section linear temperature compensation circuit 6 is for carrying out temperature-compensating to described band-gap reference circuit 3, it may be assumed that low-temperature space is had segmented line The voltage V of property_{PC_Low}, and absolute temperature T^1.5The voltage being directly proportionalJoin the bandgap reference that band-gap reference circuit 3 produces In voltage, and pump except high-temperature region has piecewise linear voltage from the bandgap voltage reference that band-gap reference circuit produces V_{PC_High}。

Start-up circuit 1 only plays a role when band-gap reference reference circuit powers on, when band-gap reference reference circuit has started After one-tenth, start-up circuit 1 quits work, it is to avoid the start-up circuit 1 impact on circuit below.

As the preferred technical scheme of one, as it is shown on figure 3, described start-up circuit 1 includes: PMOS Ms1, PMOS Ms2, NMOS tube Ms3, NMOS tube Ms4, NMOS tube Ms5, NMOS tube Ms6 and NMOS tube Ms7, the wherein source electrode of PMOS Ms1 Being connected with external power source VDD, the grid of PMOS Ms1 is connected with the source electrode of the drain electrode of PMOS Ms1 and PMOS Ms2, The grid of PMOS Ms2 and the drain electrode of PMOS Ms2, the drain electrode of NMOS tube Ms3, the grid of NMOS tube Ms4, NMOS tube Ms5 The grid of grid, the grid of NMOS tube Ms6 and NMOS tube Ms7 is connected, the source electrode of NMOS tube Ms3 and the source electrode of NMOS tube Ms4, The source electrode of NMOS tube Ms5, the source electrode of NMOS tube Ms6, the source electrode of NMOS tube Ms7 and outside ground wire GND are connected；

Described front regulator circuit 2 includes: PMOS M1, PMOS M2, NMOS tube M3, NMOS tube M4, PMOS M5, NMOS tube M6, NMOS tube M7 and PMOS M8, wherein the source electrode of PMOS M1 is connected with external power source VDD, PMOS M1 Grid is connected with the drain electrode of drain electrode, the grid of PMOS M2, the drain electrode of NMOS tube Ms4 and NMOS tube M3 of PMOS M1, The grid of NMOS tube M3 and the grid of NMOS tube M6, the grid of NMOS tube M7, the drain electrode of NMOS tube M7 and the leakage of PMOS M8 The most connected, the source electrode of NMOS tube M3 and the source electrode of NMOS tube M4, the source electrode of NMOS tube M6, the source electrode of NMOS tube M7 and externally Line GND is connected, and the source electrode of PMOS M2 is connected with external power source VDD, the drain electrode of PMOS M2 and the drain electrode of NMOS tube M4, PMOS The source electrode of pipe M5, the source electrode of PMOS M8, the source electrode of PMOS M9, the source electrode of PMOS M10, the source electrode of PMOS M11, PMOS The source electrode of pipe M12, the source electrode of PMOS M17, the source electrode of PMOS M18, the source electrode of PMOS M19, the source electrode of PMOS M20, The source electrode of PMOS M26, the source electrode of PMOS M27, the source electrode of PMOS M25, the source electrode of PMOS M28, the source of PMOS M31 The source electrode of pole, the source electrode of PMOS M32, the source electrode of PMOS M33, the source electrode of PMOS M36 and PMOS M37 is connected, The drain electrode of PMOS M5 is connected with the drain electrode of the grid of NMOS tube M4 and NMOS tube M6；

Described band-gap reference circuit 3 includes: PMOS M9, PMOS M10, PMOS M11, PMOS M36, PMOS M37, error amplifier A1, error amplifier A2, PNP type triode Q1, PNP type triode Q2, resistance R1, resistance R2 and electricity Resistance R3, the wherein drain electrode of the PMOS M9 reverse input end with error amplifier A1 and the emitter stage phase of PNP type triode Q1 Even, the grid of PMOS M9 and the grid of PMOS M10, the outfan of error amplifier A1, the drain electrode of NMOS tube Ms5, PMOS The grid of pipe M8, the grid of PMOS M12, the grid of PMOS M20, the grid of PMOS M28 and the grid of PMOS M36 It is connected, the drain electrode of PMOS M10 and the grid of PMOS M5, the positive input of error amplifier A1, error amplifier A2 Reverse input end and resistance R1 are connected, and the other end of resistance R1 is connected with the emitter stage of PNP type triode Q2, positive-negative-positive three pole The base stage of pipe Q1 and the colelctor electrode of PNP type triode Q1, the base stage of PNP type triode Q2, PNP type triode Q2 colelctor electrode with And outside ground wire GND is connected, the grid of PMOS M11 and the outfan of error amplifier A2, the drain electrode of NMOS tube Ms6, PMOS The grid of the grid of pipe M17, the grid of PMOS M31 and PMOS M37 is connected, and the drain electrode of PMOS M11 is amplified with error The positive input of device A2 and resistance R2 are connected, and the other end of resistance R2 is connected with outside ground wire GND, the leakage of PMOS M36 Pole and the drain electrode of PMOS M37, the grid of NMOS tube Ms3, the drain electrode of PMOS M19, the drain electrode of PMOS M25, NMOS tube M35 Drain electrode, the outfan V of band-gap reference reference circuit_REFAnd resistance R3 is connected, the other end of resistance R3 and outside ground wire GND It is connected；

Described low-temperature region piecewise linearity temperature-compensation circuit 4 includes: PMOS M12, NMOS tube M13, NMOS tube M14, NMOS tube M15, NMOS tube M16, PMOS M17, PMOS M18 and PMOS M19, wherein the drain electrode of PMOS M12 with The grid of the drain electrode of NMOS tube M13, the grid of NMOS tube M13 and NMOS tube M14 is connected, the drain electrode of PMOS M17 and NMOS The grid of the drain electrode of pipe M14, the drain electrode of NMOS tube M15, the grid of NMOS tube M15 and NMOS tube M16 is connected, PMOS M18 Drain electrode be connected with the drain electrode of the grid of PMOS M18, the grid of PMOS M19 and NMOS tube M16, the source of NMOS tube M13 Pole is connected with the source electrode of NMOS tube M14, the source electrode of NMOS tube M15, the source electrode of NMOS tube M16 and outside ground wire GND；

Described high-temperature area and absolute temperature T^1.5The temperature-compensation circuit 5 being directly proportional includes: PMOS M20, NMOS tube M21, NMOS tube M22, NMOS tube M23, NMOS tube M24, PMOS M25, PMOS M26 and PMOS M27, wherein PMOS The drain electrode of M20 is connected with the grid of the drain electrode of NMOS tube M21, the grid of NMOS tube M21 and NMOS tube M22, PMOS M26 Drain electrode and the grid of PMOS M26, the grid of PMOS M27, the grid of PMOS M25, the drain electrode of NMOS tube Ms7 and NMOS The drain electrode of pipe M23 is connected, the grid of NMOS tube M23 and the grid of NMOS tube M24, the drain electrode of NMOS tube M24 and PMOS M27 Drain electrode be connected, the source electrode of NMOS tube M23 is connected with the drain electrode of NMOS tube M22, the source electrode of NMOS tube M21 and NMOS tube M22 Source electrode, the source electrode of NMOS tube M24 and outside ground wire GND are connected；

Described high-temperature area piecewise linearity temperature-compensation circuit 6 includes: PMOS M28, NMOS tube M29, NMOS tube M30, PMOS M31, PMOS M32, PMOS M33, NMOS tube M34 and NMOS tube M35, wherein the drain electrode of PMOS M28 with The grid of the drain electrode of NMOS tube M29, the grid of NMOS tube M29 and NMOS tube M30 is connected, the drain electrode of PMOS M31 and PMOS The drain electrode of the drain electrode of pipe M32, the grid of PMOS M32, the grid of PMOS M33 and NMOS tube M30 is connected, PMOS M33 Drain electrode be connected with the grid of the drain electrode of NMOS tube M34, the grid of NMOS tube M34 and NMOS tube M35, the source of NMOS tube M29 Pole is connected with the source electrode of NMOS tube M30, the source electrode of NMOS tube M34, the source electrode of NMOS tube M35 and outside ground wire GND.

Error amplifier A1 and error amplifier A2 in described band-gap reference circuit 3 are prior aries.

Error amplifier A1 makes the voltage of input node A of error amplifier and input node B equal, i.e. V_A=V_B= V_EB1, wherein, V_EB1It it is the emitter base voltage of PNP type triode Q1.

PMOS M9 and PMOS M10 have identical breadth length ratio, then the drain current I of PMOS M10₁₀For:

$I_{10}=\frac{kT}{{\mathrm{qR}}_1}\ln N---\left(1\right)$

In formula, N is the ratio of the PNP type triode Q2 emitter area with PNP type triode Q1, and k is Boltzmann constant, T is absolute temperature, and q is electron charge, and all of resistance is all that identical material realizes.Formula (1) illustrates the leakage of PMOS M10 Electrode current I₁₀There is positive temperature characterisitic.

Error amplifier A2 makes input node B of error amplifier A1 and the electricity of input node C of error amplifier A2 Press equal, i.e. V_B=V_C=V_EB1, input node B of described error amplifier A1 is the input joint of described error amplifier A2 simultaneously Point, then the drain current I of PMOS M11₁₁For:

$I_{11}=\frac{V_{EB1}}{R_2}---\left(2\right)$

From formula (2), the drain current I of PMOS M11₁₁There is negative temperature characteristic.

The present invention is for compensating V_EB1The temperature high-order nonlinear item of low-temperature region, uses low-temperature region piecewise linearity temperature to mend Repay circuit 4.The breadth length ratio of PMOS M12 is the β of PMOS M10₁Times, NMOS tube M13 and NMOS tube M14 have identical wide length Ratio, then the drain current I of NMOS tube M14₁₄For:

$I_{14}={\mathrm{\&beta;}}_1\frac{kT}{{\mathrm{qR}}_1}\ln N---\left(3\right)$

The breadth length ratio of PMOS M17 is the β of PMOS M11₂Times, then the drain current I of PMOS M17₁₇For:

$I_{17}={\mathrm{\&beta;}}_2\frac{V_{EB1}}{R_2}---\left(4\right)$

From formula (3), (4), in reference temperature T_r1Under, by parameters optimization β₁With β₂, there is a following relation:

I₁₄=I₁₇ (5)

From Kirchhoff's current law (KCL), the drain current I of NMOS tube M15₁₅For:

I₁₅=I₁₇-I₁₄ (6)

NMOS tube M15 and NMOS tube M16 have identical breadth length ratio, and the wide length of PMOS M19 is the β of PMOS M18₃ Times, then the drain current I of PMOS M19₁₉For:

$I_{19}=\left\{\begin{array}{cc}{\mathrm{\&beta;}}_3({\mathrm{\&beta;}}_2\frac{V_{EB1}}{R_2}-{\mathrm{\&beta;}}_1\frac{kT}{{\mathrm{qR}}_1}\ln N)& T<T_{r1}\\ 0& T\&GreaterEqual;T_{r1}\end{array}\right.---\left(7\right)$

From formula (7), the drain current I of PMOS M19₁₉At low-temperature space, there is temperature section linear characteristic.

The present invention is for compensating V_EB1The temperature high-order nonlinear item of high-temperature area, use high-temperature area and absolute temperature T^1.5 The temperature-compensation circuit 5 being directly proportional.PMOS M20 and PMOS M10 have identical breadth length ratio, PMOS M26 and PMOS M27 has identical breadth length ratio, and the breadth length ratio of PMOS M25 is the β of PMOS M26₈Times, NMOS tube M21, PMOS M20, PMOS M26, PMOS M27 and PMOS M25 are all operated in saturation region, and NMOS tube M22 is operated in deep linear zone, NMOS tube M23 and NMOS tube M24 are operated in sub-threshold region, and the breadth length ratio of NMOS tube M23 is the β of NMOS tube M24₇Times, then PMOS M25 Drain current I₂₅For:

$I_{25}\&ap;{\mathrm{n\&beta;}}_8{\left(\frac{W}{L}\right)}_{22}\sqrt{2{\mathrm{\&mu;}}_n{C}_{ox}\ln N}\frac{ln\left({\mathrm{\&beta;}}_7\right)}{\sqrt{R_1{\left(\frac{W}{L}\right)}_{21}}}\frac{k^{1.5}}{q^{1.5}}{T}^{1.5}---\left(8\right)$

In formula, n is the non-ideal factor more than 1,It is the breadth length ratio of NMOS tube M22,It it is NMOS tube The breadth length ratio of M21, μ_nIt is electron mobility, C_oxIt is unit are gate oxide capacitance, from formula (8), the leakage of PMOS M25 Electrode current I₂₅With absolute temperature T^1.5It is directly proportional.

Meanwhile, the present invention is for compensating V_EB1The temperature high-order nonlinear item of high-temperature area, use high-temperature area piecewise linearity Temperature-compensation circuit 6.The breadth length ratio of PMOS M28 is the β of PMOS M10₄, NMOS tube M29 and NMOS tube M30 have identical Breadth length ratio, then the drain current I of NMOS tube M30₃₀For:

$I_{30}={\mathrm{\&beta;}}_4\frac{kT}{{\mathrm{qR}}_1}\ln N---\left(9\right)$

PMOS M31 is the β of PMOS M11₅, then the drain current I of PMOS M31₃₁For:

$I_{31}={\mathrm{\&beta;}}_5\frac{V_{EB1}}{R_2}---\left(10\right)$

From formula (9), (10), in reference temperature T_r2(T_r2>>T_r1Under), by parameters optimization by optimizing β₄And β₅, have Following relation:

I₃₀=I₃₁ (11)

PMOS M32 and PMOS M33 have identical breadth length ratio, and the breadth length ratio of NMOS tube M35 is the β of NMOS tube M34₆ Times, then the drain current I of NMOS tube M35₃₅For:

$I_{35}=\left\{\begin{array}{cc}{\mathrm{\&beta;}}_6({\mathrm{\&beta;}}_4\frac{kT}{{\mathrm{qR}}_1}\ln m-{\mathrm{\&beta;}}_5\frac{V_{EB1}}{R_2})& T>T_{r2}\\ 0& T\&le;T_{r2}\end{array}\right.---\left(12\right)$

From formula (12), the drain current I of NMOS tube M35₃₅There is temperature section linear characteristic in high-temperature region.

The breadth length ratio of PMOS M36 is the β of PMOS M10₉Times, the breadth length ratio of PMOS M37 is the β of PMOS M11₁₀ Times, from formula (1), (2), (7), (8), (12), the band-gap reference reference circuit that high PSRR is high-order temperature compensated Output voltage V_REFFor:

$V_{REF}=V_{PTAT}+V_{CTAT}+V_{PC\_Low}+V_{{\mathrm{PTAT}}^{3/2}}-V_{PC\_High}---\left(13\right)$

Wherein,

$V_{PTAT}={\mathrm{\&beta;}}_9\frac{R_{3}kT}{R_{1}q}\ln N---\left(14\right)$

$V_{CTAT}={\mathrm{\&beta;}}_{10}\frac{R_3{V}_{EB1}}{R_2}---\left(15\right)$

$V_{PC\_Low}=\left\{\begin{array}{cc}{\mathrm{\&beta;}}_3{R}_3({\mathrm{\&beta;}}_2\frac{V_{EB1}}{R_2}-{\mathrm{\&beta;}}_1\frac{kT}{{\mathrm{qR}}_1}\ln m)& T\&le;T_{r1}\\ 0& T>T_{r1}\end{array}\right.---\left(16\right)$

$V_{{\mathrm{PTAT}}^{3/2}}={\mathrm{n\&beta;}}_8{\left(\frac{W}{L}\right)}_{22}\sqrt{2{\mathrm{\&mu;}}_n{C}_{ox}\ln N}\frac{ln\left({\mathrm{\&beta;}}_7\right)}{\sqrt{R_1{\left(\frac{W}{L}\right)}_{21}}}\frac{k^{1.5}}{q^{1.5}}{T}^{1.5}\&times;R_3---\left(17\right)$

$V_{PC\_High}=\left\{\begin{array}{cc}0& T\&le;T_{r2}\\ {\mathrm{\&beta;}}_6{R}_3({\mathrm{\&beta;}}_4\frac{kT}{{\mathrm{qR}}_1}\ln m-{\mathrm{\&beta;}}_5\frac{V_{EB1}}{R_2})& T>T_{r2}\end{array}\right.---\left(18\right)$

From formula (14), V_PTATIt is the voltage of a positive temperature coefficient, the V in formula (15)_EB1It it is PNP type triode Q1 Emitter base voltage, thereby through the parameter beta in optimized-type (14), (15)₉、β₁₀, N and resistance R₁、R₂、R₃, it is achieved Single order temperature-compensating, obtains single order bandgap voltage reference, i.e. available bandgap voltage reference curve as shown in Figure 4.

It is true that V_EB1There is high-order nonlinear temperature item, from Fig. 4 and formula (14), (15), V_PTATOnly offset V_EB1 The first order of temperature T, it is therefore desirable to carrying out high-order temperature compensated, the present invention, on single order band-gap reference reference circuit basis One low-temperature space piecewise linearity temperature-compensation circuit (4) of upper introducing, high-temperature region and absolute temperature T^1.5The temperature-compensating electricity being directly proportional Road (5) and high-temperature region piecewise linearity temperature-compensation circuit (6), solve the problem that single order band-gap reference reference circuit exists. From formula (16), voltage V_{PC_Low}It is one, at low-temperature space, there is piecewise linear voltage, from formula (17), voltage It is one and temperature T^1.5The voltage being directly proportional, simultaneously from formula (18), voltage V_{PC_High}It is one, in high-temperature region, there is segmentation Linear voltage, thus by V_{PC_Low}、With V_{PC_High}Three voltages are incorporated in single order band-gap reference reference circuit, can be effective Compensation V_EB1In the higher order term of temperature T, obtain high-order temperature compensation bandgap reference voltage, i.e. can get band gap base shown in Fig. 5 Quasi-voltage curve.

From formula (13), (14), (15), (16), (17), (18) and Fig. 5, the high PSRR high-order of the present invention The output voltage V of the band-gap reference reference circuit of temperature-compensating_REFTemperature characteristics can be divided into following four regions:

Region 1, temperature T is less than reference temperature T_r1, i.e. T ＜ T_r1.In this region,Have insignificant little, V_{PC_High}It is zero, the output voltage V of band-gap reference reference circuit_REFBy V_{PC_Low}、V_CTATAnd V_PTATContribution, then band-gap reference reference The output voltage V of circuit_REFFor:

V_REF=V_CTAT+V_PTAT+V_{PC_Low} (19)

Region 2, temperature T is more than reference temperature T_r1, less than reference temperature T_a, i.e. T_r1＜ T ＜ T_a, T here_aIt is with reference to temperature Degree, and have T_r1＜ T_a＜ T_r2Relation, in this region,Have insignificant little, V_{PC_Low}It is zero, V simultaneously_{PC_High}Also it is Zero, the output voltage V of band-gap reference reference circuit_REFBy V_CTATAnd V_PTATContribution, then the output voltage of band-gap reference reference circuit V_REFFor:

V_REF=V_PTAT+V_{PC_Low} (20)

Region 3, temperature T is more than reference temperature T_a, less than reference temperature T_r2, i.e. T_a＜ T ＜ T_r2, this region, V_{PC_Low}For Zero, V simultaneously_{PC_High}Also it is zero, the output voltage V of band-gap reference reference circuit_REFBy V_CTAT、V_PTATAndContribution, then band gap The output voltage V of reference circuit_REFFor:

$V_{REF}=V_{CTAT}+V_{PTAT}+V_{{\mathrm{PTAT}}^{3/2}}---\left(21\right)$

Region 4, temperature T is more than reference temperature T_r2, i.e. T ＞ T_r2, this region, V_{PC_Low}It is zero, band-gap reference reference circuit Output voltage V_REFBy V_CTAT、V_PTAT、And V_{PC_High}Contribution, then the output voltage V of band-gap reference reference circuit_REFFor:

$V_{\mathrm{REF}}=V_{\mathrm{CTAT}}+V_{\mathrm{PTAT}}+V_{{\mathrm{PTAT}}^{3/2}}-V_{\mathrm{PC}\_\mathrm{High}}---\left(22\right)$

Fig. 6 is the output voltage V of the high-order temperature compensated band-gap reference reference circuit of the high PSRR of the present invention_REF Temperature characterisitic simulation curve, wherein abscissa is temperature, and vertical coordinate is band-gap reference output voltage.Simulation result shows, Temperature range is-55 DEG C～140 DEG C, and the high-order temperature compensated band-gap reference reference circuit of this high PSRR reaches The temperature coefficient of 7.78ppm/ DEG C.

For improving band-gap reference output voltage V_REFPSRR, use before regulator circuit 2, front regulator circuit 2 Output voltage be band-gap reference circuit 3, low-temperature region piecewise linearity temperature-compensation circuit 4, high-temperature area and absolute temperature T^1.5 The temperature-compensation circuit 5 being directly proportional and the working power voltage of high-temperature area piecewise linearity temperature-compensation circuit 6.Work as external electrical Source VDD has a fluctuation voltage v_ddTime, the drain electrode of PMOS M2 has a fluctuation voltage v_reg, then the grid of PMOS M10 has a fluctuation Voltage v_d, the drain electrode of PMOS M10 has a fluctuation voltage v_b.The grid fluctuation voltage v of PMOS M10_dIt is input to PMOS M8 grid Pole, the drain electrode fluctuation voltage v of PMOS M10_bIt is input to the grid of PMOS M5, simultaneously PMOS M5, PMOS M8, NMOS tube M6, NMOS tube M7 constitute difference amplifier, and the output voltage of this difference amplifier is input to the grid of NMOS tube M4, then NMOS tube M4 forces the drain voltage of PMOS M2 to return to correct magnitude of voltage, thus improves band-gap reference output voltage V_REFPower supply suppression Ratio.Fig. 7 is the PSRR emulation song of the high-order temperature compensated band-gap reference reference circuit of the high PSRR of the present invention Line, wherein abscissa is frequency, and vertical coordinate is the PSRR of band-gap reference output voltage.Simulation result shows, the present invention The high-order temperature compensated bandgap voltage reference of high PSRR obtain respectively at 1Hz, 100Hz, 100kHz and 1MHz frequency Obtain-123.51dB ,-123.52dB ,-88.5dB and the PSRR of-50.23dB.

Here, when start-up circuit 1 starts, due to band-gap reference output voltage V_REFComparing relatively low, NMOS tube Ms3 is ended, The grid potential making NMOS tube Ms4, NMOS tube Ms5, NMOS tube Ms6 and NMOS tube Ms7 is high potential, so that PMOS M2, PMOS M8, PMOS M9, PMOS M10, PMOS M11, PMOS M12, PMOS M17, PMOS M20, PMOS M26, PMOS M27, PMOS M25, PMOS M28, PMOS M31, PMOS M36, the grid of PMOS M23 are low electricity Position, this is formed for PMOS M2 to PMOS M9 to PNP type triode Q1, PMOS M2 to PMOS M10 to PNP type triode Q2, PMOS M2 are to PMOS M11 to resistance R2, the current path of PMOS M2 to PMOS M27 to NMOS tube M24 so that Circuit departs from zero state, enters duty.But, V_REFWhen rising to more than NMOS threshold voltage, NMOS tube Ms1 turns on, and makes The grid obtaining NMOS tube Ms4, NMOS tube Ms5, NMOS tube Ms6 and NMOS tube Ms7 is electronegative potential and is operated in cut-off region so that open Galvanic electricity road 1 no longer produces impact to band-gap reference reference circuit below, and startup completes.

In above-described embodiment of the application, by providing the band-gap reference of a kind of high PSRR source compensated by using high-order curvature to join Examine circuit, by by low-temperature region piecewise linearity temperature-compensated current I₁₉, high-temperature area and absolute temperature T^1.5The temperature being directly proportional Compensate electric current I₂₅Join in traditional single order band-gap reference reference circuit, and take away from conventional first order band-gap reference reference circuit High-temperature area piecewise linearity temperature-compensated current I₃₅, will PMOS M19 in low-temperature region piecewise linearity temperature-compensation circuit 4 Leakage current I₁₉With high-temperature area and absolute temperature T^1.5The leakage current of PMOS M25 in the temperature-compensation circuit 5 being directly proportional I₂₅Join on resistance R3, at the outfan V of band-gap reference reference circuit_REFIn take away and flow through high-temperature area piecewise linearity temperature The leakage current I of NMOS tube M35 in compensation circuit 6₃₅, thus obtain the reference voltage of source compensated by using high-order curvature, use this technology can Obtain the reference voltage of less temperature coefficient；Adjustor technology before one negative feedback is also joined band-gap reference reference by the present invention In circuit, will before the output voltage V of regulator circuit 2_REGMend as band-gap reference circuit 3, low-temperature region piecewise linearity temperature Repay circuit 4, high-temperature area and absolute temperature T^1.5The temperature-compensation circuit 5 being directly proportional and high-temperature area piecewise linearity temperature are mended Repay the working power voltage of circuit 6, obtain the band-gap reference reference circuit of high PSRR source compensated by using high-order curvature.

It should be pointed out that, described above is not limitation of the present invention, the present invention is also not limited to the example above, Change, modification that those skilled in the art are made in the essential scope of the present invention, add or replace, also should Belong to protection scope of the present invention.

Claims (6)

1. the band-gap reference reference circuit of a high PSRR source compensated by using high-order curvature, it is characterised in that include start-up circuit (1), front regulator circuit (2), band-gap reference circuit (3), low-temperature region piecewise linearity temperature-compensation circuit (4), high-temperature area With absolute temperature T^1.5The temperature-compensation circuit (5) that is directly proportional, high-temperature area piecewise linearity temperature-compensation circuit (6)；

The enabling signal outfan of wherein said start-up circuit (1) connects described front regulator circuit (2), band-gap reference circuit respectively (3), low-temperature region piecewise linearity temperature-compensation circuit (4), high-temperature area and absolute temperature T^1.5The temperature-compensation circuit being directly proportional (5) and the enabling signal input of high-temperature area piecewise linearity temperature-compensation circuit (6), described band-gap reference circuit (3) Signal output part connects described front regulator circuit (2), low-temperature region piecewise linearity temperature-compensation circuit (4), high-temperature area respectively With absolute temperature T^1.5The temperature-compensation circuit (5) being directly proportional and the signal of high-temperature area piecewise linearity temperature-compensation circuit (6) Input, the voltage signal output end of described front regulator circuit (2) connects described band-gap reference circuit (3), low-temperature region respectively Piecewise linearity temperature-compensation circuit (4), high-temperature area and absolute temperature T^1.5The temperature-compensation circuit (5) being directly proportional and high temperature The working power voltage input of area segmentation linear temperature compensation circuit (6), the output voltage of described band-gap reference circuit (3) Signal connects the voltage signal inputs of described start-up circuit (1)；

Described start-up circuit (1) makes band-gap reference reference circuit normally work, and produces bandgap voltage reference output, described front tune Whole device circuit (2) is for improving the PSRR of band-gap reference reference circuit, the output voltage of described front regulator circuit (2) V_REGAs described band-gap reference circuit (3), low-temperature region piecewise linearity temperature-compensation circuit (4), high-temperature area and absolute temperature T^1.5The temperature-compensation circuit (5) being directly proportional and the working power voltage of high-temperature area piecewise linearity temperature-compensation circuit (6), The band gap reference voltage of described band-gap reference circuit (3) generation low-temperature coefficient: positive temperature coefficient voltage V_PTATWith negative temperature system Number voltage V_CTAT, described low-temperature region piecewise linearity temperature-compensation circuit (4) produces low-temperature space and has piecewise linear voltage V_{PC_Low}, described high-temperature area and absolute temperature T^1.5The temperature-compensation circuit (5) being directly proportional produces and absolute temperature T^1.5It is directly proportional VoltageDescribed high-temperature area piecewise linearity temperature-compensation circuit (6) produces high-temperature region and has piecewise linear voltage V_{PC_High}, described low-temperature region piecewise linearity temperature-compensation circuit (4), high-temperature area and absolute temperature T^1.5The temperature being directly proportional Compensate circuit (5) and high-temperature area piecewise linearity temperature-compensation circuit (6) for described band-gap reference circuit (3) is carried out temperature Degree compensates, it may be assumed that low-temperature space has piecewise linear voltage V_{PC_Low}, and absolute temperature T^1.5The voltage being directly proportionalAdd In the band gap reference voltage that band-gap reference circuit (3) produces, and take out from the bandgap voltage reference that band-gap reference circuit produces Remove high-temperature region and there is piecewise linear voltage V_{PC_High}。

The band-gap reference reference circuit of high PSRR source compensated by using high-order curvature the most according to claim 1, its feature exists In,

Described start-up circuit (1) including: PMOS Ms1, PMOS Ms2, NMOS tube Ms3, NMOS tube Ms4, NMOS tube Ms5, NMOS tube Ms6 and NMOS tube Ms7, wherein the source electrode of PMOS Ms1 is connected with external power source VDD, the grid of PMOS Ms1 with The drain electrode of PMOS Ms1 and the source electrode of PMOS Ms2 are connected, the grid of PMOS Ms2 and the drain electrode of PMOS Ms2, NMOS The drain electrode of pipe Ms3, the grid of NMOS tube Ms4, the grid of NMOS tube Ms5, the grid of NMOS tube Ms6 and the grid of NMOS tube Ms7 The most connected, the source electrode of NMOS tube Ms3 and the source electrode of NMOS tube Ms4, the source electrode of NMOS tube Ms5, the source electrode of NMOS tube Ms6, NMOS Source electrode and the outside ground wire GND of pipe Ms7 are connected；

Described front regulator circuit (2) including: PMOS M1, PMOS M2, NMOS tube M3, NMOS tube M4, PMOS M5, NMOS Pipe M6, NMOS tube M7 and PMOS M8, wherein the source electrode of PMOS M1 is connected with external power source VDD, the grid of PMOS M1 The drain electrode of drain electrode, the grid of PMOS M2, the drain electrode of NMOS tube Ms4 and NMOS tube M3 with PMOS M1 is connected, NMOS tube The grid of M3 is connected with the drain electrode of the grid of NMOS tube M6, the grid of NMOS tube M7, the drain electrode of NMOS tube M7 and PMOS M8, The source electrode of NMOS tube M3 and the source electrode of NMOS tube M4, the source electrode of NMOS tube M6, the source electrode of NMOS tube M7 and outside ground wire GND phase Even, the source electrode of PMOS M2 is connected with external power source VDD, the drain electrode of PMOS M2 and the drain electrode of NMOS tube M4, PMOS M5 Source electrode, the source electrode of PMOS M8, the source electrode of PMOS M9, the source electrode of PMOS M10, the source electrode of PMOS M11, PMOS M12 Source electrode, the source electrode of PMOS M17, the source electrode of PMOS M18, the source electrode of PMOS M19, the source electrode of PMOS M20, PMOS The source electrode of M26, the source electrode of PMOS M27, the source electrode of PMOS M25, the source electrode of PMOS M28, the source electrode of PMOS M31, The source electrode of the source electrode of PMOS M32, the source electrode of PMOS M33, the source electrode of PMOS M36 and PMOS M37 is connected, PMOS The drain electrode of M5 is connected with the drain electrode of the grid of NMOS tube M4 and NMOS tube M6；

Described band-gap reference circuit (3) including: PMOS M9, PMOS M10, PMOS M11, PMOS M36, PMOS M37, Error amplifier A1, error amplifier A2, PNP type triode Q1, PNP type triode Q2, resistance R1, resistance R2 and resistance R3, wherein the drain electrode of PMOS M9 is connected with the reverse input end of error amplifier A1 and the emitter stage of PNP type triode Q1, The grid of PMOS M9 and the grid of PMOS M10, the outfan of error amplifier A1, the drain electrode of NMOS tube Ms5, PMOS M8 The grid phase of grid, the grid of PMOS M12, the grid of PMOS M20, the grid of PMOS M28 and PMOS M36 Even, the drain electrode of PMOS M10 and the grid of PMOS M5, the positive input of error amplifier A1, error amplifier A2 anti- Being connected to input and resistance R1, the other end of resistance R1 is connected with the emitter stage of PNP type triode Q2, PNP type triode The base stage of Q1 and the colelctor electrode of PNP type triode Q1, the base stage of PNP type triode Q2, the colelctor electrode of PNP type triode Q2 and Outside ground wire GND is connected, the grid of PMOS M11 and the outfan of error amplifier A2, the drain electrode of NMOS tube Ms6, PMOS The grid of the grid of M17, the grid of PMOS M31 and PMOS M37 is connected, the drain electrode of PMOS M11 and error amplifier The positive input of A2 and resistance R2 are connected, and the other end of resistance R2 is connected with outside ground wire GND, the drain electrode of PMOS M36 Drain electrode with PMOS M37, the grid of NMOS tube Ms3, the drain electrode of PMOS M19, the drain electrode of PMOS M25, NMOS tube M35 Drain electrode, the outfan V of band-gap reference reference circuit_REFAnd resistance R3 is connected, the other end of resistance R3 and outside ground wire GND phase Even；

Described low-temperature region piecewise linearity temperature-compensation circuit (4) including: PMOS M12, NMOS tube M13, NMOS tube M14, NMOS tube M15, NMOS tube M16, PMOS M17, PMOS M18 and PMOS M19, wherein the drain electrode of PMOS M12 with The grid of the drain electrode of NMOS tube M13, the grid of NMOS tube M13 and NMOS tube M14 is connected, the drain electrode of PMOS M17 and NMOS The grid of the drain electrode of pipe M14, the drain electrode of NMOS tube M15, the grid of NMOS tube M15 and NMOS tube M16 is connected, PMOS M18 Drain electrode be connected with the drain electrode of the grid of PMOS M18, the grid of PMOS M19 and NMOS tube M16, the source of NMOS tube M13 Pole is connected with the source electrode of NMOS tube M14, the source electrode of NMOS tube M15, the source electrode of NMOS tube M16 and outside ground wire GND；

Described high-temperature area and absolute temperature T^1.5The temperature-compensation circuit (5) being directly proportional including: PMOS M20, NMOS tube M21, NMOS tube M22, NMOS tube M23, NMOS tube M24, PMOS M25, PMOS M26 and PMOS M27, wherein PMOS M20 Drain electrode be connected with the grid of the drain electrode of NMOS tube M21, the grid of NMOS tube M21 and NMOS tube M22, the leakage of PMOS M26 Pole and the grid of PMOS M26, the grid of PMOS M27, the grid of PMOS M25, the drain electrode of NMOS tube Ms7 and NMOS tube The drain electrode of M23 is connected, the grid of NMOS tube M23 and the grid of NMOS tube M24, the drain electrode of NMOS tube M24 and PMOS M27 Drain electrode is connected, and the source electrode of NMOS tube M23 is connected with the drain electrode of NMOS tube M22, the source electrode of NMOS tube M21 and the source of NMOS tube M22 Pole, the source electrode of NMOS tube M24 and outside ground wire GND are connected；

Described high-temperature area piecewise linearity temperature-compensation circuit (6) including: PMOS M28, NMOS tube M29, NMOS tube M30, PMOS M31, PMOS M32, PMOS M33, NMOS tube M34 and NMOS tube M35, wherein the drain electrode of PMOS M28 with The grid of the drain electrode of NMOS tube M29, the grid of NMOS tube M29 and NMOS tube M30 is connected, the drain electrode of PMOS M31 and PMOS The drain electrode of the drain electrode of pipe M32, the grid of PMOS M32, the grid of PMOS M33 and NMOS tube M30 is connected, PMOS M33 Drain electrode be connected with the grid of the drain electrode of NMOS tube M34, the grid of NMOS tube M34 and NMOS tube M35, the source of NMOS tube M29 Pole is connected with the source electrode of NMOS tube M30, the source electrode of NMOS tube M34, the source electrode of NMOS tube M35 and outside ground wire GND.

The band-gap reference reference circuit of high PSRR source compensated by using high-order curvature the most according to claim 2, its feature exists In,

In described band-gap reference circuit (3), PMOS M9 and PMOS M10 have identical breadth length ratio, the drain electrode of PMOS M10 Electric current I₁₀For:In formula, k is Boltzmann constant, and T is absolute temperature, and q is electron charge, R₁For resistance R1 Resistance, N is the ratio of the PNP type triode Q2 emitter area with PNP type triode Q1；

The drain current I of PMOS M11₁₁For:In formula, V_EB1Emitter stage-base stage electricity for PNP type triode Q1 Pressure, R₂Resistance for resistance R2；

In described low-temperature region piecewise linearity temperature-compensation circuit (4), NMOS tube M13 and NMOS tube M14 have identical wide length Ratio, NMOS tube M15 and NMOS tube M16 have identical breadth length ratio, the drain current I of PMOS M19₁₉At low-temperature space, there is temperature Piece wire characteristic, to compensate the emitter base voltage V of PNP type triode Q1_EB1The temperature high-order nonlinear of low-temperature region ,

$I_{19}=\left\{\begin{array}{cc}{\mathrm{\&beta;}}_3({\mathrm{\&beta;}}_2\frac{V_{EB1}}{R_2}-{\mathrm{\&beta;}}_1\frac{kT}{{\mathrm{qR}}_1}lnN)& T<T_{r1}\\ 0& T\&GreaterEqual;T_{r1}\end{array}\right.$

In formula, β₁For the ratio of PMOS M12 with the breadth length ratio of PMOS M10, β₂Breadth length ratio for PMOS M17 Yu PMOS M11 Ratio, β₃For the ratio of PMOS M19 with the breadth length ratio of PMOS M18, V_EB1Emitter stage-base stage electricity for PNP type triode Q1 Pressure, R₁For the resistance of resistance R1, R₂For the resistance of resistance R2, k is Boltzmann constant, and T is absolute temperature, and q is electron charge, N It is the ratio of the PNP type triode Q2 emitter area with PNP type triode Q1, T_r1For reference temperature.

The band-gap reference reference circuit of high PSRR source compensated by using high-order curvature the most according to claim 2, its feature exists In, in described high-temperature area and absolute temperature T^1.5In the temperature-compensation circuit (5) being directly proportional, PMOS M20 has with PMOS M10 Having identical breadth length ratio, PMOS M26 and PMOS M27 to have identical breadth length ratio, the breadth length ratio of PMOS M25 is PMOS The β of M26₈Times, NMOS tube M21, PMOS M20, PMOS M26, PMOS M27 and PMOS M25 are all operated in saturation region, NMOS tube M22 is operated in deep linear zone, and NMOS tube M23 and NMOS tube M24 are operated in sub-threshold region, the breadth length ratio of NMOS tube M23 It is the β of NMOS tube M24₇Times, then the drain current I of PMOS M25₂₅For:

$I_{25}\&ap;{\mathrm{n\&beta;}}_8{\left(\frac{W}{L}\right)}_{22}\sqrt{2{\mathrm{\&mu;}}_n{C}_{ox}\ln N}\frac{\ln \left({\mathrm{\&beta;}}_7\right)}{\sqrt{R_1{\left(\frac{W}{L}\right)}_{21}}}\frac{k^{1.5}}{q^{1.5}}{T}^{1.5}$

In formula, n is the non-ideal factor more than 1, β₈It is the ratio of the PMOS M25 breadth length ratio with PMOS M26,It is The breadth length ratio of NMOS tube M22, μ_nIt is electron mobility, C_oxUnit are gate oxide capacitance, N be PNP type triode Q2 with The ratio of the emitter area of PNP type triode Q1, β₇It is the ratio of the NMOS tube M23 breadth length ratio with NMOS tube M24, R₁For resistance R1 Resistance,Being the breadth length ratio of NMOS tube M21, k is Boltzmann constant, and T is absolute temperature, and q is electron charge, PMOS The drain current I of pipe M25₂₅With absolute temperature T¹ _. ⁵It is directly proportional.

The band-gap reference reference circuit of high PSRR source compensated by using high-order curvature the most according to claim 2, its feature exists In, in described high-temperature area piecewise linearity temperature-compensation circuit (6), the breadth length ratio of PMOS M28 is the β of PMOS M10₄Times, NMOS tube M29 and NMOS tube M30 have identical breadth length ratio, and the breadth length ratio of PMOS M31 is the β of PMOS M11₅Times, PMOS Pipe M32 and PMOS M33 have identical breadth length ratio, and the breadth length ratio of NMOS tube M35 is the β of NMOS tube M34₆Times, NMOS tube M35 Drain current I₃₅There is temperature section linear characteristic in high-temperature region, to compensate the emitter base voltage of PNP type triode Q1 V_EB1The temperature high-order nonlinear item of high-temperature area,

$I_{35}=\left\{\begin{array}{cc}{\mathrm{\&beta;}}_6({\mathrm{\&beta;}}_4\frac{kT}{{\mathrm{qR}}_1}lnN-{\mathrm{\&beta;}}_5\frac{V_{EB1}}{R_2})& T>T_{r2}\\ 0& T\&le;T_{r2}\end{array}\right.$

In formula, β₆It is the ratio of the NMOS tube M35 breadth length ratio with NMOS tube M34, β₄It it is the breadth length ratio of PMOS M28 and PMOS M10 Ratio, k is Boltzmann constant, and T is absolute temperature, and q is electron charge, R₁For the resistance of resistance R1, N is PNP type triode The ratio of Q2 and the emitter area of PNP type triode Q1, β₅It is the ratio of the PMOS M31 breadth length ratio with PMOS M11, V_EB1For The emitter base voltage of PNP type triode Q1, R₂For the resistance of resistance R2, T_r2For reference temperature.

6. according to the band-gap reference of the high PSRR source compensated by using high-order curvature described in any claim in claim 2 to 5 Reference circuit, it is characterised in that the breadth length ratio of PMOS M36 is the β of PMOS M10₉Times, the breadth length ratio of PMOS M37 is The β of PMOS M11₁₀Times, the output voltage V of band-gap reference reference circuit_REFFor:

$V_{REF}=V_{PTAT}+V_{CTAT}+V_{PC\_Low}+V_{{\mathrm{PTAT}}^{3/2}}-V_{PC\_High}$

Wherein,

V_PTATFor positive temperature coefficient voltage,

V_CTATFor negative temperature coefficient voltage,

V_{PC_Low}For low-temperature space, there is piecewise linear voltage,

For with definitely temperature T¹ _. ⁵The voltage being directly proportional:

$V_{{\mathrm{PTAT}}^{3/2}}={\mathrm{n\&beta;}}_8{\left(\frac{W}{L}\right)}_{22}\sqrt{2{\mathrm{\&mu;}}_n{C}_{ox}\ln N}\frac{\ln \left({\mathrm{\&beta;}}_7\right)}{\sqrt{R_1{\left(\frac{W}{L}\right)}_{21}}}\frac{k^{1.5}}{q^{1.5}}{T}^{1.5}\&times;R_3;$

V_PC-HighFor high-temperature region, there is piecewise linear voltage,

In formula, β₉It is the ratio of the PMOS M36 breadth length ratio with PMOS M10, R₃Being the resistance of resistance R3, k is that Boltzmann is normal Number, T is absolute temperature, and q is electron charge, R₁For the resistance of resistance R1, N is PNP type triode Q2 and PNP type triode Q1 The ratio of emitter area, β₁₀It is the ratio of the PMOS M37 breadth length ratio with PMOS M11, V_EB1Transmitting for PNP type triode Q1 Pole-base voltage, R₂For the resistance of resistance R2, β₁For the ratio of PMOS M12 with the breadth length ratio of PMOS M10, β₂For PMOS The ratio of M17 and the breadth length ratio of PMOS M11, β₃For the ratio of PMOS M19 with the breadth length ratio of PMOS M18, T_r1For reference temperature, N is the non-ideal factor more than 1, β₈It is the ratio of the PMOS M25 breadth length ratio with PMOS M26,It it is NMOS tube The breadth length ratio of M22, μ_nIt is electron mobility, C_oxIt is unit are gate oxide capacitance, β₇It is NMOS tube M23 and NMOS tube M24 The ratio of breadth length ratio,Being the breadth length ratio of NMOS tube M21, k is Boltzmann constant, and T is absolute temperature, and q is electronics electricity Lotus, β₆It is the ratio of the NMOS tube M35 breadth length ratio with NMOS tube M34, β₄It is the ratio of the PMOS M28 breadth length ratio with PMOS M10, β₅It is the ratio of the PMOS M31 breadth length ratio with PMOS M11, T_r2For reference temperature.