CN105807838B - High-order temperature compensation bandgap reference circuit - Google Patents

Abstract

The invention provides a kind of high-order temperature compensation bandgap reference circuit, including start-up circuit, ambipolar band-gap reference circuit, piecewise linearity temperature-compensation circuit and Δ V_GSTemperature-compensation circuit, the start-up circuit causes high-order temperature compensation bandgap reference circuit normal work, the ambipolar band-gap reference circuit produces the band gap reference voltage of low-temperature coefficient, the temperature section linear compensation voltage and the Δ V that the piecewise linearity temperature-compensation circuit is produced_GSThe Δ V that temperature-compensation circuit is produced_GSTemperature-compensated voltage is added in the low temperature coefficient with gap reference voltage that the ambipolar band-gap reference circuit is produced, so as to obtain high-order temperature compensated reference voltage, significantly reduces the temperature coefficient of band-gap reference circuit output voltage.

Description

High-order temperature compensation bandgap reference circuit

Technical field

The present invention relates to microelectronics technology, and in particular to a kind of high-order temperature compensation bandgap reference circuit.

Background technology

Band-gap reference circuit is the basic module of many simulations and Digital Analog Hybrid Circuits system, and it is simulation and numerical model analysis Circuit system provides stable reference voltage, and its performance characteristics directly affects simulation and the performance of Digital Analog Hybrid Circuits system is special Property.

Fig. 1 gives a kind of traditional single order band-gap reference, and resistance R2 and R3 is just the same, and nmos pass transistor M1 and M2 has There is identical breadth length ratio, PNP type triode Q2 emitter area is α times of PNP type triode Q1 emitter area.PNP Type triode Q1 emitter base voltage V_EB1Reduced, resistance R2 both end voltage as temperature increasesWherein k is Boltzmann constant, and T is absolute temperature, and q is electron charge, R₁For resistance R1 resistance, R₂For resistance R2 resistance.According to principle of stacking, the voltage of the band-gap reference circuit output end VREF shown in Fig. 1In formula, V_EB1With negative temperature coefficient,With positive temperature coefficient, thus close Reason adjustment α, R₁And R₂Size, the band-gap reference reference voltage V of zero-temperature coefficient can be obtained in certain temperature range_REF。

However, due to PNP type triode emitter base voltage V_EBNonlinear temperature cause single order band-gap reference refer to Voltage has higher temperature coefficient, so as to constrain application of the single order band-gap reference circuit in High Definition Systems.

The content of the invention

The application can substantially reduce band-gap reference circuit defeated by providing a kind of high-order temperature compensation bandgap reference circuit Go out the temperature coefficient of voltage.

The application is achieved using following technical scheme：

A kind of high-order temperature compensation bandgap reference circuit, including start-up circuit, ambipolar band-gap reference circuit, piecewise linearity Temperature-compensation circuit and Δ V_GSTemperature-compensation circuit, wherein, the enabling signal output end of the start-up circuit connects institute respectively State the enabling signal input and Δ V of ambipolar band-gap reference circuit_GSThe enabling signal input of temperature-compensation circuit, it is described The signal output part of ambipolar band-gap reference circuit connect respectively the start-up circuit voltage signal inputs and described point The signal input part of section linear temperature compensation circuit, the start-up circuit causes band-gap reference circuit normal work, described bipolar Type band-gap reference circuit produces the band gap reference voltage of low-temperature coefficient, and the piecewise linearity temperature-compensation circuit produces temperature point Section linear compensation voltage, the Δ V_GSTemperature-compensation circuit produces Δ V_GSTemperature-compensated voltage, the piecewise linearity temperature-compensating Circuit and Δ V_GSTemperature-compensation circuit carries out temperature-compensating to the ambipolar band-gap reference circuit, will the piecewise linearity Temperature section linear compensation voltage and the Δ V that temperature-compensation circuit is produced_GSThe Δ V that temperature-compensation circuit is produced_GSTemperature is mended Voltage is repaid to be added in the low temperature coefficient with gap reference voltage that the ambipolar band-gap reference circuit is produced.

As a kind of perferred technical scheme, the start-up circuit includes：PMOS MS1, PMOS MS2, NMOS tube MS3, NMOS tube MS4, NMOS tube MS5 and NMOS tube MS6, the ambipolar band-gap reference circuit include：PMOS M1, PMOS Pipe M2, PMOS M3, PMOS M4, PMOS M5, error amplifier A1, error amplifier A2, PNP type triode Q1, positive-negative-positive Triode Q2, resistance R1, resistance R2, resistance R3, resistance R4 and resistance R5, the piecewise linearity temperature-compensation circuit include： PMOS M6, PMOS M9, PMOS M10, PMOS M11, PMOS M13, PMOS M14, PMOS M15, NMOS tube M7, NMOS tube M8 and NMOS tube M12, the Δ V_GSTemperature-compensation circuit includes：PMOS M16, PMOS M17, PMOS M18, NMOS tube M19, NMOS tube M20, error amplifier A3, resistance R6 and resistance R7；

Wherein, PMOS MS1 source electrode is connected with external power source VDD in the start-up circuit, PMOS MS1 grid The source electrode of drain electrode and PMOS MS2 with PMOS MS1 is connected, PMOS MS2 grid and PMOS MS2 drain electrode, NMOS tube MS3 drain electrode, NMOS tube MS4 grid, NMOS tube MS5 grid and NMOS tube MS6 grid are connected, NMOS tube MS3 source electrode and NMOS tube MS4 source electrode, NMOS tube MS5 source electrode, NMOS tube MS6 source electrode and external thread GND phases Even；

PMOS M1 source electrode and PMOS M2 source electrode, PMOS M3 source in the ambipolar band-gap reference circuit Pole, PMOS M4 source electrode, PMOS M5 source electrode and external power source VDD are connected, PMOS M1 drain electrode and the pole of positive-negative-positive three Pipe Q1 emitter stage and error amplifier A1 reverse input end are connected, PMOS M1 grid and PMOS M2 grid, PMOS M4 grid, PMOS M9 grid, PMOS M13 grid, NMOS tube MS5 drain electrode and error amplifier A1 Output end be connected, PNP type triode Q1 base stage and PNP type triode Q1 colelctor electrode, PNP type triode Q2 base stage, PNP type triode Q2 colelctor electrode and external thread GND are connected, and PMOS M2 drain electrode is positive defeated with error amplifier A1's The one end for entering end, error amplifier A2 reverse input end and resistance R1 is connected, resistance the R1 other end and PNP type triode Q2 emitter stage is connected, PMOS M3 grid and error amplifier A2 output end, NMOS tube MS4 drain electrode, PMOS M5 Grid and PMOS M6 grid be connected, PMOS M3 drain electrode and error amplifier A2 positive input and resistance R2 one end is connected, and the resistance R2 other end is connected with external thread GND, PMOS M4 drain electrode and PMOS M5 drain electrode, Band-gap reference output end VREF, NMOS tube MS3 grid and resistance R3 one end are connected, resistance the R3 other end and PMOS M16 drain electrode and resistance R4 one end are connected, the resistance R4 other end and PMOS M11 drain electrode, PMOS M15 drain electrode And resistance R5 one end is connected, the resistance R5 other end is connected with external thread GND；

Source electrode, the PMOS M10 of PMOS M6 source electrode and PMOS M9 in the piecewise linearity temperature-compensation circuit Source electrode, PMOS M11 source electrode, PMOS M13 source electrode, PMOS M14 source electrode, PMOS M15 source electrode and outer Portion power vd D is connected, PMOS M6 drain electrode and NMOS tube M7 drain electrode, NMOS tube M7 grid, NMOS tube M8 grid with And NMOS tube M12 grid is connected, NMOS tube M7 source electrode and NMOS tube M8 source electrode, NMOS tube M12 source electrode and outside Ground wire GND is connected, PMOS M9 drain electrode and PMOS M10 grid, PMOS M10 drain electrode, PMOS M11 grid with And NMOS tube M8 drain electrode is connected, PMOS M13 drain electrode and PMOS M14 grid, PMOS M14 drain electrode, PMOS The drain electrode of M15 grid and NMOS tube M12 is connected；

In the Δ V_GSPMOS M16 source electrode and PMOS M17 source electrode in temperature-compensation circuit, PMOS M18 Source electrode and external power source VDD are connected, PMOS M16 grid and NMOS tube MS6 drain electrode, PMOS M17 grid, PMOS Pipe M18 grid and error amplifier A3 output end are connected, PMOS M17 drain electrode and NMOS tube M19 grid, error Amplifier A3 reverse input end and resistance R6 one end are connected, and the resistance R6 other end is connected with NMOS tube M19 drain electrode, NMOS tube M19 source electrode is connected with NMOS tube M20 source electrode and external thread GND, and PMOS M18 drain electrode and error are amplified Device A3 positive input and resistance R7 one end are connected, the resistance R7 other end and NMOS tube M20 grid and NMOS Pipe M20 drain electrode is connected.

Further, PMOS M1 and PMOS M2 has identical breadth length ratio in the ambipolar band-gap reference circuit, PMOS M4 and PMOS M2 has identical breadth length ratio, then PMOS M4 drain current I₄In resistance R3, resistance R4 and electricity The voltage V produced on resistance R5_PTATFor：In formula, α is PNP type triode Q2 and positive-negative-positive three The ratio between pole pipe Q1 emitter area, k is Boltzmann constant, and T is absolute temperature, and q is electron charge, R₁It is resistance R1 resistance Value, R₃It is resistance R3 resistance, R₄It is resistance R4 resistance, R₅It is resistance R5 resistance；

PMOS M5 and PMOS M3 has identical breadth length ratio, PMOS M5 drain current I₅In resistance R3, resistance The voltage V produced on R4 and resistance R5_CTATFor:In formula, V_EB1It is PNP type triode Q1 Emitter base voltage, R₂It is resistance R2 resistance.

Further, PMOS M6 breadth length ratios are the β of PMOS M3 breadth length ratios in the piecewise linearity temperature-compensation circuit₁ Times, NMOS tube M7 and NMOS tube M8 has identical breadth length ratio, and PMOS M9 breadth length ratios are the β of PMOS M2 breadth length ratios₂Times, PMOS M11 breadth length ratios are the β of PMOS M10 breadth length ratios₃Times, then PMOS M11 drain current I₁₁Produced on resistance R5 Voltage V_NL1For

In formula, T_r1For reference voltage；

PMOS M13 breadth length ratios are the β of PMOS M2 breadth length ratios₄Times, NMOS tube M12 has identical wide with NMOS tube M7 Long ratio, PMOS M15 breadth length ratios are the β of PMOS M14 breadth length ratios₅Times, then PMOS M15 drain current I₁₅On resistance R5 Produce voltage V_NL2For

In formula, T_r2For reference voltage, and T_r2＜ T_r1。

Further, the Δ V_GSIn temperature-compensation circuit, PMOS M17 and PMOS M18 has identical breadth length ratio, And PMOS M17 and PMOS M18 is operated in saturation region, NMOS tube M20 breadth length ratios are the β of NMOS tube M19 breadth length ratios₇Times, And NMOS tube M19 and NMOS tube M20 is operated in sub-threshold region, PMOS M16 breadth length ratios are the β of PMOS M18 breadth length ratios₆ Times, PMOS M16 drain current I₁₆The pressure drop V produced on resistance R4 and resistance R5_{BGR_MOS}For

In formula, R₇It is resistance R7 resistance, E, F and G are positive constant.

Further, the output voltage V of described high-order temperature compensation bandgap reference circuit_REFFor

V_REF=(V_CTAT+V_PTAT)+(V_{BGR_MOS}+V_NL1+V_NL2)。

Compared with prior art, the technique effect that has of technical scheme or advantage that the application is provided be：By piecewise linearity The compensation circuit voltage V that temperature-compensation circuit 3 is provided_NL1And V_NL2、ΔV_GSThe Δ V that temperature-compensation circuit 4 is provided_GSTemperature-compensating Voltage V_{BGR_MOS}It is incorporated into ambipolar band-gap reference 2, obtains high-order temperature compensated reference voltage, so as to obtains smaller temperature The reference voltage of coefficient.

Brief description of the drawings

Fig. 1 is the principle schematic of conventional first order band-gap reference circuit；

Fig. 2 is the structure chart of the high-order temperature compensation bandgap reference circuit of the present invention；

Fig. 3 is the circuit diagram of the high-order temperature compensation bandgap reference circuit of the present invention；

Fig. 4 is single order band-gap reference circuit output voltage curve schematic diagram；

Fig. 5 is introducing Δ V_GSTemperature-compensated voltage V_{BGR_MOS}Output voltage curve schematic diagram afterwards；

Fig. 6 is introducing Δ V_GSTemperature-compensated voltage V_{BGR_MOS}And piecewise linearity temperature-compensated voltage V_NL1Output electricity afterwards Press curve synoptic diagram；

Fig. 7 is the output voltage curve figure of the high-order temperature compensation bandgap reference circuit of the present invention；

Fig. 8 is the output voltage temperature characterisitic analogous diagram of the high-order temperature compensation bandgap reference circuit of the present invention.

Embodiment

The embodiment of the present application is mended the piecewise linearity temperature by providing a kind of high-order temperature compensation bandgap reference circuit Repay the temperature section linear compensation voltage and the Δ V of circuit generation_GSThe Δ V that temperature-compensation circuit is produced_GSTemperature-compensated voltage It is added in the low temperature coefficient with gap reference voltage that the ambipolar band-gap reference circuit is produced, so as to obtain high-order temperature benefit The reference voltage repaid, significantly reduces the temperature coefficient of band-gap reference circuit output voltage.

It is right below in conjunction with Figure of description and specific embodiment in order to be better understood from above-mentioned technical proposal Above-mentioned technical proposal is described in detail.

Embodiment

A kind of high-order temperature compensation bandgap reference circuit, as shown in Fig. 2 including start-up circuit 1, ambipolar band-gap reference electricity Road 2, piecewise linearity temperature-compensation circuit 3 and Δ V_GSTemperature-compensation circuit 4, wherein, the enabling signal of the start-up circuit 1 is defeated Go out enabling signal input and Δ V that end connects the ambipolar band-gap reference circuit 2 respectively_GSTemperature-compensation circuit 4 is opened Dynamic signal input part, the signal output part of the ambipolar band-gap reference circuit 2 connects the voltage letter of the start-up circuit 1 respectively The signal input part of number input and the piecewise linearity temperature-compensation circuit 3, the start-up circuit 1 causes band-gap reference electricity Road normal work, the ambipolar band-gap reference circuit 2 produces the band gap reference voltage of low-temperature coefficient, and the segmented line is warm-natured Spend compensation circuit 3 and produce temperature section linear compensation voltage, the Δ V_GSTemperature-compensation circuit 4 produces Δ V_GSTemperature-compensating electricity Pressure, the piecewise linearity temperature-compensation circuit 3 and Δ V_GS4 pairs of the temperature-compensation circuit ambipolar band-gap reference circuit 2 enters Trip temperature is compensated, will the piecewise linearity temperature-compensation circuit 3 the temperature section linear compensation voltage and the Δ V that produce_GS The Δ V that temperature-compensation circuit 4 is produced_GSTemperature-compensated voltage is added to the low temperature that the ambipolar band-gap reference circuit 2 is produced In coefficient band gap reference voltage.

As a kind of perferred technical scheme, as shown in figure 3, the start-up circuit 1 includes：PMOS MS1, PMOS MS2, NMOS tube MS3, NMOS tube MS4, NMOS tube MS5 and NMOS tube MS6, the ambipolar band-gap reference circuit 2 include： PMOS M1, PMOS M2, PMOS M3, PMOS M4, PMOS M5, error amplifier A1, error amplifier A2, positive-negative-positive Triode Q1, PNP type triode Q2, resistance R1, resistance R2, resistance R3, resistance R4 and resistance R5, the piecewise linearity temperature Compensation circuit 3 includes：PMOS M6, PMOS M9, PMOS M10, PMOS M11, PMOS M13, PMOS M14, PMOS Pipe M15, NMOS tube M7, NMOS tube M8 and NMOS tube M12, the Δ V_GSTemperature-compensation circuit 4 includes：PMOS M16, PMOS Pipe M17, PMOS M18, NMOS tube M19, NMOS tube M20, error amplifier A3, resistance R6 and resistance R7；

Wherein, PMOS MS1 source electrode is connected with external power source VDD in the start-up circuit 1, PMOS MS1 grid Pole is connected with PMOS MS1 drain electrode and PMOS MS2 source electrode, PMOS MS2 grid and PMOS MS2 drain electrode, NMOS tube MS3 drain electrode, NMOS tube MS4 grid, NMOS tube MS5 grid and NMOS tube MS6 grid are connected, NMOS tube MS3 source electrode and NMOS tube MS4 source electrode, NMOS tube MS5 source electrode, NMOS tube MS6 source electrode and external thread GND phases Even；

PMOS M1 source electrode and PMOS M2 source electrode, PMOS M3 in the ambipolar band-gap reference circuit 2 Source electrode, PMOS M4 source electrode, PMOS M5 source electrode and external power source VDD are connected, PMOS M1 drain electrode and positive-negative-positive three Pole pipe Q1 emitter stage and error amplifier A1 reverse input end are connected, PMOS M1 grid and PMOS M2 grid Pole, PMOS M4 grid, PMOS M9 grid, PMOS M13 grid, NMOS tube MS5 drain electrode and error amplification Device A1 output end is connected, PNP type triode Q1 base stage and PNP type triode Q1 colelctor electrode, PNP type triode Q2 base Pole, PNP type triode Q2 colelctor electrode and external thread GND are connected, and PMOS M2 drain electrode and error amplifier A1 are just It is connected to one end of input, error amplifier A2 reverse input end and resistance R1, resistance the R1 other end and positive-negative-positive three Pole pipe Q2 emitter stage is connected, PMOS M3 grid and error amplifier A2 output end, NMOS tube MS4 drain electrode, PMOS Pipe M5 grid and PMOS M6 grid are connected, PMOS M3 drain electrode and error amplifier A2 positive input and Resistance R2 one end is connected, and the resistance R2 other end is connected with external thread GND, PMOS M4 drain electrode and PMOS M5 leakage Pole, band-gap reference output end VREF, NMOS tube MS3 grid and resistance R3 one end are connected, the resistance R3 other end with PMOS M16 drain electrode and resistance R4 one end are connected, the resistance R4 other end and PMOS M11 drain electrode, PMOS M15 Drain electrode and resistance R5 one end be connected, the resistance R5 other end is connected with external thread GND；

Source electrode, the PMOS M10 of PMOS M6 source electrode and PMOS M9 in the piecewise linearity temperature-compensation circuit 3 Source electrode, PMOS M11 source electrode, PMOS M13 source electrode, PMOS M14 source electrode, PMOS M15 source electrode and outer Portion power vd D is connected, PMOS M6 drain electrode and NMOS tube M7 drain electrode, NMOS tube M7 grid, NMOS tube M8 grid with And NMOS tube M12 grid is connected, NMOS tube M7 source electrode and NMOS tube M8 source electrode, NMOS tube M12 source electrode and outside Ground wire GND is connected, PMOS M9 drain electrode and PMOS M10 grid, PMOS M10 drain electrode, PMOS M11 grid with And NMOS tube M8 drain electrode is connected, PMOS M13 drain electrode and PMOS M14 grid, PMOS M14 drain electrode, PMOS The drain electrode of M15 grid and NMOS tube M12 is connected；

In the Δ V_GSPMOS M16 source electrode and PMOS M17 source electrode in temperature-compensation circuit 4, PMOS M18 Source electrode and external power source VDD are connected, PMOS M16 grid and NMOS tube MS6 drain electrode, PMOS M17 grid, PMOS Pipe M18 grid and error amplifier A3 output end are connected, PMOS M17 drain electrode and NMOS tube M19 grid, error Amplifier A3 reverse input end and resistance R6 one end are connected, and the resistance R6 other end is connected with NMOS tube M19 drain electrode, NMOS tube M19 source electrode is connected with NMOS tube M20 source electrode and external thread GND, and PMOS M18 drain electrode and error are amplified Device A3 positive input and resistance R7 one end are connected, the resistance R7 other end and NMOS tube M20 grid and NMOS Pipe M20 drain electrode is connected.

Error amplifier A1 causes the input node A of error amplifier and defeated in the ambipolar band-gap reference circuit 2 Ingress B voltage is equal, i.e. V_A=V_B=V_EB1, wherein, V_EB1It is PNP type triode Q1 emitter base voltage, V_AIt is Node A voltage, V_BIt is node B voltage.PMOS M1 and PMOS M2 has identical breadth length ratio, then PMOS M2 leakage Electrode current I₂ForIn formula, α is the ratio between PNP type triode Q2 and PNP type triode Q1 emitter area, and k is Boltzmann constant, T is absolute temperature, and q is electron charge, R₁It is resistance R1 resistance, and all resistance is all identical material What material was realized.PMOS M4 and PMOS M2 has identical breadth length ratio, thus PMOS M4 drain current I₄For I₄=I₂, Then electric current I₄Pressure drop V is produced on resistance R3, resistance R4 and resistance R5_PTATFor：

In formula, R₃It is resistance R3 resistance, R₄It is resistance R4 resistance, R₅It is resistance R5 resistance, electricity is understood by formula (1) Press V_PTATWith positive temperature coefficient.

Error amplifier A2 causes error amplifier A1 input node B and error amplifier A2 input node C electricity Press equal, i.e. V_B=V_C=V_EB1, wherein V_CIt is node C voltage, the input node B of the error amplifier A1 is simultaneously described Error amplifier A2 input node, PMOS M3 drain current I₃ForIn formula, R₂It is resistance R₂Resistance. PMOS M5 and PMOS M3 has identical breadth length ratio, thus PMOS M5 drain current I₅For I₅=I₃, then electric current I₅ Pressure drop V is produced on resistance R3, resistance R4 and resistance R5_CTATFor：

Voltage V is understood by formula (2)_CTATWith negative temperature coefficient.

The present invention is in order to compensate V_EB1The temperature high-order nonlinear of low-temperature region, using piecewise linearity temperature-compensation circuit 3.PMOS M6 breadth length ratios are the β of PMOS M3 breadth length ratios₁Times, NMOS tube M7 and NMOS tube M8 has identical breadth length ratio, then NMOS tube M8 drain current I₈For I₈=β₁I₃.PMOS M9 breadth length ratios are the β of PMOS M2 breadth length ratios₂Times, then PMOS M9 Drain current I₉For I₉=β₂I₂.From (1), (2) formula, it is more than or equal to reference temperature T in temperature T_r1Under the conditions of, by excellent Change parameter beta₁With β₂, PMOS M10 drain current I₁₀There is I₁₀=I₈-I₉=β₁I₃-β₂I₂=0.PMOS M11 breadth length ratios are The β of PMOS M10 breadth length ratios₃Times, then PMOS M11 drain current I₁₁The pressure drop V produced on resistance R5_NL1For：

In formula, R₅It is resistance R5 resistance, from formula (3), PMOS M11 drain current I₁₁Produced on resistance R5 Pressure drop V_NL1With temperature section linear characteristic.

PMOS M13 breadth length ratios are the β of PMOS M2 breadth length ratios₄Times, NMOS tube M12 has identical wide with NMOS tube M7 Long ratio, from formula (1), (2), is more than or equal to reference temperature T in temperature T_r2Under the conditions of, pass through Optimal Parameters β₄, PMOS M14 Drain current I₁₄There is I₁₄=I₁₂-I₁₃=β₁I₃-β₄I₂=0, wherein T_r2＜ T_r1.PMOS M15 breadth length ratios are PMOS M14 The β of breadth length ratio₅Times, then PMOS M15 drain current I₁₅The pressure drop V produced on resistance R5_NL2For：

From formula (4), PMOS M15 drain current I₁₅The pressure drop V produced in resistance R5_NL2With temperature section line Property characteristic.

The present invention is compensation V_EB1Temperature high-order nonlinear, using Δ V_GSTemperature-compensation circuit 4.PMOS M17 with PMOS M18 has identical breadth length ratio, and PMOS M17 and PMOS M18 is operated in saturation region.NMOS tube M19 with NMOS tube M20 is operated in sub-threshold region, and is operated in the drain current I of sub-threshold region NMOS tube_DFor：

In formula, μ_nIt is electron mobility, C_oxIt is unit area gate oxide capacitance, V_THIt is the threshold voltage of metal-oxide-semiconductor, V_GS It is the gate source voltage of metal-oxide-semiconductor, V_DSIt is the drain-source voltage of metal-oxide-semiconductor,It is the breadth length ratio of metal-oxide-semiconductor, m and n are the ginsengs related to technique Number.Work as V_DS>200mV, formula (5) can be approximately：

NMOS tube M20 breadth length ratios are the β of NMOS tube M19 breadth length ratios₇Times, PMOS M16 breadth length ratios are the wide length of PMOS M18 The β of ratio₆Times, then PMOS M16 drain current I₁₆For：

In fact, in formula (7), R₇It is resistance R7 resistance, n and temperature T relation is n (T)=E+FT+GT², wherein, E, F and G is positive constant.Thus electric current I₁₆The pressure drop V produced on resistance R4 and resistance R5_{BGR_MOS}For：

From formula (1)-formula (8), high-order temperature compensation bandgap reference circuit output end VREF output voltage V_REFFor：

V_REF=(V_CTAT+V_PTAT)+(V_{BGR_MOS}+V_NL1+V_NL2) (9)

From formula (9), band-gap reference output voltage V_REFIt is divided into two factors.One factor isIts Pass through Optimal Parameters α and resistance R₁、R₂, single order temperature-compensating is realized, single order bandgap voltage reference is obtained；Another factor is (V_{BGR_MOS}+V_NL1+V_NL2), it compensates V_EB1Temperature high-order nonlinear, obtain high-order temperature compensation bandgap reference voltage, i.e., It can obtain bandgap voltage reference curve shown in Fig. 7.Wherein, Fig. 4 is single order band-gap reference output voltage curve schematic diagram, and Fig. 5 is Introduce Δ V_GSTemperature-compensated voltage V_{BGR_MOS}Output voltage curve schematic diagram afterwards, Fig. 6 is introducing Δ V_GSTemperature-compensated voltage V_{BGR_MOS}And piecewise linearity temperature-compensated voltage V_NL1Output voltage curve schematic diagram afterwards, Fig. 7 is introducing Δ V_GSTemperature-compensating Voltage V_{BGR_MOS}And piecewise linearity temperature-compensated voltage V_NL1、V_NL2Output voltage curve schematic diagram afterwards, i.e. high-order temperature are mended Repay the output voltage schematic diagram of band-gap reference circuit.

From formula (1)-formula (9) and Fig. 7, the output voltage of high-order temperature compensation bandgap reference circuit of the invention V_REFTemperature characteristics can be divided into following three region：

Region 1, temperature T is more than reference temperature T_r1, i.e. T ＞ T_r1.In this region, V_NL1And V_NL2It is zero, band-gap reference The output voltage V of circuit_REFBy V_CTAT、V_PTATAnd V_{BGR_MOS}Contribute, then the output voltage V of band-gap reference circuit_REFFor：

V_REF=V_CTAT+V_PTAT+V_{BGR_MOS} (10)

Region 2, temperature T is more than reference temperature T_r2, less than reference temperature T_r1, i.e. T_r2＜ T ＜ T_r1.In the region, V_NL2For Zero, the output voltage V of band-gap reference circuit_REFBy V_CTAT、V_PTAT、V_{BGR_MOS}And V_NL1The output electricity of contribution, then band-gap reference circuit Press V_REFFor：

V_REF=V_CTAT+V_PTAT+V_{BGR_MOS}+V_NL1 (11)

Region 3, temperature T is less than reference temperature T_r2, i.e. T ＜ T_r2.The region, the output voltage V of band-gap reference circuit_REFBy V_CTAT、V_PTAT、V_{BGR_MOS}、V_NL1And V_NL2Contribute, then the output voltage V of band-gap reference circuit_REFFor：

V_REF=V_CTAT+V_PTAT+V_{BGR_MOS}+V_NL1+V_NL2 (12)

Fig. 8 is the output voltage V of the high-order temperature compensation bandgap reference circuit of the present invention_REFTemperature characterisitic simulation curve, Wherein abscissa is temperature, and ordinate is band-gap reference output voltage.Simulation result shows, is -55 DEG C~125 in temperature range DEG C, the high-order temperature compensated band-gap reference circuit has reached 0.6457ppm/ DEG C of temperature coefficient.

When start-up circuit 1 starts, due to band-gap reference output voltage V_REFCompare relatively low, NMOS tube MS3 cut-offs so that NMOS tube MS4, NMOS tube MS5 and NMOS tube MS6 grid potential be high potential so that PMOS M1, PMOS M2, PMOS M3, PMOS M17, PMOS M18 grid be low potential, this just formed PMOS M1 to PNP type triode Q1, PMOS M2 to resistance R1 to PNP type triode Q2, PMOS M3 are to resistance R2, PMOS M17 to resistance R6 to NMOS tube The current path of M19, PMOS M18 to resistance R7 to NMOS tube M20 so that circuit departs from nought state, into working condition.So And, V_REFWhen rising to more than NMOS tube threshold voltage, NMOS tube MS3 conductings so that NMOS tube MS4, NMOS tube MS5 and NMOS Pipe MS6 grid is low potential and is operated in cut-off region so that start-up circuit 1 is no longer produced to band-gap reference reference circuit below Raw influence, start completion.

In above-described embodiment of the application, by providing a kind of high-order temperature compensation bandgap reference circuit, including start electricity Road, ambipolar band-gap reference circuit, piecewise linearity temperature-compensation circuit and Δ V_GSTemperature-compensation circuit, wherein, it is described to start The enabling signal output end of circuit connects the enabling signal input and Δ V of the ambipolar band-gap reference circuit respectively_GSTemperature The enabling signal input of compensation circuit is spent, the signal output part of the ambipolar band-gap reference circuit connects the startup respectively The signal input part of the voltage signal inputs of circuit and the piecewise linearity temperature-compensation circuit, the start-up circuit causes High-order temperature compensation bandgap reference circuit normal work, the ambipolar band-gap reference circuit produces the band gap ginseng of low-temperature coefficient Examine voltage, the piecewise linearity temperature-compensation circuit and Δ V_GSTemperature-compensation circuit enters to the ambipolar band-gap reference circuit Trip temperature is compensated, and significantly reduces the temperature coefficient of band-gap reference circuit output voltage.

It should be pointed out that described above is not limitation of the present invention, the present invention is also not limited to the example above, What those skilled in the art were made in the essential scope of the present invention changes, is modified, adds or replaces, and also should Belong to protection scope of the present invention.

Claims (5)

1. a kind of high-order temperature compensation bandgap reference circuit, it is characterised in that including start-up circuit (1), ambipolar band-gap reference Circuit (2), piecewise linearity temperature-compensation circuit (3) and Δ V_GSTemperature-compensation circuit (4), wherein, the start-up circuit (1) Enabling signal output end connects the enabling signal input and the Δ V of the ambipolar band-gap reference circuit (2) respectively_GSTemperature The enabling signal input of compensation circuit (4) is spent, the signal output part of the ambipolar band-gap reference circuit (2) connects institute respectively The voltage signal inputs of start-up circuit (1) and the signal input part of the piecewise linearity temperature-compensation circuit (3) are stated, it is described Start-up circuit (1) causes band-gap reference circuit normal work, and the ambipolar band-gap reference circuit (2) produces low-temperature coefficient Band gap reference voltage, the piecewise linearity temperature-compensation circuit (3) produces temperature section linear compensation voltage, the Δ V_GSTemperature Compensation circuit (4) produces Δ V_GSTemperature-compensated voltage, the piecewise linearity temperature-compensation circuit (3) and Δ V_GSTemperature-compensating Circuit (4) carries out temperature-compensating to the ambipolar band-gap reference circuit (2), will the piecewise linearity temperature-compensation circuit (3) the temperature section linear compensation voltage and the Δ V produced_GSThe Δ V that temperature-compensation circuit (4) is produced_GSTemperature-compensated voltage It is added in the band gap reference voltage that the ambipolar band-gap reference circuit (2) produces；

The start-up circuit (1) includes：PMOS MS1, PMOS MS2, NMOS tube MS3, NMOS tube MS4, NMOS tube MS5 and NMOS tube MS6, the ambipolar band-gap reference circuit (2) includes：PMOS M1, PMOS M2, PMOS M3, PMOS M4, PMOS M5, error amplifier A1, error amplifier A2, PNP type triode Q1, PNP type triode Q2, resistance R1, resistance R2, Resistance R3, resistance R4 and resistance R5, the piecewise linearity temperature-compensation circuit (3) include：PMOS M6, PMOS M9, PMOS M10, PMOS M11, PMOS M13, PMOS M14, PMOS M15, NMOS tube M7, NMOS tube M8 and NMOS tube M12, the Δ V_GSTemperature-compensation circuit (4) includes：PMOS M16, PMOS M17, PMOS M18, NMOS tube M19, NMOS Pipe M20, error amplifier A3, resistance R6 and resistance R7；

Wherein, PMOS MS1 source electrode is connected with external power source VDD in the start-up circuit (1), PMOS MS1 grid The source electrode of drain electrode and PMOS MS2 with PMOS MS1 is connected, PMOS MS2 grid and PMOS MS2 drain electrode, NMOS tube MS3 drain electrode, NMOS tube MS4 grid, NMOS tube MS5 grid and NMOS tube MS6 grid are connected, NMOS tube MS3 source electrode and NMOS tube MS4 source electrode, NMOS tube MS5 source electrode, NMOS tube MS6 source electrode and external thread GND phases Even；

PMOS M1 source electrode and PMOS M2 source electrode, PMOS M3 source in the ambipolar band-gap reference circuit (2) Pole, PMOS M4 source electrode, PMOS M5 source electrode and external power source VDD are connected, PMOS M1 drain electrode and the pole of positive-negative-positive three Pipe Q1 emitter stage and error amplifier A1 reverse input end are connected, PMOS M1 grid and PMOS M2 grid, PMOS M4 grid, PMOS M9 grid, PMOS M13 grid, NMOS tube MS5 drain electrode and error amplifier A1 Output end be connected, PNP type triode Q1 base stage and PNP type triode Q1 colelctor electrode, PNP type triode Q2 base stage, PNP type triode Q2 colelctor electrode and external thread GND are connected, and PMOS M2 drain electrode is positive defeated with error amplifier A1's The one end for entering end, error amplifier A2 reverse input end and resistance R1 is connected, resistance the R1 other end and PNP type triode Q2 emitter stage is connected, PMOS M3 grid and error amplifier A2 output end, NMOS tube MS4 drain electrode, PMOS M5 Grid and PMOS M6 grid be connected, PMOS M3 drain electrode and error amplifier A2 positive input and resistance R2 one end is connected, and the resistance R2 other end is connected with external thread GND, PMOS M4 drain electrode and PMOS M5 drain electrode, Band-gap reference output end VREF, NMOS tube MS3 grid and resistance R3 one end are connected, resistance the R3 other end and PMOS M16 drain electrode and resistance R4 one end are connected, the resistance R4 other end and PMOS M11 drain electrode, PMOS M15 drain electrode And resistance R5 one end is connected, the resistance R5 other end is connected with external thread GND；

PMOS M6 source electrode and PMOS M9 source electrode, PMOS M10 in the piecewise linearity temperature-compensation circuit (3) Source electrode, PMOS M11 source electrode, PMOS M13 source electrode, PMOS M14 source electrode, PMOS M15 source electrode and outside Power vd D is connected, PMOS M6 drain electrode and NMOS tube M7 drain electrode, NMOS tube M7 grid, NMOS tube M8 grid and NMOS tube M12 grid is connected, NMOS tube M7 source electrode and NMOS tube M8 source electrode, NMOS tube M12 source electrode and externally Line GND is connected, PMOS M9 drain electrode and PMOS M10 grid, PMOS M10 drain electrode, PMOS M11 grid and NMOS tube M8 drain electrode is connected, PMOS M13 drain electrode and PMOS M14 grid, PMOS M14 drain electrode, PMOS M15 Grid and NMOS tube M12 drain electrode be connected；

In the Δ V_GSPMOS M16 source electrode and PMOS M17 source electrode, PMOS M18 source in temperature-compensation circuit (4) Pole and external power source VDD are connected, PMOS M16 grid and NMOS tube MS6 drain electrode, PMOS M17 grid, PMOS M18 grid and error amplifier A3 output end are connected, and PMOS M17 drain electrode is put with NMOS tube M19 grid, error Big device A3 reverse input end and resistance R6 one end are connected, and the resistance R6 other end is connected with NMOS tube M19 drain electrode, NMOS tube M19 source electrode is connected with NMOS tube M20 source electrode and external thread GND, and PMOS M18 drain electrode and error are amplified Device A3 positive input and resistance R7 one end are connected, the resistance R7 other end and NMOS tube M20 grid and NMOS Pipe M20 drain electrode is connected.

2. high-order temperature compensation bandgap reference circuit according to claim 1, it is characterised in that the ambipolar band gap base PMOS M1 and PMOS M2 has identical breadth length ratio in quasi- circuit (2), and PMOS M4 has identical wide with PMOS M2 Length compares, then PMOS M4 drain current I₄The voltage V produced on resistance R3, resistance R4 and resistance R5_PTATFor：In formula, α is the ratio between PNP type triode Q2 and PNP type triode Q1 emitter area, K is Boltzmann constant, and T is absolute temperature, and q is electron charge, R₁It is resistance R1 resistance, R₃It is resistance R3 resistance, R₄It is Resistance R4 resistance, R₅It is resistance R5 resistance；

PMOS M5 and PMOS M3 has identical breadth length ratio, PMOS M5 drain current I₅In resistance R3, resistance R4 and electricity The voltage V produced on resistance R5_CTATFor:In formula, V_EB1Be PNP type triode Q1 emitter stage- Base voltage, R₂It is resistance R2 resistance.

3. high-order temperature compensation bandgap reference circuit according to claim 2, it is characterised in that the piecewise linearity temperature PMOS M6 breadth length ratios are the β of PMOS M3 breadth length ratios in compensation circuit (3)₁Times, NMOS tube M7 and NMOS tube M8 has identical Breadth length ratio, PMOS M9 breadth length ratios are the β of PMOS M2 breadth length ratios₂Times, PMOS M11 breadth length ratios are the wide length of PMOS M10 The β of ratio₃Times, then PMOS M11 drain current I₁₁Voltage V is produced on resistance R5_NL1For

<mrow> <msub> <mi>V</mi> <mrow> <mi>N</mi> <mi>L</mi> <mn>1</mn> </mrow> </msub> <mo>=</mo> <mfenced open = "{" close = ""> <mtable> <mtr> <mtd> <mrow> <msub> <mi>R</mi> <mn>5</mn> </msub> <msub> <mi>&amp;beta;</mi> <mn>3</mn> </msub> <mrow> <mo>(</mo> <msub> <mi>&amp;beta;</mi> <mn>1</mn> </msub> <mfrac> <msub> <mi>V</mi> <mrow> <mi>E</mi> <mi>B</mi> <mn>1</mn> </mrow> </msub> <msub> <mi>R</mi> <mn>2</mn> </msub> </mfrac> <mo>-</mo> <msub> <mi>&amp;beta;</mi> <mn>2</mn> </msub> <mfrac> <mrow> <mi>k</mi> <mi>T</mi> </mrow> <mrow> <msub> <mi>qR</mi> <mn>1</mn> </msub> </mrow> </mfrac> <mi>l</mi> <mi>n</mi> <mi>&amp;alpha;</mi> <mo>)</mo> </mrow> </mrow> </mtd> <mtd> <mrow> <mi>T</mi> <mo>&lt;</mo> <msub> <mi>T</mi> <mrow> <mi>r</mi> <mn>1</mn> </mrow> </msub> </mrow> </mtd> </mtr> <mtr> <mtd> <mn>0</mn> </mtd> <mtd> <mrow> <mi>T</mi> <mo>&amp;GreaterEqual;</mo> <msub> <mi>T</mi> <mrow> <mi>r</mi> <mn>1</mn> </mrow> </msub> </mrow> </mtd> </mtr> </mtable> </mfenced> </mrow>

In formula, T_r1For reference voltage；

PMOS M13 breadth length ratios are the β of PMOS M2 breadth length ratios₄Times, NMOS tube M12 and NMOS tube M7 has identical breadth length ratio, PMOS M15 breadth length ratios are the β of PMOS M14 breadth length ratios₅Times, then PMOS M15 drain current I₁₅Produced on resistance R5 Voltage V_NL2For

<mrow> <msub> <mi>V</mi> <mrow> <mi>N</mi> <mi>L</mi> <mn>2</mn> </mrow> </msub> <mo>=</mo> <mfenced open = "{" close = ""> <mtable> <mtr> <mtd> <mrow> <msub> <mi>R</mi> <mn>5</mn> </msub> <msub> <mi>&amp;beta;</mi> <mn>5</mn> </msub> <mrow> <mo>(</mo> <msub> <mi>&amp;beta;</mi> <mn>1</mn> </msub> <mfrac> <msub> <mi>V</mi> <mrow> <mi>E</mi> <mi>B</mi> <mn>1</mn> </mrow> </msub> <msub> <mi>R</mi> <mn>2</mn> </msub> </mfrac> <mo>-</mo> <msub> <mi>&amp;beta;</mi> <mn>4</mn> </msub> <mfrac> <mrow> <mi>k</mi> <mi>T</mi> </mrow> <mrow> <msub> <mi>qR</mi> <mn>1</mn> </msub> </mrow> </mfrac> <mi>l</mi> <mi>n</mi> <mi>&amp;alpha;</mi> <mo>)</mo> </mrow> </mrow> </mtd> <mtd> <mrow> <mi>T</mi> <mo>&lt;</mo> <msub> <mi>T</mi> <mrow> <mi>r</mi> <mn>2</mn> </mrow> </msub> </mrow> </mtd> </mtr> <mtr> <mtd> <mn>0</mn> </mtd> <mtd> <mrow> <mi>T</mi> <mo>&amp;GreaterEqual;</mo> <msub> <mi>T</mi> <mrow> <mi>r</mi> <mn>2</mn> </mrow> </msub> </mrow> </mtd> </mtr> </mtable> </mfenced> </mrow>

In formula, T_r2For reference voltage, and T_r2＜ T_r1。

4. high-order temperature compensation bandgap reference circuit according to claim 3, it is characterised in that the Δ V_GSTemperature-compensating In circuit (4), PMOS M17 and PMOS M18 has identical breadth length ratio, and PMOS M17 and PMOS M18 is operated in Saturation region, NMOS tube M20 breadth length ratios are the β of NMOS tube M19 breadth length ratios₇Times, and NMOS tube M19 and NMOS tube M20 is operated in Sub-threshold region, PMOS M16 breadth length ratios are the β of PMOS M18 breadth length ratios₆Times, PMOS M16 drain current I₁₆In resistance R4 With the pressure drop V produced on resistance R5_{BGR_MOS}For

<mrow> <msub> <mi>V</mi> <mrow> <mi>B</mi> <mi>G</mi> <mi>R</mi> <mo>_</mo> <mi>M</mi> <mi>O</mi> <mi>S</mi> </mrow> </msub> <mo>=</mo> <msub> <mi>&amp;beta;</mi> <mn>6</mn> </msub> <mfrac> <mrow> <mi>k</mi> <mrow> <mo>(</mo> <msub> <mi>R</mi> <mn>4</mn> </msub> <mo>+</mo> <msub> <mi>R</mi> <mn>5</mn> </msub> <mo>)</mo> </mrow> <msub> <mi>ln&amp;beta;</mi> <mn>7</mn> </msub> </mrow> <mrow> <msub> <mi>qR</mi> <mn>7</mn> </msub> </mrow> </mfrac> <mrow> <mo>(</mo> <mi>E</mi> <mi>T</mi> <mo>+</mo> <msup> <mi>FT</mi> <mn>2</mn> </msup> <mo>+</mo> <msup> <mi>GT</mi> <mn>3</mn> </msup> <mo>)</mo> </mrow> </mrow>

In formula, R₇It is resistance R7 resistance, E, F and G are positive constant.

5. high-order temperature compensation bandgap reference circuit according to claim 4, it is characterised in that described high-order temperature is mended Repay the output voltage V of band-gap reference circuit_REFFor

V_REF=(V_CTAT+V_PTAT)+(V_BGR-MOS+V_NL1+V_NL2)。