CN105807838A - High-order temperature compensation band gap reference circuit - Google Patents

Abstract

The invention provides a high-order temperature compensation band gap reference circuit. The high-order temperature compensation band gap reference circuit comprises a start circuit, a bipolar band gap reference circuit, a segmental linear temperature compensation circuit and a delta VGS temperature compensation circuit, wherein the start circuit ensures that the high-order temperature compensation band gap reference circuit works normally, the bipolar band gap reference circuit generates a band gap reference voltage of a low temperature coefficient, and a temperature segmental linear compensation voltage generated by the segmental linear temperature compensation circuit and a delta VGS temperature compensation voltage generated by the delta VGS temperature compensation circuit are added into the low-temperature coefficient band gap reference voltage generated by the bipolar band gap reference circuit, so that a high-order temperature compensation reference voltage is obtained, and the temperature coefficient of a band gap reference circuit output voltage is greatly decreased.

Description

High-order temperature compensation bandgap reference circuit

Technical field

The present invention relates to microelectronics technology, be specifically related to a kind of high-order temperature compensation bandgap reference circuit.

Background technology

Band-gap reference circuit is many simulations and the basic module of Digital Analog Hybrid Circuits system, and its reference voltage for simulating and the offer of Digital Analog Hybrid Circuits system is stable, its Performance Characteristics directly affects the Performance Characteristics of simulation and Digital Analog Hybrid Circuits system.

Fig. 1 gives a kind of traditional single order band-gap reference, and resistance R2 and R3 is just the same, and nmos pass transistor M1 and M2 has identical breadth length ratio, and the emitter area of PNP type triode Q2 is α times of the emitter area of PNP type triode Q1.The emitter base voltage V of PNP type triode Q1_EB1Increase along with temperature and reduce, the both end voltage of resistance R2Wherein k is Boltzmann constant, and T is absolute temperature, and q is electron charge, R₁For the resistance of resistance R1, R₂Resistance for resistance R2.According to principle of stacking, the voltage of the band-gap reference circuit outfan VREF shown in Fig. 1In formula, V_EB1There is negative temperature coefficient,There is positive temperature coefficient, thus Reasonable adjustment α, R₁And R₂Size, the band-gap reference reference voltage V of zero-temperature coefficient can be obtained in certain temperature range_REF。

But, due to PNP type triode emitter base voltage V_EBNonlinear temperature make single order band-gap reference reference voltage have higher temperature coefficient, thus constraining the application in High Definition Systems of the single order band-gap reference circuit.

Summary of the invention

The application is by providing a kind of high-order temperature compensation bandgap reference circuit, it is possible to be substantially reduced the temperature coefficient of band-gap reference circuit output voltage.

The application is achieved by the following technical solutions:

A kind of high-order temperature compensation bandgap reference circuit, including start-up circuit, ambipolar band-gap reference circuit, piecewise linearity temperature-compensation circuit and Δ V_GSTemperature-compensation circuit, wherein, the enabling signal outfan of described start-up circuit connects enabling signal input and the Δ V of described ambipolar band-gap reference circuit respectively_GSThe enabling signal input of temperature-compensation circuit, the signal output part of described ambipolar band-gap reference circuit connects the voltage signal inputs of described start-up circuit and the signal input part of described piecewise linearity temperature-compensation circuit respectively, described start-up circuit makes band-gap reference circuit normal operation, described ambipolar band-gap reference circuit produces the band gap reference voltage of low-temperature coefficient, described piecewise linearity temperature-compensation circuit produces temperature section linear compensation voltage, described Δ V_GSTemperature-compensation circuit produces Δ V_GSTemperature-compensated voltage, described piecewise linearity temperature-compensation circuit and Δ V_GSDescribed ambipolar band-gap reference circuit is carried out temperature-compensating by temperature-compensation circuit, by temperature section linear compensation voltage and the described Δ V of the generation of described piecewise linearity temperature-compensation circuit_GSThe Δ V that temperature-compensation circuit produces_GSTemperature-compensated voltage joins in the low temperature coefficient with gap reference voltage that described ambipolar band-gap reference circuit produces.

nullAs the preferred technical scheme of one，Described start-up circuit includes: PMOS MS1、PMOS MS2、NMOS tube MS3、NMOS tube MS4、NMOS tube MS5 and NMOS tube MS6，Described ambipolar band-gap reference circuit includes: PMOS M1、PMOS M2、PMOS M3、PMOS M4、PMOS M5、Error amplifier A1、Error amplifier A2、PNP type triode Q1、PNP type triode Q2、Resistance R1、Resistance R2、Resistance R3、Resistance R4 and resistance R5，Described piecewise linearity temperature-compensation circuit includes: PMOS M6、PMOS M9、PMOS M10、PMOS M11、PMOS M13、PMOS M14、PMOS M15、NMOS tube M7、NMOS tube M8 and NMOS tube M12，Described Δ V_GSTemperature-compensation circuit includes: PMOS M16, PMOS M17, PMOS M18, NMOS tube M19, NMOS tube M20, error amplifier A3, resistance R6 and resistance R7；

Wherein, in described start-up circuit, the source electrode of PMOS MS1 is connected with external power source VDD, the grid of PMOS MS1 is connected with the source electrode of the drain electrode of PMOS MS1 and PMOS MS2, the grid of PMOS MS2 is connected with the drain electrode of PMOS MS2, the drain electrode of NMOS tube MS3, the grid of NMOS tube MS4, the grid of NMOS tube MS5 and the grid of NMOS tube MS6, and the source electrode of NMOS tube MS3 and the source electrode of NMOS tube MS4, the source electrode of NMOS tube MS5, the source electrode of NMOS tube MS6 and outside ground wire GND are connected；

nullThe source electrode of the source electrode of PMOS M1 and PMOS M2 in described ambipolar band-gap reference circuit、The source electrode of PMOS M3、The source electrode of PMOS M4、The source electrode of PMOS M5 and external power source VDD are connected，The drain electrode of PMOS M1 is connected with the reverse input end of the emitter stage of PNP type triode Q1 and error amplifier A1，The grid of PMOS M1 and the grid of PMOS M2、The grid of PMOS M4、The grid of PMOS M9、The grid of PMOS M13、The drain electrode of NMOS tube MS5 and the outfan of error amplifier A1 are connected，The base stage of PNP type triode Q1 and the colelctor electrode of PNP type triode Q1、The base stage of PNP type triode Q2、Colelctor electrode and the outside ground wire GND of PNP type triode Q2 are connected，The positive input of the drain electrode of PMOS M2 and error amplifier A1、The reverse input end of error amplifier A2 and resistance R1 are connected，The other end of resistance R1 is connected with the emitter stage of PNP type triode Q2，The outfan of the grid of PMOS M3 and error amplifier A2、The drain electrode of NMOS tube MS4、The grid of PMOS M5 and the grid of PMOS M6 are connected，The drain electrode of PMOS M3 is connected with positive input and the resistance R2 of error amplifier A2，The other end of resistance R2 is connected with outside ground wire GND，The drain electrode of PMOS M4 and the drain electrode of PMOS M5、Band-gap reference outfan VREF、The grid of NMOS tube MS3 and resistance R3 are connected，The other end of resistance R3 is connected with the drain electrode of PMOS M16 and resistance R4，The other end of resistance R4 and the drain electrode of PMOS M11、The drain electrode of PMOS M15 and resistance R5 are connected，The other end of resistance R5 is connected with outside ground wire GND；

nullThe source electrode of the source electrode of PMOS M6 and PMOS M9 in described piecewise linearity temperature-compensation circuit、The source electrode of PMOS M10、The source electrode of PMOS M11、The source electrode of PMOS M13、The source electrode of PMOS M14、The source electrode of PMOS M15 and external power source VDD are connected，The drain electrode of PMOS M6 and the drain electrode of NMOS tube M7、The grid of NMOS tube M7、The grid of NMOS tube M8 and the grid of NMOS tube M12 are connected，The source electrode of NMOS tube M7 and the source electrode of NMOS tube M8、Source electrode and the outside ground wire GND of NMOS tube M12 are connected，The drain electrode of PMOS M9 and the grid of PMOS M10、The drain electrode of PMOS M10、The grid of PMOS M11 and the drain electrode of NMOS tube M8 are connected，The drain electrode of PMOS M13 and the grid of PMOS M14、The drain electrode of PMOS M14、The grid of PMOS M15 and the drain electrode of NMOS tube M12 are connected；

At described Δ V_GSnullThe source electrode of the source electrode of PMOS M16 and PMOS M17 in temperature-compensation circuit、The source electrode of PMOS M18 and external power source VDD are connected，The grid of PMOS M16 and the drain electrode of NMOS tube MS6、The grid of PMOS M17、The grid of PMOS M18 and the outfan of error amplifier A3 are connected，The drain electrode of PMOS M17 and the grid of NMOS tube M19、The reverse input end of error amplifier A3 and resistance R6 are connected，The other end of resistance R6 is connected with the drain electrode of NMOS tube M19，The source electrode of NMOS tube M19 is connected with the source electrode of NMOS tube M20 and outside ground wire GND，The drain electrode of PMOS M18 is connected with positive input and the resistance R7 of error amplifier A3，The other end of resistance R7 is connected with the drain electrode of the grid of NMOS tube M20 and NMOS tube M20.

Further, in described ambipolar band-gap reference circuit, PMOS M1 and PMOS M2 has identical breadth length ratio, and PMOS M4 and PMOS M2 has identical breadth length ratio, then the drain current I of PMOS M4₄The voltage V produced on resistance R3, resistance R4 and resistance R5_PTATFor:In formula, α is the ratio of the emitter area of PNP type triode Q2 and PNP type triode Q1, and k is Boltzmann constant, and T is absolute temperature, and q is electron charge, R₁It is the resistance of resistance R1, R₃It is the resistance of resistance R3, R₄It is the resistance of resistance R4, R₅It it is the resistance of resistance R5；

PMOS M5 and PMOS M3 has identical breadth length ratio, the drain current I of PMOS M5₅The voltage V produced on resistance R3, resistance R4 and resistance R5_CTATFor:In formula, V_EB1It is the emitter base voltage of PNP type triode Q1, R₂It it is the resistance of resistance R2.

Further, in described piecewise linearity temperature-compensation circuit, PMOS M6 breadth length ratio is the β of PMOS M3 breadth length ratio₁Times, NMOS tube M7 and NMOS tube M8 has identical breadth length ratio, and PMOS M9 breadth length ratio is the β of PMOS M2 breadth length ratio₂Times, PMOS M11 breadth length ratio is the β of PMOS M10 breadth length ratio₃Times, then the drain current I of PMOS M11₁₁Resistance R5 produces voltage V_NL1For

$V_{NL1}=\left\{\begin{array}{cc}{R}_5{\mathrm{\&beta;}}_3({\mathrm{\&beta;}}_1\frac{V_{EB1}}{R_2}-{\mathrm{\&beta;}}_2\frac{kT}{{\mathrm{qR}}_1}ln\mathrm{\&alpha;})& T<T_{r1}\\ 0& T\&GreaterEqual;T_{r1}\end{array}\right.$

In formula, T_r1For reference voltage；

PMOS M13 breadth length ratio is the β of PMOS M2 breadth length ratio₄Times, NMOS tube M12 and NMOS tube M7 has identical breadth length ratio, and PMOS M15 breadth length ratio is the β of PMOS M14 breadth length ratio₅Times, then the drain current I of PMOS M15₁₅Resistance R5 produces voltage V_NL2For

$V_{NL2}=\left\{\begin{array}{cc}{R}_5{\mathrm{\&beta;}}_5({\mathrm{\&beta;}}_1\frac{V_{EB1}}{R_2}-{\mathrm{\&beta;}}_4\frac{kT}{{\mathrm{qR}}_1}ln\mathrm{\&alpha;})& T<T_{r2}\\ 0& T\&GreaterEqual;T_{r2}\end{array}\right.$

In formula, T_r2For reference voltage, and T_r2< T_r1。

Further, described Δ V_GSIn temperature-compensation circuit, PMOS M17 and PMOS M18 has identical breadth length ratio, and PMOS M17 and PMOS M18 is all operated in saturation region, and NMOS tube M20 breadth length ratio is the β of NMOS tube M19 breadth length ratio₇Again, and NMOS tube M19 and NMOS tube M20 is all operated in sub-threshold region, and PMOS M16 breadth length ratio is the β of PMOS M18 breadth length ratio₆Times, electric current I₁₆The pressure drop V produced on resistance R4 and resistance R5_{BGR_MOS}For

$V_{BGR\_MOS}={\mathrm{\&beta;}}_6\frac{k(R_4+R_5){\mathrm{ln\&beta;}}_7}{{\mathrm{qR}}_7}(ET+{\mathrm{FT}}^2+{\mathrm{GT}}^3)$

In formula, R₇Being the resistance of resistance R7, E, F and G are positive constant.

Further, the output voltage V of described high-order temperature compensation bandgap reference circuit_REFFor

V_REF=(V_CTAT+V_PTAT)+(V_{BGR_MOS}+V_NL1+V_NL2)。

Compared with prior art, the application provides the technique effect that has of technical scheme or advantage be: the compensation circuit voltage V provided by piecewise linearity temperature-compensation circuit 3_NL1And V_NL2、ΔV_GSThe Δ V that temperature-compensation circuit 4 provides_GSTemperature-compensated voltage V_{BGR_MOS}It is incorporated in ambipolar band-gap reference 2, obtains high-order temperature compensated reference voltage, thus obtaining the reference voltage of less temperature coefficient.

Accompanying drawing explanation

Fig. 1 is the principle schematic of conventional first order band-gap reference circuit；

Fig. 2 is the structure chart of the high-order temperature compensation bandgap reference circuit of the present invention；

Fig. 3 is the circuit diagram of the high-order temperature compensation bandgap reference circuit of the present invention；

Fig. 4 is single order band-gap reference circuit output voltage curve synoptic diagram；

Fig. 5 is for introducing Δ V_GSTemperature-compensated voltage V_{BGR_MOS}After output voltage curve synoptic diagram；

Fig. 6 is for introducing Δ V_GSTemperature-compensated voltage V_{BGR_MOS}And piecewise linearity temperature-compensated voltage V_NL1After output voltage curve synoptic diagram；

Fig. 7 is the output voltage curve chart of the high-order temperature compensation bandgap reference circuit of the present invention；

Fig. 8 is the output voltage temperature characterisitic analogous diagram of the high-order temperature compensation bandgap reference circuit of the present invention.

Detailed description of the invention

The embodiment of the present application is by providing a kind of high-order temperature compensation bandgap reference circuit, by the temperature section linear compensation voltage of described piecewise linearity temperature-compensation circuit generation and described Δ V_GSThe Δ V that temperature-compensation circuit produces_GSTemperature-compensated voltage joins in the low temperature coefficient with gap reference voltage that described ambipolar band-gap reference circuit produces, thus obtaining high-order temperature compensated reference voltage, significantly reduces the temperature coefficient of band-gap reference circuit output voltage.

In order to be better understood from technique scheme, below in conjunction with Figure of description and specific embodiment, technique scheme is described in detail.

Embodiment

A kind of high-order temperature compensation bandgap reference circuit, as in figure 2 it is shown, include start-up circuit 1, ambipolar band-gap reference circuit 2, piecewise linearity temperature-compensation circuit 3 and Δ V_GSTemperature-compensation circuit 4, wherein, the enabling signal outfan of described start-up circuit 1 connects enabling signal input and the Δ V of described ambipolar band-gap reference circuit 2 respectively_GSThe enabling signal input of temperature-compensation circuit 4, the signal output part of described ambipolar band-gap reference circuit 2 connects the voltage signal inputs of described start-up circuit 1 and the signal input part of described piecewise linearity temperature-compensation circuit 3 respectively, described start-up circuit 1 makes band-gap reference circuit normal operation, described ambipolar band-gap reference circuit 2 produces the band gap reference voltage of low-temperature coefficient, described piecewise linearity temperature-compensation circuit 3 produces temperature section linear compensation voltage, described Δ V_GSTemperature-compensation circuit 4 produces Δ V_GSTemperature-compensated voltage, described piecewise linearity temperature-compensation circuit 3 and Δ V_GSDescribed ambipolar band-gap reference circuit 2 is carried out temperature-compensating by temperature-compensation circuit 4, by temperature section linear compensation voltage and the described Δ V of the generation of described piecewise linearity temperature-compensation circuit 3_GSThe Δ V that temperature-compensation circuit 4 produces_GSTemperature-compensated voltage joins in the low temperature coefficient with gap reference voltage that described ambipolar band-gap reference circuit 2 produces.

nullAs the preferred technical scheme of one，As shown in Figure 3，Described start-up circuit 1 includes: PMOS MS1、PMOS MS2、NMOS tube MS3、NMOS tube MS4、NMOS tube MS5 and NMOS tube MS6，Described ambipolar band-gap reference circuit 2 includes: PMOS M1、PMOS M2、PMOS M3、PMOS M4、PMOS M5、Error amplifier A1、Error amplifier A2、PNP type triode Q1、PNP type triode Q2、Resistance R1、Resistance R2、Resistance R3、Resistance R4 and resistance R5，Described piecewise linearity temperature-compensation circuit 3 includes: PMOS M6、PMOS M9、PMOS M10、PMOS M11、PMOS M13、PMOS M14、PMOS M15、NMOS tube M7、NMOS tube M8 and NMOS tube M12，Described Δ V_GSTemperature-compensation circuit 4 includes: PMOS M16, PMOS M17, PMOS M18, NMOS tube M19, NMOS tube M20, error amplifier A3, resistance R6 and resistance R7；

Wherein, in described start-up circuit 1, the source electrode of PMOS MS1 is connected with external power source VDD, the grid of PMOS MS1 is connected with the source electrode of the drain electrode of PMOS MS1 and PMOS MS2, the grid of PMOS MS2 is connected with the drain electrode of PMOS MS2, the drain electrode of NMOS tube MS3, the grid of NMOS tube MS4, the grid of NMOS tube MS5 and the grid of NMOS tube MS6, and the source electrode of NMOS tube MS3 and the source electrode of NMOS tube MS4, the source electrode of NMOS tube MS5, the source electrode of NMOS tube MS6 and outside ground wire GND are connected；

nullThe source electrode of the source electrode of PMOS M1 and PMOS M2 in described ambipolar band-gap reference circuit 2、The source electrode of PMOS M3、The source electrode of PMOS M4、The source electrode of PMOS M5 and external power source VDD are connected，The drain electrode of PMOS M1 is connected with the reverse input end of the emitter stage of PNP type triode Q1 and error amplifier A1，The grid of PMOS M1 and the grid of PMOS M2、The grid of PMOS M4、The grid of PMOS M9、The grid of PMOS M13、The drain electrode of NMOS tube MS5 and the outfan of error amplifier A1 are connected，The base stage of PNP type triode Q1 and the colelctor electrode of PNP type triode Q1、The base stage of PNP type triode Q2、Colelctor electrode and the outside ground wire GND of PNP type triode Q2 are connected，The positive input of the drain electrode of PMOS M2 and error amplifier A1、The reverse input end of error amplifier A2 and resistance R1 are connected，The other end of resistance R1 is connected with the emitter stage of PNP type triode Q2，The outfan of the grid of PMOS M3 and error amplifier A2、The drain electrode of NMOS tube MS4、The grid of PMOS M5 and the grid of PMOS M6 are connected，The drain electrode of PMOS M3 is connected with positive input and the resistance R2 of error amplifier A2，The other end of resistance R2 is connected with outside ground wire GND，The drain electrode of PMOS M4 and the drain electrode of PMOS M5、Band-gap reference outfan VREF、The grid of NMOS tube MS3 and resistance R3 are connected，The other end of resistance R3 is connected with the drain electrode of PMOS M16 and resistance R4，The other end of resistance R4 and the drain electrode of PMOS M11、The drain electrode of PMOS M15 and resistance R5 are connected，The other end of resistance R5 is connected with outside ground wire GND；

nullThe source electrode of the source electrode of PMOS M6 and PMOS M9 in described piecewise linearity temperature-compensation circuit 3、The source electrode of PMOS M10、The source electrode of PMOS M11、The source electrode of PMOS M13、The source electrode of PMOS M14、The source electrode of PMOS M15 and external power source VDD are connected，The drain electrode of PMOS M6 and the drain electrode of NMOS tube M7、The grid of NMOS tube M7、The grid of NMOS tube M8 and the grid of NMOS tube M12 are connected，The source electrode of NMOS tube M7 and the source electrode of NMOS tube M8、Source electrode and the outside ground wire GND of NMOS tube M12 are connected，The drain electrode of PMOS M9 and the grid of PMOS M10、The drain electrode of PMOS M10、The grid of PMOS M11 and the drain electrode of NMOS tube M8 are connected，The drain electrode of PMOS M13 and the grid of PMOS M14、The drain electrode of PMOS M14、The grid of PMOS M15 and the drain electrode of NMOS tube M12 are connected；

At described Δ V_GSnullThe source electrode of the source electrode of PMOS M16 and PMOS M17 in temperature-compensation circuit 4、The source electrode of PMOS M18 and external power source VDD are connected，The grid of PMOS M16 and the drain electrode of NMOS tube MS6、The grid of PMOS M17、The grid of PMOS M18 and the outfan of error amplifier A3 are connected，The drain electrode of PMOS M17 and the grid of NMOS tube M19、The reverse input end of error amplifier A3 and resistance R6 are connected，The other end of resistance R6 is connected with the drain electrode of NMOS tube M19，The source electrode of NMOS tube M19 is connected with the source electrode of NMOS tube M20 and outside ground wire GND，The drain electrode of PMOS M18 is connected with positive input and the resistance R7 of error amplifier A3，The other end of resistance R7 is connected with the drain electrode of the grid of NMOS tube M20 and NMOS tube M20.

In described ambipolar band-gap reference circuit 2, error amplifier A1 makes the voltage of the input node A and input node B of error amplifier equal, i.e. V_A=V_B=V_EB1, wherein, V_EB1It is the emitter base voltage of PNP type triode Q1, V_AIt is the voltage of node A, V_BIt is the voltage of node B.PMOS M1 and PMOS M2 has identical breadth length ratio, then the drain current I of PMOS M2₂ForIn formula, α is the ratio of the emitter area of PNP type triode Q2 and PNP type triode Q1, and k is Boltzmann constant, and T is absolute temperature, and q is electron charge, R₁It is the resistance of resistance R1, and all of resistance is all that identical material realizes.PMOS M4 and PMOS M2 have an identical breadth length ratio, thus the drain current I of PMOS M4₄For I₄=I₂, then electric current I₄Resistance R3, resistance R4 and resistance R5 produce pressure drop V_PTATFor:

$V_{PTAT}=\frac{R_3+R_4+R_5}{R_1}\frac{kT}{q}ln\mathrm{\&alpha;}---\left(1\right)$

In formula, R₃It is the resistance of resistance R3, R₄It is the resistance of resistance R4, R₅It is the resistance of resistance R5, by the known voltage V of formula (1)_PTATThere is positive temperature coefficient.

Error amplifier A2 makes the voltage of the input node C of the input node B and error amplifier A2 of error amplifier A1 equal, i.e. V_B=V_C=V_EB1, wherein V_CBeing the voltage of node C, the input node B of described error amplifier A1 is the input node of described error amplifier A2 simultaneously, the drain current I of PMOS M3₃ForIn formula, R₂It is resistance R₂Resistance.PMOS M5 and PMOS M3 have an identical breadth length ratio, thus the drain current I of PMOS M5₅For I₅=I₃, then electric current I₅Resistance R3, resistance R4 and resistance R5 produce pressure drop V_CTATFor:

$V_{CTAT}=\frac{V_{EB1}}{R_2}(R_3+R_4+R_5)---\left(2\right)$

By the known voltage V of formula (2)_CTATThere is negative temperature coefficient.

The present invention is in order to compensate V_EB1The temperature high-order nonlinear item of low-temperature region, adopts piecewise linearity temperature-compensation circuit 3.PMOS M6 breadth length ratio is the β of PMOS M3 breadth length ratio₁Times, NMOS tube M7 and NMOS tube M8 has identical breadth length ratio, then the drain current I of NMOS tube M8₈For I₈=β₁I₃.PMOS M9 breadth length ratio is the β of PMOS M2 breadth length ratio₂Times, then the drain current I of PMOS M9₉For I₉=β₂I₂.By (1), (2) formula it can be seen that at temperature T be more than or equal to reference temperature T_r1Under condition, by parameters optimization β₁With β₂, the drain current I of PMOS M10₁₀There is I₁₀=I₈-I₉=β₁I₃-β₂I₂=0.PMOS M11 breadth length ratio is the β of PMOS M10 breadth length ratio₃Times, then the drain current I of PMOS M11₁₁The pressure drop V produced on resistance R5_NL1For:

$V_{NL1}=\left\{\begin{array}{cc}{R}_5{\mathrm{\&beta;}}_3({\mathrm{\&beta;}}_1\frac{V_{EB1}}{R_2}-{\mathrm{\&beta;}}_2\frac{kT}{{\mathrm{qR}}_1}ln\mathrm{\&alpha;})& T<T_{r1}\\ 0& T\&GreaterEqual;T_{r1}\end{array}\right.---\left(3\right)$

In formula, R₅It is the resistance of resistance R5, by formula (3) it can be seen that the drain current I of PMOS M11₁₁The pressure drop V produced on resistance R5_NL1There is temperature section linear characteristic.

PMOS M13 breadth length ratio is the β of PMOS M2 breadth length ratio₄Times, NMOS tube M12 and NMOS tube M7 have identical breadth length ratio, by formula (1), (2) it can be seen that at temperature T be more than or equal to reference temperature T_r2Under condition, by parameters optimization β₄, the drain current I of PMOS M14₁₄There is I₁₄=I₁₂-I₁₃=β₁I₃-β₄I₂=0, wherein T_r2< T_r1.PMOS M15 breadth length ratio is the β of PMOS M14 breadth length ratio₅Times, then the drain current I of PMOS M15₁₅The pressure drop V produced on resistance R5_NL2For:

$V_{NL2}=\left\{\begin{array}{cc}{R}_5{\mathrm{\&beta;}}_5({\mathrm{\&beta;}}_1\frac{V_{EB1}}{R_2}-{\mathrm{\&beta;}}_4\frac{kT}{{\mathrm{qR}}_1}ln\mathrm{\&alpha;})& T<T_{r2}\\ 0& T\&GreaterEqual;T_{r2}\end{array}\right.---\left(4\right)$

By formula (4) it can be seen that the drain current I of PMOS M15₁₅At the resistance R5 pressure drop V produced_NL2There is temperature section linear characteristic.

The present invention is for compensating V_EB1Temperature high-order nonlinear item, adopt Δ V_GSTemperature-compensation circuit 4.PMOS M17 and PMOS M18 has identical breadth length ratio, and PMOS M17 and PMOS M18 is all operated in saturation region.NMOS tube M19 and NMOS tube M20 is all operated in sub-threshold region, and is operated in the drain current I of sub-threshold region NMOS tube_DFor:

$I_D={\mathrm{\&mu;}}_n{C}_{ox}\frac{W}{mL}{\left(\frac{nkT}{q}\right)}^2{e}^{\frac{q}{nkT}(V_{GS}-V_{TH}-\frac{nkT}{q})}\&lsqb;1-e^{(-\frac{{\mathrm{mqV}}_{DS}}{nkT})}\&rsqb;---\left(5\right)$

In formula, μ_nIt is electron mobility, C_oxIt is unit are gate oxide capacitance, V_THIt is the threshold voltage of metal-oxide-semiconductor, V_GSIt is the gate source voltage of metal-oxide-semiconductor, V_DSIt is the drain-source voltage of metal-oxide-semiconductor,Being the breadth length ratio of metal-oxide-semiconductor, m and n is the parameter relevant to technique.Work as V_DS> 200mV, formula (5) can be approximately:

$I_D={\mathrm{\&mu;}}_n{C}_{ox}\frac{W}{mL}{\left(\frac{nkT}{q}\right)}^2{e}^{\frac{q}{nkT}(V_{GS}-V_{TH}\frac{nkT}{q})}---\left(6\right)$

NMOS tube M20 breadth length ratio is the β of NMOS tube M19 breadth length ratio₇Times, PMOS M16 breadth length ratio is the β of PMOS M18 breadth length ratio₆Times, then the drain current I of PMOS M16₁₆For:

$I_{16}={\mathrm{\&beta;}}_6\frac{nkT}{{\mathrm{qR}}_7}{\mathrm{ln\&beta;}}_7---\left(7\right)$

It is true that in formula (7), R₇Being the resistance of resistance R7, the relation of n and temperature T is n (T)=E+FT+GT², wherein, E, F and G are positive constant.Thus electric current I₁₆The pressure drop V produced on resistance R4 and resistance R5_{BGR_MOS}For:

$V_{BGR\_MOS}={\mathrm{\&beta;}}_6\frac{k(R_4+R_5){\mathrm{ln\&beta;}}_7}{{\mathrm{qR}}_7}(ET+{\mathrm{FT}}^2+{\mathrm{GT}}^3)---\left(8\right)$

By formula (1)-Shi (8) it can be seen that the output voltage V of high-order temperature compensation bandgap reference circuit outfan VREF_REFFor:

V_REF=(V_CTAT+V_PTAT)+(V_{BGR_MOS}+V_NL1+V_NL2)(9)

By formula (9) it can be seen that band-gap reference output voltage V_REFIt is divided into two factors.One factor is (V_CTAT+V_PTAT), it passes through parameters optimization α and resistance R₁、R₂, it is achieved single order temperature-compensating, obtain single order bandgap voltage reference；Another factor is (V_{BGR_MOS}+V_NL1+V_NL2), it compensates V_EB1Temperature high-order nonlinear item, obtain high-order temperature compensation bandgap reference voltage, bandgap voltage reference curve shown in Fig. 7 can be obtained.Wherein, Fig. 4 is single order band-gap reference output voltage curve synoptic diagram, and Fig. 5 is for introducing Δ V_GSTemperature-compensated voltage V_{BGR_MOS}After output voltage curve synoptic diagram, Fig. 6 for introduce Δ V_GSTemperature-compensated voltage V_{BGR_MOS}And piecewise linearity temperature-compensated voltage V_NL1After output voltage curve synoptic diagram, Fig. 7 for introduce Δ V_GSTemperature-compensated voltage V_{BGR_MOS}And piecewise linearity temperature-compensated voltage V_NL1、V_NL2After output voltage curve synoptic diagram, i.e. the output voltage schematic diagram of high-order temperature compensation bandgap reference circuit.

By formula (1)-Shi (9) and Fig. 7 it can be seen that the output voltage V of the high-order temperature compensation bandgap reference circuit of the present invention_REFTemperature characteristics can be divided into following three region:

Region 1, temperature T is more than reference temperature T_r1, i.e. T > T_r1.In this region, V_NL1And V_NL2It is zero, the output voltage V of band-gap reference circuit_REFBy V_CTAT、V_PTATAnd V_{BGR_MOS}Contribution, then the output voltage V of band-gap reference circuit_REFFor:

V_REF=V_CTAT+V_PTAT+V_{BGR_MOS}(10)

Region 2, temperature T is more than reference temperature T_r2, less than reference temperature T_r1, i.e. T_r2< T < T_r1.At this region, V_NL2It is zero, the output voltage V of band-gap reference circuit_REFBy V_CTAT、V_PTAT、V_{BGR_MOS}And V_NL1Contribution, then the output voltage V of band-gap reference circuit_REFFor:

V_REF=V_CTAT+V_PTAT+V_{BGR_MOS}+V_NL1(11)

Region 3, temperature T is less than reference temperature T_r2, i.e. T < T_r2.This region, the output voltage V of band-gap reference circuit_REFBy V_CTAT、V_PTAT、V_{BGR_MOS}、V_NL1And V_NL2Contribution, then the output voltage V of band-gap reference circuit_REF

For:

V_REF=V_CTAT+V_PTAT+V_{BGR_MOS}+V_NL1+V_NL2(12)

Fig. 8 is the output voltage V of the high-order temperature compensation bandgap reference circuit of the present invention_REFTemperature characterisitic simulation curve, wherein abscissa is temperature, and vertical coordinate is band-gap reference output voltage.Simulation result shows, is-55 DEG C～125 DEG C in temperature range, and this high-order temperature compensated band-gap reference circuit has reached the temperature coefficient of 0.6457ppm/ DEG C.

When start-up circuit 1 starts, due to band-gap reference output voltage V_REFCompare relatively low, NMOS tube MS3 ends, the grid potential making NMOS tube MS4, NMOS tube MS5 and NMOS tube MS6 is high potential, so that the grid of PMOS M1, PMOS M2, PMOS M3, PMOS M17, PMOS M18 is electronegative potential, this be formed for PMOS M1 to PNP type triode Q1, PMOS M2 to resistance R1 to PNP type triode Q2, PMOS M3 is to resistance R2, PMOS M17 to resistance R6 to NMOS tube M19, PMOS M18 is to resistance R7 to NMOS tube M20 current path, make circuit depart from zero state, enter duty.But, V_REFWhen rising to more than NMOS tube threshold voltage, NMOS tube MS3 turns on, the grid making NMOS tube MS4, NMOS tube MS5 and NMOS tube MS6 is electronegative potential and is operated in cut-off region so that band-gap reference reference circuit below is no longer produced impact by start-up circuit 1, and startup completes.

In above-described embodiment of the application, by providing a kind of high-order temperature compensation bandgap reference circuit, including start-up circuit, ambipolar band-gap reference circuit, piecewise linearity temperature-compensation circuit and Δ V_GSTemperature-compensation circuit, wherein, the enabling signal outfan of described start-up circuit connects enabling signal input and the Δ V of described ambipolar band-gap reference circuit respectively_GSThe enabling signal input of temperature-compensation circuit, the signal output part of described ambipolar band-gap reference circuit connects the voltage signal inputs of described start-up circuit and the signal input part of described piecewise linearity temperature-compensation circuit respectively, described start-up circuit makes high-order temperature compensation bandgap reference circuit normal operation, described ambipolar band-gap reference circuit produces the band gap reference voltage of low-temperature coefficient, described piecewise linearity temperature-compensation circuit and Δ V_GSDescribed ambipolar band-gap reference circuit is carried out temperature-compensating by temperature-compensation circuit, significantly reduces the temperature coefficient of band-gap reference circuit output voltage.

It should be noted that; described above is not limitation of the present invention; the present invention is also not limited to the example above, change, modified, interpolation or the replacement that those skilled in the art are made in the essential scope of the present invention, also should belong to protection scope of the present invention.

Claims (6)

1. a high-order temperature compensation bandgap reference circuit, it is characterised in that include start-up circuit (1), ambipolar band-gap reference circuit (2), piecewise linearity temperature-compensation circuit (3) and Δ V_GSTemperature-compensation circuit (4), wherein, the enabling signal outfan of described start-up circuit (1) connects the enabling signal input of described ambipolar band-gap reference circuit (2) and described Δ V respectively_GSThe enabling signal input of temperature-compensation circuit (4), the signal output part of described ambipolar band-gap reference circuit (2) connects the voltage signal inputs of described start-up circuit (1) and the signal input part of described piecewise linearity temperature-compensation circuit (3) respectively, described start-up circuit (1) makes band-gap reference circuit normal operation, described ambipolar band-gap reference circuit (2) produces the band gap reference voltage of low-temperature coefficient, described piecewise linearity temperature-compensation circuit (3) produces temperature section linear compensation voltage, described Δ V_GSTemperature-compensation circuit (4) produces Δ V_GSTemperature-compensated voltage, described piecewise linearity temperature-compensation circuit (3) and Δ V_GSDescribed ambipolar band-gap reference circuit (2) is carried out temperature-compensating by temperature-compensation circuit (4), the temperature section linear compensation voltage produced by described piecewise linearity temperature-compensation circuit (3) and described Δ V_GSThe Δ V that temperature-compensation circuit (4) produces_GSTemperature-compensated voltage joins in the band gap reference voltage that described ambipolar band-gap reference circuit (2) produces.

2. high-order temperature compensation bandgap reference circuit according to claim 1, it is characterised in that

nullDescribed start-up circuit (1) including: PMOS MS1、PMOS MS2、NMOS tube MS3、NMOS tube MS4、NMOS tube MS5 and NMOS tube MS6，Described ambipolar band-gap reference circuit (2) including: PMOS M1、PMOS M2、PMOS M3、PMOS M4、PMOS M5、Error amplifier A1、Error amplifier A2、PNP type triode Q1、PNP type triode Q2、Resistance R1、Resistance R2、Resistance R3、Resistance R4 and resistance R5，Described piecewise linearity temperature-compensation circuit (3) including: PMOS M6、PMOS M9、PMOS M10、PMOS M11、PMOS M13、PMOS M14、PMOS M15、NMOS tube M7、NMOS tube M8 and NMOS tube M12，Described Δ V_GSTemperature-compensation circuit (4) including: PMOS M16, PMOS M17, PMOS M18, NMOS tube M19, NMOS tube M20, error amplifier A3, resistance R6 and resistance R7；

Wherein, in described start-up circuit (1), the source electrode of PMOS MS1 is connected with external power source VDD, the grid of PMOS MS1 is connected with the source electrode of the drain electrode of PMOS MS1 and PMOS MS2, the grid of PMOS MS2 is connected with the drain electrode of PMOS MS2, the drain electrode of NMOS tube MS3, the grid of NMOS tube MS4, the grid of NMOS tube MS5 and the grid of NMOS tube MS6, and the source electrode of NMOS tube MS3 and the source electrode of NMOS tube MS4, the source electrode of NMOS tube MS5, the source electrode of NMOS tube MS6 and outside ground wire GND are connected；

nullThe source electrode of the source electrode of PMOS M1 and PMOS M2 in described ambipolar band-gap reference circuit (2)、The source electrode of PMOS M3、The source electrode of PMOS M4、The source electrode of PMOS M5 and external power source VDD are connected，The drain electrode of PMOS M1 is connected with the reverse input end of the emitter stage of PNP type triode Q1 and error amplifier A1，The grid of PMOS M1 and the grid of PMOS M2、The grid of PMOS M4、The grid of PMOS M9、The grid of PMOS M13、The drain electrode of NMOS tube MS5 and the outfan of error amplifier A1 are connected，The base stage of PNP type triode Q1 and the colelctor electrode of PNP type triode Q1、The base stage of PNP type triode Q2、Colelctor electrode and the outside ground wire GND of PNP type triode Q2 are connected，The positive input of the drain electrode of PMOS M2 and error amplifier A1、The reverse input end of error amplifier A2 and resistance R1 are connected，The other end of resistance R1 is connected with the emitter stage of PNP type triode Q2，The outfan of the grid of PMOS M3 and error amplifier A2、The drain electrode of NMOS tube MS4、The grid of PMOS M5 and the grid of PMOS M6 are connected，The drain electrode of PMOS M3 is connected with positive input and the resistance R2 of error amplifier A2，The other end of resistance R2 is connected with outside ground wire GND，The drain electrode of PMOS M4 and the drain electrode of PMOS M5、Band-gap reference outfan VREF、The grid of NMOS tube MS3 and resistance R3 are connected，The other end of resistance R3 is connected with the drain electrode of PMOS M16 and resistance R4，The other end of resistance R4 and the drain electrode of PMOS M11、The drain electrode of PMOS M15 and resistance R5 are connected，The other end of resistance R5 is connected with outside ground wire GND；

nullThe source electrode of the source electrode of PMOS M6 and PMOS M9 in described piecewise linearity temperature-compensation circuit (3)、The source electrode of PMOS M10、The source electrode of PMOS M11、The source electrode of PMOS M13、The source electrode of PMOS M14、The source electrode of PMOS M15 and external power source VDD are connected，The drain electrode of PMOS M6 and the drain electrode of NMOS tube M7、The grid of NMOS tube M7、The grid of NMOS tube M8 and the grid of NMOS tube M12 are connected，The source electrode of NMOS tube M7 and the source electrode of NMOS tube M8、Source electrode and the outside ground wire GND of NMOS tube M12 are connected，The drain electrode of PMOS M9 and the grid of PMOS M10、The drain electrode of PMOS M10、The grid of PMOS M11 and the drain electrode of NMOS tube M8 are connected，The drain electrode of PMOS M13 and the grid of PMOS M14、The drain electrode of PMOS M14、The grid of PMOS M15 and the drain electrode of NMOS tube M12 are connected；

At described Δ V_GSnullThe source electrode of the source electrode of PMOS M16 and PMOS M17 in temperature-compensation circuit (4)、The source electrode of PMOS M18 and external power source VDD are connected，The grid of PMOS M16 and the drain electrode of NMOS tube MS6、The grid of PMOS M17、The grid of PMOS M18 and the outfan of error amplifier A3 are connected，The drain electrode of PMOS M17 and the grid of NMOS tube M19、The reverse input end of error amplifier A3 and resistance R6 are connected，The other end of resistance R6 is connected with the drain electrode of NMOS tube M19，The source electrode of NMOS tube M19 is connected with the source electrode of NMOS tube M20 and outside ground wire GND，The drain electrode of PMOS M18 is connected with positive input and the resistance R7 of error amplifier A3，The other end of resistance R7 is connected with the drain electrode of the grid of NMOS tube M20 and NMOS tube M20.

3. high-order temperature compensation bandgap reference circuit according to claim 2, it is characterized in that, in described ambipolar band-gap reference circuit (2), PMOS M1 and PMOS M2 has identical breadth length ratio, PMOS M4 and PMOS M2 has identical breadth length ratio, then the drain current I of PMOS M4₄The voltage V produced on resistance R3, resistance R4 and resistance R5_PTATFor:In formula, α is the ratio of the emitter area of PNP type triode Q2 and PNP type triode Q1, and k is Boltzmann constant, and T is absolute temperature, and q is electron charge, R₁It is the resistance of resistance R1, R₃It is the resistance of resistance R3, R₄It is the resistance of resistance R4, R₅It it is the resistance of resistance R5；

PMOS M5 and PMOS M3 has identical breadth length ratio, the drain current I of PMOS M5₅The voltage V produced on resistance R3, resistance R4 and resistance R5_CTATFor:In formula, V_EB1It is the emitter base voltage of PNP type triode Q1, R₂It it is the resistance of resistance R2.

4. high-order temperature compensation bandgap reference circuit according to claim 2, it is characterised in that in described piecewise linearity temperature-compensation circuit (3), PMOS M6 breadth length ratio is the β of PMOS M3 breadth length ratio₁Times, NMOS tube M7 and NMOS tube M8 has identical breadth length ratio, and PMOS M9 breadth length ratio is the β of PMOS M2 breadth length ratio₂Times, PMOS M11 breadth length ratio is the β of PMOS M10 breadth length ratio₃Times, then the drain current I of PMOS M11₁₁Resistance R5 produces voltage V_NL1For

$V_{NL1}=\left\{\begin{array}{cc}{R}_5{\mathrm{\&beta;}}_3({\mathrm{\&beta;}}_1\frac{V_{EB1}}{R_2}-{\mathrm{\&beta;}}_2\frac{kT}{{\mathrm{qR}}_1}ln\mathrm{\&alpha;})& T<T_{r1}\\ 0& T\&GreaterEqual;T_{r1}\end{array}\right.$

In formula, T_r1For reference voltage；

PMOS M13 breadth length ratio is the β of PMOS M2 breadth length ratio₄Times, NMOS tube M12 and NMOS tube M7 has identical breadth length ratio, and PMOS M15 breadth length ratio is the β of PMOS M14 breadth length ratio₅Times, then the drain current I of PMOS M15₁₅Resistance R5 produces voltage V_NL2For

$V_{NL2}=\left\{\begin{array}{cc}{R}_5{\mathrm{\&beta;}}_5({\mathrm{\&beta;}}_1\frac{V_{EB1}}{R_2}-{\mathrm{\&beta;}}_4\frac{kT}{{\mathrm{qR}}_1}ln\mathrm{\&alpha;})& T<T_{r2}\\ 0& T\&GreaterEqual;T_{r2}\end{array}\right.$

In formula, T_r2For reference voltage, and T_r2< T_r1。

5. high-order temperature compensation bandgap reference circuit according to claim 2, it is characterised in that described Δ V_GSIn temperature-compensation circuit (4), PMOS M17 and PMOS M18 has identical breadth length ratio, and PMOS M17 and PMOS M18 is all operated in saturation region, and NMOS tube M20 breadth length ratio is the β of NMOS tube M19 breadth length ratio₇Again, and NMOS tube M19 and NMOS tube M20 is all operated in sub-threshold region, and PMOS M16 breadth length ratio is the β of PMOS M18 breadth length ratio₆Times, electric current I₁₆The pressure drop V produced on resistance R4 and resistance R5_{BGR_MOS}For

$V_{BGR\_MOS}={\mathrm{\&beta;}}_6\frac{k(R_4+R_5){\mathrm{ln\&beta;}}_7}{{\mathrm{qR}}_7}(ET+{\mathrm{FT}}^2+{\mathrm{GT}}^3)$

In formula, R₇Being the resistance of resistance R7, E, F and G are positive constant.

6. high-order temperature compensation bandgap reference circuit according to claim 2, it is characterised in that the output voltage V of described high-order temperature compensation bandgap reference circuit_REFFor

V_REF=(V_CTAT+V_PTAT)+(V_{BGR_MOS}+V_NL1+V_NL2)。