CN106843358A - A kind of high PSRR whole CMOS reference voltage source - Google Patents

A kind of high PSRR whole CMOS reference voltage source Download PDF

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CN106843358A
CN106843358A CN201710170849.7A CN201710170849A CN106843358A CN 106843358 A CN106843358 A CN 106843358A CN 201710170849 A CN201710170849 A CN 201710170849A CN 106843358 A CN106843358 A CN 106843358A
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pmos
circuit
nmos tube
grid
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CN106843358B (en
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岳宏卫
龚全熙
朱智勇
徐卫林
吴超飞
孙晓菲
汤寒雪
邓进丽
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Guilin University of Electronic Technology
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation

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  • Electromagnetism (AREA)
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  • Automation & Control Theory (AREA)
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Abstract

The present invention discloses a kind of high PSRR whole CMOS reference voltage source, including reference voltage source, and the reference voltage source includes start-up circuit, current source circuit and temperature-compensation circuit；The output end of start-up circuit connects the input of current source circuit, and the output end of current source circuit connects the input of temperature-compensation circuit, and the output end of temperature-compensation circuit forms the output end of whole reference voltage source.The present invention produces the reference current of na magnitude using the working characteristics for being operated in sub-threshold region metal-oxide-semiconductor, and power supply noise is suppressed using common-source common-gate current mirror.Additionally, the present invention not only has chip area small, low in energy consumption, only nanowatt magnitude；And with high PSRR, the advantage of Low Drift Temperature coefficient and Low line regulation, and without using resistance, diode and triode, it is compatible with standard CMOS process, chip area is effectively reduced, and reduce production cost.

Description

A kind of high PSRR whole CMOS reference voltage source
Technical field
The present invention relates to technical field of integrated circuits, and in particular to a kind of high PSRR whole CMOS reference voltage source.
Background technology
Reference voltage source is an important module in Digital Analog Hybrid Circuits and analog hybrid, is usually applied to Voltage management chip, digital analog converter (DAC), analog-digital converter (ADC) and phaselocked loop (PLL), low pressure difference linear voltage regulator Etc. (LDO) in circuit, reference voltage source provides DC reference voltage for system.In high precision, the reference voltage source of high stability is The necessary unit of high performance analog integrated circuit.In view of having low-temperature coefficient, high PSRR and energy and standard CMOS The advantages of technique is mutually compatible so that CMOS reference voltage source circuits obtain extensive research and apply, and it provides one for system The individual DC voltage or electric current for being influenceed very little by supply voltage, technological parameter and temperature change, its performance has directly influenced and has been The precision and stability of system.
With the further complication of IC system, for Analogous Integrated Electronic Circuits basic module, such as ADC, DAC, LDO Precision and rate request higher is proposed Deng circuit, this allows for proposing the CMOS reference voltage sources of Embedded higher Requirement.Additionally, CMOS reference voltage sources are needing to meet low supply voltage, high accuracy, low-power consumption, height according to different applications PSRR (PSRR) and low-voltage regulation (LS) etc. are different to be required.Therefore, research and design meets different performance requirement The CMOS reference voltage sources of different circuit structures have realistic meaning and practical value.
The content of the invention
The technical problems to be solved by the invention are big existing reference voltage source chip areas, and power consumption is high, and power supply suppression System is than relatively low problem, there is provided a kind of high PSRR whole CMOS reference voltage source.
To solve the above problems, the present invention is achieved by the following technical solutions：
A kind of high PSRR whole CMOS reference voltage source, including reference voltage source, the reference voltage source include starting Circuit, current source circuit and temperature-compensation circuit；The output end of start-up circuit connects the input of current source circuit, current source electricity The output end on road connects the input of temperature-compensation circuit, and the output end of temperature-compensation circuit forms the defeated of whole reference voltage source Go out end；
Start-up circuit, helps a reference source to break away from degeneracy bias point, into normal operating conditions；
Current source circuit, using sub-threshold region metal-oxide-semiconductor working characteristics is operated in, produces the reference current of na magnitude；Adopt With common-source common-gate current mirror, suppress power supply noise；Using the electricity being operated in during the metal-oxide-semiconductor of linear zone replaces traditional benchmark voltage source Resistance, on the basis of voltage generation circuit provide current offset；
Temperature-compensation circuit, it is poor using different metal-oxide-semiconductor formation gate source voltages, by mutually regulation, one is obtained with temperature The unrelated reference voltage of degree.
In such scheme, the metal-oxide-semiconductor for forming gate source voltage difference is the metal-oxide-semiconductor of 1.8V and the metal-oxide-semiconductor of 3.3V.
In such scheme, start-up circuit includes PMOS M1、M2、M3, NMOS tube M4、M5, and electric capacity C1；PMOS M1With M3Source electrode be connected to power vd D；Electric capacity C1Bottom crown and NMOS tube M4And M5Source electrode be connected to ground GND；PMOS M1's Grid and drain electrode and PMOS M2Source electrode be connected；PMOS M2Grid and drain electrode, PMOS M3Grid, NMOS tube M4 Grid and electric capacity C2Top crown be connected；NMOS tube M3And M4Drain electrode and M5Grid be connected；NMOS tube M5Drain electrode The output end of start-up circuit is formed, and is connected with the input of current source circuit.
In such scheme, current source circuit includes PMOS M6、M7、M11、M12、M15、M16, and NMOS tube M8、M9、M10、 M13、M14、M17、M18；PMOS M6、M11And M15Source electrode be connected to power vd D；NMOS tube M10、M14、M18Source electrode be connected to Ground GND；PMOS M6Grid and drain electrode, PMOS M7Source electrode, PMOS M11And M15Grid be connected, formed current source First output end of circuit, and be connected with the first input end of temperature-compensation circuit；PMOS M7Grid and drain electrode and NMOS Pipe M8Drain electrode, PMOS M12And M16Grid be connected, formed current source circuit the second output end, and with temperature-compensating electricity The second input connection on road；NMOS tube M8Grid and PMOS M12Drain electrode, NMOS tube M13Grid be connected with drain electrode, The input of current source circuit is formed, and is connected with the output end of start-up circuit；NMOS tube M8Source electrode and NMOS tube M9Drain electrode It is connected；NMOS tube M9Grid, NMOS tube M14Grid and drain electrode with NMOS tube M13Source electrode be connected；NMOS tube M9Source Pole and NMOS tube M10Drain electrode be connected；NMOS tube M10、M17And M18Grid and NMOS tube M17Drain electrode be connected to PMOS M16Drain electrode；PMOS M11Drain electrode and PMOS M12Source electrode be connected；PMOS M15Drain electrode and PMOS M16Source Pole is connected；NMOS tube M17Source electrode and NMOS tube M18Drain electrode be connected.
In such scheme, temperature-compensation circuit includes PMOS M19、M20, NMOS tube M21、M22, and electric capacity C2；PMOS M19Source electrode be connected to power vd D；NMOS tube M22Source electrode and electric capacity C2Bottom crown be connected to ground GND；PMOS M19Grid Pole forms the first input end of temperature-compensation circuit, and is connected with the first output end of current source circuit；PMOS M19Drain electrode With PMOS M20Source electrode be connected；PMOS M20Grid form the second input of temperature-compensation circuit, and and current source The second output end connection of circuit；PMOS M20Drain electrode and NMOS tube M21Drain and gate, NMOS tube M22Grid be connected Connect；NMOS tube M21Source electrode, NMOS tube M22Drain electrode and electric capacity C2Top crown be connected, and form whole reference voltage source Output end Vref。
Compared with prior art, the present invention produces na magnitude using the working characteristics for being operated in sub-threshold region metal-oxide-semiconductor Reference current, power supply noise is suppressed using common-source common-gate current mirror.Additionally, the present invention not only has, and chip area is small, power consumption It is low, only nanowatt magnitude；And with high PSRR, the advantage of Low Drift Temperature coefficient and Low line regulation, and do not have Have using resistance, diode and triode, it is compatible with standard CMOS process, chip area is effectively reduced, and reduce life Produce cost.
Brief description of the drawings
Fig. 1 is a kind of schematic diagram of high PSRR whole CMOS reference voltage source.
Specific embodiment
With reference to the accompanying drawings and examples, technical scheme is described in detail：
A kind of high PSRR whole CMOS reference voltage source, as shown in figure 1, including start-up circuit, current source and temperature Compensation circuit.The output end of start-up circuit connects the input of current source circuit, and the output end connection temperature of current source circuit is mended The input of circuit is repaid, the output end of temperature-compensation circuit forms the output end V of whole reference voltage sourceref。
Start-up circuit, electric current is provided when reference voltage source is opened so that reference voltage source breaks away from degeneracy bias point, is entered Normal operating conditions.In a preferred embodiment of the invention, above-mentioned start-up circuit includes PMOS M1、M2、M3, NMOS tube M4、M5With Electric capacity C1.Wherein, M1、M3Source electrode be connected to power vd D；Electric capacity C1Bottom crown and M4、M5Source electrode be connected to ground GND；M1 Grid, drain electrode and M2Source electrode be connected；M2Grid, drain electrode, M3、M4Grid and electric capacity C2Top crown be connected；M3、 M4Drain electrode and M5Grid be connected；M5Drain electrode and current source circuit in M8、M13Grid, M12、M13Drain electrode be connected Connect.
Current source circuit, using the working characteristics for being operated in sub-threshold region metal-oxide-semiconductor, produces electric current.Using cascade electricity Stream mirror, suppresses power supply noise；Using being operated in the metal-oxide-semiconductor of linear zone instead of the resistance in traditional benchmark voltage source, on the basis of electricity Pressure produces circuit to provide current offset；In a preferred embodiment of the invention, above-mentioned current source circuit of receiving includes PMOS M6、M7、 M11、M12、M15、M16, NMOS tube M8、M9、M10、M13、M14、M17、M18.Wherein M6、M11、M15Source electrode be connected to power vd D；M10、 M14、M18Source electrode be connected to ground GND；M6Grid, drain electrode and M7Source electrode, M11、M15Grid be connected, and be connected to temperature M in degree compensation circuit19Grid；M7Grid, drain electrode and M8Drain electrode, M12、M16Grid be connected, and be connected to temperature benefit Repay M in circuit20Grid；M8Grid and M12Drain electrode, M13Grid, drain electrode be connected, and be connected to M in start-up circuit5 Drain electrode；M8Source electrode and M9Drain electrode be connected；M9Grid, M14Grid, drain electrode and M13Source electrode be connected；M9Source Pole and M10Drain electrode be connected；M10、M17、M18Grid and M17Drain electrode be connected to M16Drain electrode；M11Drain electrode and M12Source Pole is connected；M15Drain electrode and M16Source electrode be connected；M17Source electrode and M18Drain electrode be connected.
Temperature-compensation circuit, it is poor using 1.8VMOS pipes and 3.3VMOS pipe gate source voltages, by mutually regulation, obtain one Temperature independent reference voltage.In a preferred embodiment of the invention, said temperature compensation circuit includes PMOS M19、M20, NMOS tube M21、M22With electric capacity C2.Wherein, M19Source electrode be connected to power vd D；M22Source electrode, electric capacity C2Bottom crown be connected to Ground GND；M19Grid and current source circuit in M6、M11、M15Grid, M6Drain electrode, M7Source electrode be connected；M19Drain electrode With M20Source electrode be connected；M20Grid and current source circuit in M7、M12、M16Grid, M7、M8Drain electrode be connected；M20 Drain electrode and M21Drain electrode, grid, M22Grid be connected；M21Source electrode, M22Drain electrode and electric capacity C2Top crown be connected Connect, and be connected to output end Vref。
Operation principle of the invention is：
In start-up circuit, when supply voltage VDD is when zero begins to ramp up, due to M1、M2Grid be low level, its source electrode It is supply voltage VDD, so M1、M2Conducting, now charges to C1, M3、M4Composition phase inverter, M5Grid is high level, M5Conducting, Give current source circuit one starting current, force circuit to depart from degeneracy point；Until VDD rises to VTH, phase inverter M5Grid is low Level, final M5Cut-off, start-up circuit and core circuit depart from, and complete whole start-up course, hereafter M5All the time in cut-off shape State, does not have quiescent current, does not consume power.
Current source circuit is by metal-oxide-semiconductor M6、M7、M8、M9、M10、M11、M12、M13、M14、M15、M16、M17And M18Constitute, wherein M6、 M7、M11、M12、M15And M16Three pairs of common-source common-gate current mirrors are constituted, effect is image current；On the basis of voltage source power supply suppress Than using cascode structure；The I-V characteristic for being operated in the metal-oxide-semiconductor of sub-threshold region can be expressed as：
In formula, IDIt is the drain terminal electric current of metal-oxide-semiconductor；K=W/I is the breadth length ratio of metal-oxide-semiconductor；I0It is characterized electric current,μ=μ0(T0/T)mIt is the electron mobility of metal-oxide-semiconductor, T0It is reference temperature, μ0It is reference temperature T0When Electron mobility, T is expressed as absolute temperature, and m is humidity index, COX=εOX/tOXIt is gate oxide capacitance, wherein εOXIt is oxygen Compound dielectric constant, tOXIt is oxidated layer thickness, η is sub-threshold region slope factor, VGSIt is the gate source voltage of metal-oxide-semiconductor, VT=kBT/q It is thermal voltage, kBIt is Boltzmann constant, q is electron charge, VTHRepresent the threshold voltage of metal-oxide-semiconductor, VDSRepresent the drain-source of metal-oxide-semiconductor Voltage.
Work as VDS>3VTWhen, V can be neglectedDSTo IDInfluence, therefore be simplified shown as：
Further obtain the gate source voltage of metal-oxide-semiconductor：
η depends on the electric capacity of gate oxide and depletion layer, and existing η is assumed to a constant.
VGSiIt is metal-oxide-semiconductor MiGate source voltage, VDSiIt is metal-oxide-semiconductor MiDrain-source voltage, VTHiIt is metal-oxide-semiconductor MiThreshold voltage, KiIt is metal-oxide-semiconductor MiBreadth length ratio.
M9And M14Sub-threshold region is operated in, and two metal-oxide-semiconductor grids link together, current potential is identical, and source potential It is unequal, therefore M9And M14The potential difference of source electrode is equal to M10Drain-source voltage VDS10, therefore M10Drain-source voltage VDS10It is expressed as：
M10It is operated in linear zone, M10I-V characteristic curve can be expressed as：
IgnoreInfluence, be expressed as again：
IP=ID10=β [(VA-VTH)VDS10] (6)
In formula, IPIt is the output current of current source circuit, β=μ COXK10, μ (μ=μ0(T0/T)m) it is electron mobility, m is Humidity index, COXIt is gate oxide capacitance, K10It is M10Breadth length ratio, ID10It is M10Drain current, VTHIt is threshold voltage, VTH =VTH0- κ T, VTH0Threshold voltage value when representing that absolute temperature is 0K, κ is VTHTemperature coefficient.Electric current IPTemperature coefficientCan be expressed as：
In circuit, bias voltage VA=VGS18；M10Saturation region is operated in, so VGS18Can be expressed as：
ID18=QIP=ID10 (9)
Q is M in circuit in formula18With M10Leakage current the ratio between, according to formula (7) and (8), the TC in current source circuitI Finally may be expressed as：
Because the value of humidity index m is about 1.5, TCIValue very little, so the output current I of current sourcePShow good Temperature characterisitic, to provide a bias current for stabilization in temperature-compensation circuit, and can drive its normal work.
Temperature-compensation circuit refer to the attached drawing 1, by the metal-oxide-semiconductor M for being operated in sub-threshold region19~M22Composition.M19、M20With electric current M in source circuit15、M16Constitute common-source common-gate current mirror structure, can from current source circuit image current；Using being operated in The 1.8VMOS pipes of sub-threshold region and the gate source voltage of 3.3VMOS pipes are poor, obtain a reference voltage for zero temp shift；M21、M22Pipe It is the core circuit of temperature-compensating, is operated in sub-threshold region；Refer to the attached drawing 1 can obtain output reference voltage VrefExpression Formula is：
Vref=VGS22-VGS21 (11)
Using the I-V characteristic of the metal-oxide-semiconductor worked in sub-threshold region, output voltage V can be obtainedrefExpression formula：
In formula, tOX,iRepresent metal-oxide-semiconductor MiGate oxide thickness, Δ VTHRepresent metal-oxide-semiconductor M22、M21The difference of threshold voltage；Its The expression formula of middle threshold voltage is：
VTH=VTH0-κT (13)
Therefore Δ VTHWith negative temperature coefficient；Again by the V with positive temperature coefficientrefWith with negative temperature coefficient ΔVTHMutually regulation, just can obtain one and the unrelated output reference voltage V of temperatureref, threshold voltage VTHFurther can be with table It is shown as：
In formula, εsiRepresent the relative dielectric constant of silicon substrate；NAIt is substrate doping；niFor intrinsic carrier is dense Degree；EgIt is band gap；ψBIt is fermi level potential energy and the difference of intrinsic level potential energy；
In formula, NCIt is the available state state density of conduction band, NνIt is the available state state density of valence band, ignores bulk effect, can be with Obtain the temperature coefficient TC of reference voltageV：
The temperature coefficient for making reference voltage is zero, then can determine the breadth length ratio of metal-oxide-semiconductor：
Thus formula can be seemed, by K21/K22Adjustment, just can obtain the reference voltage that temperature coefficient is zero.Electricity Hold C2Purpose improve supply-voltage rejection ratio.
Under SMIC0.18-μm CMOS technology standard, emulated using CadenceSpectre emulators.Simulation result Show, under 1.8V supply voltages, the supply-voltage rejection ratio of this reference voltage source is -85.62dB in low frequency, in high frequency For -42dB；There is 34.43ppm/ DEG C of temperature coefficient within the temperature range of-25-125 DEG C；In 1.0V -3.4V power supplys electricity There is 0.06% line-voltage regulation, its power consumption is 206nW, the above measure of these simulation results shows in the range of pressure Validity.

Claims (5)

1. a kind of high PSRR whole CMOS reference voltage source, including reference voltage source, it is characterised in that：The reference voltage source Including start-up circuit, current source circuit and temperature-compensation circuit；The output end of start-up circuit connects the input of current source circuit, The output end of current source circuit connects the input of temperature-compensation circuit, and the output end of temperature-compensation circuit forms whole benchmark electricity The output end of potential source；
Start-up circuit, helps a reference source to break away from degeneracy bias point, into normal operating conditions；
Current source circuit, using sub-threshold region metal-oxide-semiconductor working characteristics is operated in, produces the reference current of na magnitude；Using altogether Source source common-gate current mirror, suppresses power supply noise；Using the resistance being operated in during the metal-oxide-semiconductor of linear zone replaces traditional benchmark voltage source, On the basis of voltage generation circuit provide current offset；
Temperature-compensation circuit, forms gate source voltage poor using different metal-oxide-semiconductor, by mutually regulation, obtain one and temperature without The reference voltage of pass.
2. a kind of high PSRR whole CMOS reference voltage source according to claim 1, it is characterised in that：Form grid source The metal-oxide-semiconductor of voltage difference is the metal-oxide-semiconductor of 1.8V and the metal-oxide-semiconductor of 3.3V.
3. a kind of high PSRR whole CMOS reference voltage source according to claim 1, it is characterised in that：Start-up circuit Including PMOS M1、M2、M3, NMOS tube M4、M5, and electric capacity C1；
PMOS M1And M3Source electrode be connected to power vd D；Electric capacity C1Bottom crown and NMOS tube M4And M5Source electrode be connected to ground GND；PMOS M1Grid and drain electrode with PMOS M2Source electrode be connected；PMOS M2Grid and drain electrode, PMOS M3's Grid, NMOS tube M4Grid and electric capacity C2Top crown be connected；NMOS tube M3And M4Drain electrode and M5Grid be connected； NMOS tube M5Drain electrode form the output end of start-up circuit, and be connected with the input of current source circuit.
4. a kind of high PSRR whole CMOS reference voltage source according to claim 1, it is characterised in that：Current source electricity Road includes PMOS M6、M7、M11、M12、M15、M16, and NMOS tube M8、M9、M10、M13、M14、M17、M18；
PMOS M6、M11And M15Source electrode be connected to power vd D；NMOS tube M10、M14、M18Source electrode be connected to ground GND；PMOS Pipe M6Grid and drain electrode, PMOS M7Source electrode, PMOS M11And M15Grid be connected, formed current source circuit first Output end, and be connected with the first input end of temperature-compensation circuit；PMOS M7Grid and drain electrode with NMOS tube M8Drain electrode, PMOS M12And M16Grid be connected, form the second output end of current source circuit, it is and defeated with the second of temperature-compensation circuit Enter end connection；NMOS tube M8Grid and PMOS M12Drain electrode, NMOS tube M13Grid be connected with drain electrode, formed current source The input of circuit, and be connected with the output end of start-up circuit；NMOS tube M8Source electrode and NMOS tube M9Drain electrode be connected； NMOS tube M9Grid, NMOS tube M14Grid and drain electrode with NMOS tube M13Source electrode be connected；NMOS tube M9Source electrode with NMOS tube M10Drain electrode be connected；NMOS tube M10、M17And M18Grid and NMOS tube M17Drain electrode be connected to PMOS M16's Drain electrode；PMOS M11Drain electrode and PMOS M12Source electrode be connected；PMOS M15Drain electrode and PMOS M16Source electrode be connected Connect；NMOS tube M17Source electrode and NMOS tube M18Drain electrode be connected.
5. a kind of high PSRR whole CMOS reference voltage source according to claim 1, it is characterised in that：Temperature-compensating Circuit includes PMOS M19、M20, NMOS tube M21、M22, and electric capacity C2；
PMOS M19Source electrode be connected to power vd D；NMOS tube M22Source electrode and electric capacity C2Bottom crown be connected to ground GND； PMOS M19Grid form the first input end of temperature-compensation circuit, and be connected with the first output end of current source circuit； PMOS M19Drain electrode and PMOS M20Source electrode be connected；PMOS M20Grid form the second defeated of temperature-compensation circuit Enter end, and be connected with the second output end of current source circuit；PMOS M20Drain electrode and NMOS tube M21Drain and gate, NMOS tube M22Grid be connected；NMOS tube M21Source electrode, NMOS tube M22Drain electrode and electric capacity C2Top crown be connected, and Form the output end V of whole reference voltage sourceref。
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