CN109375688B - Sub-threshold reference voltage generation circuit with ultra-low power consumption, low voltage and low temperature drift - Google Patents
Sub-threshold reference voltage generation circuit with ultra-low power consumption, low voltage and low temperature drift Download PDFInfo
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/462—Regulating voltage or current wherein the variable actually regulated by the final control device is dc as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
- G05F1/465—Internal voltage generators for integrated circuits, e.g. step down generators
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/468—Regulating voltage or current wherein the variable actually regulated by the final control device is dc characterised by reference voltage circuitry, e.g. soft start, remote shutdown
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
Abstract
The invention provides an ultra-low power consumption low-voltage low-temperature-drift sub-threshold reference voltage generation circuit, belonging to the technical field of power management. Comprises a starting circuit, a current reference circuit and a voltage regulatorPTATCircuit, VCTATAn electrical circuit. The starting circuit is used for preventing the zero current transmission condition, after the circuit normally works, firstly, a nanoamp-level reference current is generated by using a current reference core structure comprising a high-threshold MOS tube and a low-threshold MOS tube, and a current mirror is used for setting VPTATCircuit and VCTATThe circuit provides a bias. The voltage of the negative temperature coefficient is generated by utilizing the difference of the grid source voltage of MOS tubes with different threshold voltages, and meanwhile, the voltage of the positive temperature coefficient is generated by utilizing an unbalanced differential pair. The two voltages with different temperature coefficients are mutually superposed to compensate and generate reference voltage. The invention can complete the design indexes of low-voltage output and low-temperature drift on the premise of realizing ultra-low power consumption and reducing the layout area.
Description
Technical Field
The invention belongs to the technical field of voltage management. In particular to a design of a sub-threshold reference voltage generation circuit with ultra-low power consumption, low voltage and low temperature drift.
Background
With the development of artificial intelligence technology, wearable devices and implantable medical products have received a great deal of attention from consumers. Due to the limited size and capacity of batteries in wearable and implantable devices, it becomes very important how to reduce the power consumption of the power management chip. The voltage reference circuit is one of the important modules in the chip, and its main function is to provide accurate voltage reference for the following circuits. It is critical to design a well-behaved voltage reference, and as integrated circuit fabrication technology continues to advance, process feature sizes become smaller and smaller. The research on the chip power consumption is more focused on the sub-threshold region conducting property of the MOS tube. Therefore, the voltage reference operating in the sub-threshold region has become a hot point of research in recent years.
The traditional sub-threshold voltage reference generation circuit is mainly realized by a single MOS tube, is limited by process deviation and self compensation, is not easy to realize low temperature drift, and particularly, under the constraint of conditions such as power consumption, output voltage, power supply voltage and the like, the traditional sub-threshold voltage reference is difficult to meet all requirements. Therefore, how to implement the voltage reference with low output voltage, low temperature drift and ultra-low power consumption becomes the key point of research of the invention.
Referring to fig. 1, a typical sub-threshold voltage reference generation circuit in the prior art, in order to ensure that the MOS transistor operates in the sub-threshold region, the bias current I must be generally in the nano-ampere level, first the characteristics of the MOS transistor operating in the sub-threshold region must be known,
wherein, IDThe drain current of the MOS tube is shown. Mu-mu0(T0/T)mRepresenting the electron mobility, T, of the MOS transistor0Is the reference temperature, μ0Is the reference temperature T0The electron mobility, T represents the absolute temperature, m is the temperature index, COX＝OX/tOXAnd is represented by the unit area gate oxide capacitance,OXexpressed as the oxide dielectric constant, tOXIs the thickness of the oxide layer, η is the slope factor of the subthreshold region, and is related to the process, and under the standard submicron process, about 1.5. W and L respectively represent the channel width and length, K ═ W/L represents the width-to-length ratio of the MOS transistor, VT＝kBT/q represents a thermal voltage, where kBIs the boltzmann constant and q is the electronic charge. VGSIs the gate-source voltage, V, of the MOS transistorthIs the threshold voltage, VDSIs the drain-source voltage of the MOS transistor. Wherein, the characteristic current is used0＝μCOX(η-1)VT 2. In practical circuits, the drain-source voltage VDSIs greater than the thermal voltage VTWhen V is a value ofDS≥3VTIn time, a simplified current expression can be obtained:
the simplification of the step (2) can obtain,
the conventional sub-threshold reference voltage is a tube operating in a sub-threshold region by using a nano-ampere bias current, and meanwhile, the gate and the drain of the tube are connected together, and the reference voltage is generated by a gate-source voltage, so that:
VREF＝VGS(4)
in the gate-source voltage expression, the threshold voltage of the first term has a negative temperature coefficient, and the threshold voltage of the second term has a positive temperature coefficient. The reference voltage is generated by voltage compensation of positive and negative temperature coefficients. However, although it is easy to obtain the reference voltage by using this method, the threshold voltage values working in the sub-threshold region are all large, resulting in a large final output voltage, and at the same time, the threshold voltage with negative temperature coefficient can only be compensated by adjusting the current and K, but a large L value is required, the size ratio is too large, and the mismatch problem is easy to occur, and this compensation method is not high in precision and is greatly influenced by the process and the temperature.
Because the actual project has higher and higher requirements on low voltage and precision, how to complete a simplified circuit architecture with good performance is particularly critical.
Disclosure of Invention
The invention aims to overcome the problems of large output voltage and insufficient temperature characteristic in the existing sub-threshold voltage reference technology, and provides a sub-threshold reference voltage generation circuit with ultra-low power consumption, low voltage and low temperature drift.
The technical scheme of the invention is as follows:
a sub-threshold reference voltage generation circuit with ultra-low power consumption, low voltage and low temperature drift comprises a starting circuit, a current reference circuit and two compensation circuits, wherein one of the two compensation circuits is VPTATGenerator, the other is VCTATA generator; the output end of the starting circuit is connectedA control terminal of the current reference circuit.
The current reference circuit comprises a first PMOS (P-channel metal oxide semiconductor) tube (MP1), a second PMOS tube (MP2), a third PMOS tube (MP3), a first NMOS tube (MN1), a second NMOS tube (MN2), a third NMOS tube (MN3) and a fourth NMOS tube (MN 4);
the drain electrode of the first NMOS transistor (MN1) is connected with the grid electrode and the drain electrode of the first PMOS transistor (MP1) and the grid electrodes of the second PMOS transistor (MP2) and the third PMOS transistor (MP3) to serve as the control end of the current reference circuit, and the grid electrode of the first NMOS transistor is connected with the drain electrode of the third PMOS transistor (MP3) and the drain electrode of the third NMOS transistor (MN 3);
the grid-drain short circuit of the second NMOS tube (MN2) is connected with the drain electrode of the second PMOS tube (MP2) and the grid electrode of the third NMOS tube (MN3), the source electrode of the second NMOS tube is connected with the drain electrode of the fourth NMOS tube (MN4) with the grid-drain short circuit and the source electrode of the first NMOS tube (MN1), and the drain electrode of the third NMOS tube (MN3) is connected with the drain electrode of the third PMOS tube (MP3) and serves as the output end of the current reference circuit for generating the reference current;
the source electrodes of the third NMOS transistor (MN3) and the fourth NMOS transistor (MN4) are grounded, and the source electrodes of the first PMOS transistor (MP1), the second PMOS transistor (MP2) and the third PMOS transistor (MP3) are connected with power supply voltage;
the V isPTATGenerator and VCTATThe generator comprises a fourth PMOS tube (MP4), a fifth PMOS tube (MP5), a sixth PMOS tube (MP6), a seventh PMOS tube (MP7), a fifth NMOS tube (MN5), a sixth NMOS tube (MN6), a seventh NMOS tube (MN7) and an eighth NMOS tube (MN 8);
the grid drain of the fifth NMOS transistor (MN5) is in short circuit and is connected with the grid of the sixth NMOS transistor (MN6) and the drain of the fourth PMOS transistor (MP4), and the source of the fifth NMOS transistor is connected with the drain of the sixth NMOS transistor (MN6) and is used as the VCTATThe output end of the generator is connected with VPTATThe input end of the generator is the grid electrode of a sixth PMOS tube (MP 6);
the grid electrode of the sixth PMOS tube (MP6) is taken as VPTATThe input of the generator is connected to VCTATThe source electrode of the sixth PMOS tube is connected to the drain electrode of the fifth PMOS tube (MP5) and the source electrode of the seventh PMOS tube (MP 7);
the gate-drain short circuit of the seventh PMOS tube (MP7) is simultaneously connected to the drain electrode of the eighth NMOS tube (MN8) and serves as the reference voltage output end of the sub-threshold reference voltage generation circuit;
the grid-drain short circuit of the seventh NMOS transistor (MN7) is connected to the grid electrode of the eighth NMOS transistor (MN8), and the drain electrode of the seventh NMOS transistor is connected to the drain electrode of the sixth PMOS transistor (MP 6);
the sources of the sixth NMOS transistor (MN6), the seventh NMOS transistor (MN7) and the eighth NMOS transistor (MN8) are grounded, and the sources of the fourth PMOS transistor (MP4) and the fifth PMOS transistor (MP5) are connected with the power voltage.
The starting circuit comprises a ninth NMOS transistor (MS2), a tenth NMOS transistor (MS3), an eleventh NMOS transistor (MS4), a twelfth NMOS transistor (MC1) and an eighth PMOS transistor (MS 1);
the grid electrode of an eleventh NMOS tube (MS4) is connected to the drain electrode of the tenth NMOS tube (MS3) and the grid electrode of the twelfth NMOS tube (MC1), the drain electrode of the eleventh NMOS tube is connected to the grid electrode of the eighth PMOS tube (MS1) and the grid electrode of the first PMOS tube (MP1) with short-circuited grid electrode and drain electrodes and serves as the output end of the starting circuit;
the gate and the drain of the ninth NMOS transistor (MS2) are shorted and connected to the gate of the tenth NMOS transistor (MS3), and the drain of the ninth NMOS transistor is connected to the drain of the eighth PMOS transistor (MS 1);
the sources of the ninth NMOS transistor (MS2), the tenth NMOS transistor (MS3) and the eleventh NMOS transistor (MS4) are grounded, and the source and the drain of the twelfth NMOS transistor (MC1) and the source of the eighth PMOS transistor (MS1) are connected with the power voltage.
The width-length ratios of the first PMOS tube (MP1), the second PMOS tube (MP2), the third PMOS tube (MP3), the fourth PMOS tube (MP4) and the fifth PMOS tube (MP5) are the same, and the width-length ratios of the fifth NMOS tube (MN5) and the sixth NMOS tube (MN6) are 1: 1, the width-length ratio of the sixth PMOS tube (MP6) to the seventh PMOS tube (MP7) is 1: 2, the width-to-length ratio of the seventh NMOS transistor (MN7) to the eighth NMOS transistor (MN8) is 4: 3.
the third NMOS transistor (MN3) and the sixth NMOS transistor (MN6) are NMOS transistors with standard voltage of 5.0V, and the standard voltage of all the rest MOS transistors is 1.8V.
All tubes described operate in the subthreshold region.
The invention has the advantages and beneficial effects that: by utilizing the fact that all MOS tubes work in the sub-threshold region, the output reference voltage value is small and the temperature drift is small on the premise that ultra-low power consumption and low power supply voltage are achieved.
Drawings
Fig. 1 is a typical sub-threshold voltage generation circuit in the prior art.
FIG. 2 is a circuit for generating sub-threshold reference voltages according to the present invention.
FIG. 3 is a diagram of the resulting low temperature-drift sub-threshold reference voltage curve.
The specific implementation mode is as follows:
the invention is further elucidated with reference to the drawing.
The present invention provides a novel sub-threshold reference voltage generation circuit which can be completed in a CMOS process, as shown in fig. 2. Comprises 4 parts, a starting circuit, a current reference circuit and two compensation circuits, one is VPTATGenerator, the other is VCTATA generator.
The starting circuit comprises a ninth NMOS transistor MS2, a tenth NMOS transistor MS3, an eleventh NMOS transistor MS4, a twelfth NMOS transistor MC1 and an eighth PMOS transistor MS1 (the specific connection relationship of the starting circuit is described in the summary of the invention). The twelfth NMOS tube MC1 is used as a starting capacitor, the eleventh NMOS tube MS4 is used as a switch tube, when a system is powered on, the initial voltage of the twelfth NMOS tube MC1 which is used as the starting capacitor is a power supply voltage, the grid potential of the eleventh NMOS tube MS4 of the switch tube is pulled high, the eleventh NMOS tube MS4 is conducted, the grid potential of the first PMOS tube (MP1) is pulled low, the circuit works normally, after the circuit works normally, the grid potential of the switch tube is pulled low through the mirror image of the eighth PMOS tube MS1 and the effects of the current mirror, the ninth NMOS tube MS2 and the tenth NMOS tube MS3, and the starting circuit is separated from the whole circuit.
As shown in fig. 2, the current reference circuit includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, and a fourth NMOS transistor MN4 (see the description of the summary of the invention for the specific connection relationship of the circuits). The width-to-length ratios of the first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP3 are the same, the core circuit comprises a second NMOS transistor MN2 and a fourth NMOS transistor MN4 with the standard voltage of 1.8V and a third NMOS transistor (MN3) with the standard voltage of 5.0V, and the gate-source voltage of the third NMOS transistor has the following expression:
VGS,MN3＝VGS,MN2+VGS,MN4(5)
since the width-to-length ratios of the current mirrors are the same, the current flowing is assumed to be IBTherefore, by substituting equation (3) into equation (5), it is possible to obtain:
wherein each letter represents a meaning of
C＝COX(η-1)，
The obtained reference current is mirrored to an active load circuit, namely a compensation circuit, through a third PMOS transistor MP3, and the circuit mainly comprises two circuits, one of which is VPTATGenerator, the other is VCTATA generator. VCTATThe generator comprises a fourth PMOS tube MP4, a fifth NMOS tube MN5 and a sixth NMOS tube MN6, wherein the grid drain of the fifth NMOS tube MN5 is in short circuit connection with the grid of the sixth NMOS tube MN6 and the drain of the fourth PMOS tube MP4, and the source of the fifth NMOS tube MN5 is connected with the drain of the sixth NMOS tube MN6 and serves as VCTATThe output end of the generator is connected with VPTATAn input of the generator.
VPTATThe generator comprises a fifth PMOS tube MP5, a sixth PMOS tube MP6, a seventh PMOS tube MP7, a seventh NMOS tube MN7 and an eighth NMOS tube MN 8. The gate of the sixth PMOS transistor MP6 is taken as VPTATThe input of the generator is connected to VCTATAnd the source of the output end of the generator is connected to the drain of the fifth PMOS transistor MP5 and the source of the seventh PMOS transistor MP 7.
The gate-drain short circuit of the seventh PMOS transistor MP7 is connected to the drain of the eighth NMOS transistor MN8 at the same time and serves as the reference voltage output terminal of the sub-threshold reference voltage generating circuit, the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 form an unbalanced differential pair, the sources are connected to each other, a current with a positive temperature coefficient can be generated, and the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 form a current mirror.
The specific implementation method is that firstly, the current reference circuit generates a reference current, and because the first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP3 adopt the same width-to-length ratio, the flowing currents are all IBAnd provides bias currents for both generators. The fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 have different threshold voltages and flow currents IBAnd selecting the same width-length ratio to obtain the following expression:
wherein m is η ln (C)OX1/COX2). The difference in threshold voltage has a negative temperature coefficient, albeit VTHas a positive temperature coefficient but ultimately still a negative temperature coefficient. The first term in the expression represents the difference between the threshold voltages of the sixth NMOS transistor MN6 and the fifth NMOS transistor MN 5. Considering the body effect benefit of the fifth NMOS transistor MN5 is to reduce Δ VTHAnd m is a negative value, and finally the magnitude of the output negative temperature coefficient voltage is reduced by using the threshold voltage difference value, considering the body effect and using m. Then as the input voltage of the positive temperature coefficient voltage generating module at VPTATIn the generator, the ratio of the currents flowing through the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 is the mirror ratio of the current mirror seventh NMOS transistor MN7 and the eighth NMOS transistor MN 8. The expression of the positive temperature coefficient can be obtained as
Wherein n is η ln (K)MP7KMN7/KMP6KMN8)。VTHas positive temperature coefficient, and finally obtains voltage with positive temperature coefficient. The final reference voltage expression obtained by mutual compensation of positive and negative temperatures is as follows:
VREF＝ΔVTH+mVT+nVT(9)
the expressionTerm Δ V of formulaTHIs a threshold voltage difference with a negative temperature coefficient, passing through the second term mVTThe negative temperature coefficient voltage is compensated and the output reference voltage is reduced. By adjusting the third term nVTThe number of the middle four tubes compensates for the negative temperature coefficient voltage.
All MOS tubes work in a sub-threshold region, compared with the traditional sub-threshold voltage reference, the ultra-low power consumption is realized, and meanwhile, as shown in figure 3, a reference voltage with low output voltage and low temperature drift is finally obtained.
Claims (3)
1. The sub-threshold reference voltage generation circuit is characterized by comprising a starting circuit, a current reference circuit and two compensation circuits, wherein one compensation circuit is VPTATGenerator, the other is VCTATA generator; the output end of the starting circuit is connected with the control end of the current reference circuit;
the starting circuit comprises a ninth NMOS transistor (MS2), a tenth NMOS transistor (MS3), an eleventh NMOS transistor (MS4), a twelfth NMOS transistor (MC1) and an eighth PMOS transistor (MS 1);
the grid electrode of an eleventh NMOS tube (MS4) is connected to the drain electrode of the tenth NMOS tube (MS3) and the grid electrode of the twelfth NMOS tube (MC1), the drain electrode of the eleventh NMOS tube is connected to the grid electrode of the eighth PMOS tube (MS1) and the grid electrode of the first PMOS tube (MP1) with short-circuited grid electrode and drain electrodes and serves as the output end of the starting circuit;
the gate and the drain of the ninth NMOS transistor (MS2) are shorted and connected to the gate of the tenth NMOS transistor (MS3), and the drain of the ninth NMOS transistor is connected to the drain of the eighth PMOS transistor (MS 1);
the source electrodes of the ninth NMOS transistor (MS2), the tenth NMOS transistor (MS3) and the eleventh NMOS transistor (MS4) are grounded, and the source electrode and the drain electrode of the twelfth NMOS transistor (MC1) and the source electrode of the eighth PMOS transistor (MS1) are connected with the power supply voltage;
the current reference circuit comprises a first PMOS (P-channel metal oxide semiconductor) tube (MP1), a second PMOS tube (MP2), a third PMOS tube (MP3), a first NMOS tube (MN1), a second NMOS tube (MN2), a third NMOS tube (MN3) and a fourth NMOS tube (MN 4);
the drain electrode of the first NMOS transistor (MN1) is connected with the grid electrode and the drain electrode of the first PMOS transistor (MP1) and the grid electrodes of the second PMOS transistor (MP2) and the third PMOS transistor (MP3) to serve as the control end of the current reference circuit, and the grid electrode of the first NMOS transistor is connected with the drain electrode of the third PMOS transistor (MP3) and the drain electrode of the third NMOS transistor (MN 3);
the grid-drain short circuit of the second NMOS tube (MN2) is connected with the drain electrode of the second PMOS tube (MP2) and the grid electrode of the third NMOS tube (MN3), the source electrode of the second NMOS tube is connected with the drain electrode of the fourth NMOS tube (MN4) with the grid-drain short circuit and the source electrode of the first NMOS tube (MN1), and the drain electrode of the third NMOS tube (MN3) is connected with the drain electrode of the third PMOS tube (MP3) and serves as the output end of the current reference circuit for generating the reference current;
the source electrodes of the third NMOS transistor (MN3) and the fourth NMOS transistor (MN4) are grounded, and the source electrodes of the first PMOS transistor (MP1), the second PMOS transistor (MP2) and the third PMOS transistor (MP3) are connected with power supply voltage;
the V isPTATGenerator and VCTATThe generator comprises a fourth PMOS tube (MP4), a fifth PMOS tube (MP5), a sixth PMOS tube (MP6), a seventh PMOS tube (MP7), a fifth NMOS tube (MN5), a sixth NMOS tube (MN6), a seventh NMOS tube (MN7) and an eighth NMOS tube (MN 8);
the grid drain of the fifth NMOS transistor (MN5) is in short circuit and is connected with the grid of the sixth NMOS transistor (MN6) and the drain of the fourth PMOS transistor (MP4), and the source of the fifth NMOS transistor is connected with the drain of the sixth NMOS transistor (MN6) and is used as the VCTATThe output end of the generator is connected with VPTATThe input end of the generator is the grid electrode of a sixth PMOS tube (MP 6);
the grid electrode of the sixth PMOS tube (MP6) is taken as VPTATThe input of the generator is connected to VCTATThe source electrode of the sixth PMOS tube is connected to the drain electrode of the fifth PMOS tube (MP5) and the source electrode of the seventh PMOS tube (MP 7);
the gate-drain short circuit of the seventh PMOS tube (MP7) is simultaneously connected to the drain electrode of the eighth NMOS tube (MN8) and serves as the reference voltage output end of the sub-threshold reference voltage generation circuit;
the grid-drain short circuit of the seventh NMOS transistor (MN7) is connected to the grid electrode of the eighth NMOS transistor (MN8), and the drain electrode of the seventh NMOS transistor is connected to the drain electrode of the sixth PMOS transistor (MP 6);
the source electrodes of the sixth NMOS transistor (MN6), the seventh NMOS transistor (MN7) and the eighth NMOS transistor (MN8) are grounded, and the source electrodes of the fourth PMOS transistor (MP4) and the fifth PMOS transistor (MP5) are connected with power supply voltage;
all the MOS tubes work in a subthreshold region.
2. The sub-threshold voltage generation circuit of claim 1, wherein the width-to-length ratios of the first PMOS transistor (MP1), the second PMOS transistor (MP2), the third PMOS transistor (MP3), the fourth PMOS transistor (MP4) and the fifth PMOS transistor (MP5) are the same, and the width-to-length ratios of the fifth NMOS transistor (MN5) and the sixth NMOS transistor (MN6) are 1: 1, the width-length ratio of the sixth PMOS tube (MP6) to the seventh PMOS tube (MP7) is 1: 2, the width-to-length ratio of the seventh NMOS transistor (MN7) to the eighth NMOS transistor (MN8) is 4: 3.
3. the sub-threshold voltage generation circuit of any of claims 1 to 2, wherein the third NMOS transistor (MN3) and the sixth NMOS transistor (MN6) are NMOS transistors with a standard voltage of 5.0V, and the standard voltage of all the other MOS transistors is 1.8V.
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| CN110377095A (en) * | 2019-07-22 | 2019-10-25 | 天津理工大学 | A kind of subthreshold value reference voltage generating circuit of super low-power consumption low-voltage Low Drift Temperature |
| CN110502056A (en) * | 2019-08-22 | 2019-11-26 | 成都飞机工业（集团）有限责任公司 | A kind of threshold voltage reference circuit |
| CN111026221A (en) * | 2019-12-12 | 2020-04-17 | 芯创智（北京）微电子有限公司 | Voltage reference circuit working under low power supply voltage |
| CN112416044A (en) * | 2020-12-03 | 2021-02-26 | 电子科技大学 | Voltage reference circuit with high power supply rejection ratio |
| CN115756073B (en) * | 2022-12-09 | 2024-03-01 | 深圳市中新力电子科技有限公司 | Small-volume band gap reference voltage source integrated circuit applied to intelligent mobile equipment power supply system |
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| CN108205353A (en) * | 2018-01-09 | 2018-06-26 | 电子科技大学 | A kind of CMOS subthreshold values reference voltage source |
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| US20080297229A1 (en) * | 2007-05-31 | 2008-12-04 | Navin Kumar Ramamoorthy | Low power cmos voltage reference circuits |
| CN106527572B (en) * | 2016-12-08 | 2018-01-09 | 电子科技大学 | A kind of low-power consumption Low Drift Temperature CMOS subthreshold value reference circuits |
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