CN109491432A - A kind of voltage reference circuit of ultralow pressure super low-power consumption - Google Patents
A kind of voltage reference circuit of ultralow pressure super low-power consumption Download PDFInfo
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- CN109491432A CN109491432A CN201811363674.2A CN201811363674A CN109491432A CN 109491432 A CN109491432 A CN 109491432A CN 201811363674 A CN201811363674 A CN 201811363674A CN 109491432 A CN109491432 A CN 109491432A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
A kind of voltage reference circuit of ultralow pressure super low-power consumption, belongs to technical field of integrated circuits.Including start-up circuit module, current source module, high-low voltage generation module and double N tube voltage difference blocks, start-up circuit module makes the voltage reference circuit be detached from nought state when power supply is established, in start completion backed off after random；Current source module is for generating bias current；High-low voltage generation module is for generating a high voltage and a low-voltage；The difference of high voltage and low-voltage is exported using double N tube voltage difference blocks, as reference voltage, while the size by adjusting metal-oxide-semiconductor, to adjust the temperature coefficient of voltage reference circuit.A kind of voltage reference circuit of ultralow pressure super low-power consumption proposed by the present invention solves the problems, such as that existing band-gap reference circuit is inoperable when supply voltage is lower than 0.7V cut-in voltage, can work under lower supply voltage；And power consumption of the invention is only a few nanowatts, well below the power consumption of traditional band-gap reference.
Description
Technical field
The invention belongs to technical field of integrated circuits, particularly relate to a kind of voltage reference of ultralow pressure super low-power consumption
Circuit.
Background technique
Voltage reference circuit is a part indispensable in all electronic systems, is not only wanted in some special environment
The voltage for asking voltage reference circuit to generate does not change with the variation of supply voltage and temperature, while also requiring it with extremely low power dissipation
Work is under ultra-low power supply voltage.Traditional band-gap reference is most widely used, but is limited by its cut-in voltage, cannot work
Under ultra-low power supply voltage, it cannot generally be worked normally when being lower than 0.7V.
Summary of the invention
It cannot work for above-mentioned traditional bandgap benchmark in the shortcoming of ultra-low power supply voltage, the invention proposes one kind
The voltage reference circuit of ultralow pressure super low-power consumption based on threshold difference.
The technical solution of the present invention is as follows:
A kind of voltage reference circuit of ultralow pressure super low-power consumption, comprising:
Start-up circuit module makes the voltage reference circuit be detached from nought state when power supply is established, and retreats in start completion
Out；
Current source module, for generating bias current；
The voltage reference circuit further includes high-low voltage generation module and double N tube voltage difference blocks,
The high-low voltage generation module includes the 6th PMOS tube MP6, the 7th PMOS tube MP7, the 6th NMOS tube MN6 and the
Ten NMOS tube MNHV2, wherein the tenth NMOS tube MNHV2 is high threshold NMOS tube, the 6th NMOS tube MN6 and the tenth NMOS tube
MNHV2 works in sub-threshold region；The grid of 6th PMOS tube MP6 connects the grid of the 7th PMOS tube MP7, source electrode connection the
The source electrode of seven PMOS tube MP7 simultaneously connects supply voltage, and drain electrode connects the grid of the 6th NMOS tube MN6 and drains and export low electricity
Pressure；The grid of tenth NMOS tube MNHV2 connects its drain electrode and the drain electrode of the 7th PMOS tube MP7 and output HIGH voltage, and source electrode connects
Connect the source electrode of the 6th NMOS tube MN6 and ground connection；In 6th PMOS tube MP6 and the 7th PMOS tube MP7 and the current source module
Switching tube constitutes current mirror, for branch where the bias current is mirrored to the 6th PMOS tube MP6 and the 7th PMOS tube MP7
Road；
Double N tube voltage difference blocks include the 7th NMOS tube MN7 and the 8th NMOS tube MN8, wherein the 7th NMOS tube
MN7 and the 8th NMOS tube MN8 are Low threshold NMOS tube and work in sub-threshold region；The grid leak of 7th NMOS tube MN7 is shorted
And the high voltage is connected, source electrode connects the drain electrode of the 8th NMOS tube MN8 and the output end as the voltage reference circuit；
The grid of 8th NMOS tube MN8 connects the low-voltage, source electrode ground connection.
Specifically, the current source module include work the 4th NMOS tube MN4 of sub-threshold region, the 5th NMOS tube MN5,
9th NMOS tube MNHV1, the 4th PMOS tube MP4 and the 5th PMOS tube MP5；The grid leak of 4th PMOS tube MP4 is shorted and connects
6th PMOS tube MP6 in the drain electrode of the grid and the 4th NMOS tube MN4 of five PMOS tube MP5 and the high-low voltage generation module
With the grid of the 7th PMOS tube MP7, source electrode connects the source electrode of the 5th PMOS tube MP5 and connects supply voltage；5th NMOS tube
The grid leak of MN5 is shorted and connects drain electrode and the grid of the 9th NMOS tube MNHV1 of the 5th PMOS tube MP5, source electrode connection the 4th
The drain electrode of the grid of NMOS tube MN4 and the 9th NMOS tube MNHV1；The source electrode of 4th NMOS tube MN4 and the 9th NMOS tube MNHV1 connects
Ground.
Specifically, the start-up circuit module include the first NMOS tube MN1, the second NMOS tube MN2, third NMOS tube MN3,
First PMOS tube MP1, the second PMOS tube MP2 and third PMOS tube MP3；The grid of first PMOS tube MP1 connects the current source
The grid of 4th PMOS tube MP4 in module, source electrode connect the source electrode of the second PMOS tube MP2 and connect supply voltage, drain
Connect the grid of the first NMOS tube MN1 and the grid of drain electrode and third PMOS tube MP3 and the second NMOS tube MN2；3rd PMOS
The source electrode of pipe MP3 connects grid and the drain electrode of the second PMOS tube MP2, the drain electrode and third of the second NMOS tube MN2 of drain electrode connection
The grid of NMOS tube MN3；The source electrode of second NMOS tube MN2 connects the source electrode of the first NMOS tube MN1 and ground connection；Third NMOS tube
The drain electrode of MN3 connects the grid of the 4th PMOS tube MP4 in the current source module, and source electrode connects in the current source module the
The grid of five NMOS tube MN5.
The invention has the benefit that a kind of voltage reference circuit of ultralow pressure super low-power consumption proposed by the present invention, solves
Existing band-gap reference circuit inoperable problem when supply voltage is lower than 0.7V cut-in voltage, can work lower
Under supply voltage；And power consumption of the invention is only several nanowatts, well below the power consumption of traditional band-gap reference.
Detailed description of the invention
Fig. 1 is a kind of overall structure block diagram of the voltage reference circuit of ultralow pressure super low-power consumption proposed by the present invention.
Fig. 2 is the circuit structure diagram of start-up circuit module in embodiment.
Fig. 3 is the circuit structure diagram of current source module in embodiment.
Fig. 4 is high-low voltage generation module in a kind of voltage reference circuit of ultralow pressure super low-power consumption proposed by the present invention
Circuit structure diagram.
Fig. 5 is double N tube voltage difference blocks in a kind of voltage reference circuit of ultralow pressure super low-power consumption proposed by the present invention
Circuit structure diagram.
Fig. 6 is to emulate to obtain by Hspice by a kind of voltage reference circuit of ultralow pressure super low-power consumption proposed by the present invention
Analogous diagram.
Specific embodiment
A specific embodiment of the invention is described in the following with reference to the drawings and specific embodiments.
A kind of voltage reference circuit overall structure block diagram of ultralow pressure super low-power consumption proposed by the present invention is as shown in Figure 1, packet
Start-up circuit module, current source module, high-low voltage generation module and double N tube voltage difference blocks are included, it is poor using double N tube voltages
Sub-module exports the difference of high-low voltage, as voltage reference value, while the size by adjusting metal-oxide-semiconductor, to adjust voltage base
The temperature coefficient of quasi- circuit.Voltage reference circuit proposed by the present invention can be fabricated to integrated circuit using standard CMOS process.
The circuit structure and connection relationship of describing module separately below.
Start-up circuit module is retreated for making voltage reference circuit be detached from nought state when power supply is established in start completion
Out；A kind of circuit implementation of start-up circuit module, including the first NMOS tube MN1, the second NMOS tube are given as shown in Figure 2
MN2, third NMOS tube MN3, the first PMOS tube MP1, the second PMOS tube MP2 and third PMOS tube MP3；First PMOS tube MP1's
Grid connects bias voltage Vbias, and source electrode connects the source electrode of the second PMOS tube MP2 and connects supply voltage VDD, and drain electrode connects
Connect the grid of the first NMOS tube MN1 and the grid of drain electrode and third PMOS tube MP3 and the second NMOS tube MN2, bias voltage
Vbias is provided by current source module；The source electrode of third PMOS tube MP3 connects grid and the drain electrode of the second PMOS tube MP2, drain electrode
Connect the drain electrode of the second NMOS tube MN2 and the grid of third NMOS tube MN3；The source electrode of second NMOS tube MN2 connects the first NMOS
The source electrode of pipe MN1 is simultaneously grounded VSS；The drain electrode connecting node Vup of third NMOS tube MN3, source electrode connecting node Vdown, node
Vup and node Vdown are connected to current source module, are used for enabled current source module.
Third PMOS tube MP3 and the second NMOS tube MN2 constitutes an inverter structure, initial stage in start-up circuit module
Bias current is not present in entire circuit, and phase inverter input at this time is zero, and output high level opens third NMOS tube MN3, electricity
It flows source module and generates electric current, there are voltages for phase inverter input at this time, and it exports low level and third NMOS tube MN3 is closed, starting
Process terminates.
Current source module is enabled by start-up circuit module, for generating bias current and being supplied to start-up circuit module and height
Low-voltage generation module；Give a kind of circuit implementation of current source module as shown in Figure 3, including the 4th NMOS tube MN4,
5th NMOS tube MN5, the 9th NMOS tube MNHV1, the 4th PMOS tube MP4 and the 5th PMOS tube MP5；The grid of 4th PMOS tube MP4
Leakage is shorted and exports the grid of the 5th PMOS tube MP5 of bias voltage Vbias connection and drain electrode and the height of the 4th NMOS tube MN4
The grid of 6th PMOS tube MP6 and the 7th PMOS tube MP7 in voltage generating module, source electrode connect the source of the 5th PMOS tube MP5
Pole simultaneously connects supply voltage VDD；The grid leak of 5th NMOS tube MN5 is shorted and connects the drain electrode and the 9th of the 5th PMOS tube MP5
The grid of NMOS tube MNHV1, source electrode connect the drain electrode of the grid and the 9th NMOS tube MNHV1 of the 4th NMOS tube MN4；4th
The source electrode of NMOS tube MN4 and the 9th NMOS tube MNHV1 are grounded VSS.
The grid of the 4th PMOS tube MP4 of node Vup connection, the grid of the 5th NMOS tube MN5 of node Vdown connection, circuit
After starting, after third NMOS tube MN3 is opened in start-up circuit module, control current source module generates bias current.4th NMOS
Pipe MN4, the 5th NMOS tube MN5, the 9th NMOS tube MNHV1, the 4th PMOS tube MP4 and the 5th PMOS tube MP5 work in subthreshold
It is worth area.4th PMOS tube MP4 and the 5th PMOS tube MP5 constitutes current mirror, and the ratio between electric current is related to the ratio between breadth length ratio, bias current
Ibias by the 4th NMOS tube MN4, the 5th NMOS tube MN5 and the 9th NMOS tube MNHV1 generate, the first PMOS tube respectively with open
The first PMOS tube, the 6th PMOS tube MP6 in high-low voltage generation module and the 7th PMOS tube MP7 constitute electricity in dynamic circuit module
Mirror is flowed, by image current mirror image to corresponding branch.
It is the structural schematic diagram of high-low voltage generation module, including the 6th PMOS tube MP6, the 7th PMOS tube as shown in Figure 4
MP7, the 6th NMOS tube MN6 and the tenth NMOS tube MNHV2；The grid of 6th PMOS tube MP6 connects the grid of the 7th PMOS tube MP7
Pole, source electrode connect the source electrode of the 7th PMOS tube MP7 and connect supply voltage VDD, the grid of the 6th NMOS tube MN6 of drain electrode connection
Pole and drain electrode simultaneously export low-voltage VGS1；The grid of tenth NMOS tube MNHV2 connects the drain electrode of its drain electrode and the 7th PMOS tube MP7
And output HIGH voltage VGS2, source electrode connect the source electrode of the 6th NMOS tube MN6 and are grounded VSS；6th PMOS tube MP6 and the 7th
Switching tube in PMOS tube MP7 and current source module constitutes current mirror, for by bias current be mirrored to the 6th PMOS tube MP6 and
Branch where 7th PMOS tube MP7.
For providing electric current, its threshold voltage of the 6th NMOS tube MN6 is 6th PMOS tube MP6 and the 7th PMOS tube MP7
VTH1, the tenth NMOS tube MNHV2 are high threshold NMOS, threshold voltage VTH2, the 6th NMOS tube MN6 and the tenth NMOS tube
MNHV2 works in sub-threshold region, their gate source voltage VGS1, VGS2 has following relationship:
Wherein m is the sub-threshold slope factor, VTIt is thermal voltage, μnIt is electron mobility, CoxFor gate oxidation capacitance, k1、k2
It is the multiple of electric current and bias current that third PMOS tube MP3 and the 4th PMOS tube MP4 is provided, (W/L) respectively1、(W/L)2Respectively
For the breadth length ratio of the 6th NMOS tube MN6 and the tenth NMOS tube MNHV2.
It is the structural schematic diagram of double N tube voltage difference blocks, including the 7th NMOS tube MN7 and the 8th NMOS as shown in Figure 5
Pipe MN8, wherein the 7th NMOS tube MN7 and the 8th NMOS tube MN8 are Low threshold NMOS tube and work in sub-threshold region；7th
The grid leak of NMOS tube MN7 is shorted and connects high voltage VGS2, and source electrode connects the drain electrode of the 8th NMOS tube MN8 and as voltage base
The output end of quasi- circuit；The grid of 8th NMOS tube MN8 connects low-voltage VGS1, source electrode ground connection.
The gate source voltage VGS7 of 7th NMOS tube MN7 may be expressed as:
The gate source voltage VGS8 of 4th NMOS tube MN4 may be expressed as:
Reference voltage VREF can be obtained:
Since threshold voltage can respectively indicate are as follows:
VTH1 (T)=VTH1 (T0)+Kth1(T-T0)
VTH2 (T)=VTH2 (T0)+Kth2(T-T0)
Then further abbreviation obtains:
First derivative is asked to above formula, temperature-independent voltage can be obtained.Double N tube voltage difference blocks will
The output of the difference of high voltage VGS2 and low-voltage VGS1, as voltage reference value VREF, while the size by adjusting metal-oxide-semiconductor, come
Adjust the temperature coefficient of voltage reference circuit.
A kind of voltage reference circuit of ultralow pressure super low-power consumption proposed by the invention emulates to obtain such as figure by Hspice
Analogous diagram shown in 6, emulation shows in temperature range from -40 DEG C to 80 DEG C, the base generated under standard technology angle (tt corner)
Quasi- voltage VREF temperature coefficient is only 32ppm/ DEG C.In typical case (tt corner, 27 DEG C), supply voltage VDD=0.5V,
Total current drain is 19nA, total power consumption 9.5nW.It can be seen that the present invention is not needing the feelings using bipolar junction transistor and resistance
Under condition, so that the minimum voltage of work is less than 0.7V, can work under more low supply voltage compared to traditional benchmark source；It works at the same time
Power consumption be only a few nanowatts, be able to achieve lower power consumption, reliable and stable benchmark can be provided for the medical electronics product of low-power consumption
Voltage source.
Those skilled in the art disclosed the technical disclosures can make various do not depart from originally according to the present invention
Other various specific variations and combinations of essence are invented, these variations and combinations are still within protection scope of the present invention.
Claims (3)
1. a kind of voltage reference circuit of ultralow pressure super low-power consumption, comprising:
Start-up circuit module makes the voltage reference circuit be detached from nought state, in start completion backed off after random when power supply is established；
Current source module, for generating bias current；
It is characterized in that, the voltage reference circuit further includes high-low voltage generation module and double N tube voltage difference blocks,
The high-low voltage generation module includes the 6th PMOS tube, the 7th PMOS tube MP7, the 6th NMOS tube and the tenth NMOS tube,
Wherein the tenth NMOS tube is high threshold NMOS tube, and the 6th NMOS tube and the tenth NMOS tube work in sub-threshold region；6th PMOS
The grid of pipe connects the grid of the 7th PMOS tube, and source electrode connects the source electrode of the 7th PMOS tube and connects supply voltage, drains
It connects the grid of the 6th NMOS tube and drains and export low-voltage；The grid of tenth NMOS tube connects its drain electrode and the 7th PMOS tube
Drain electrode and output HIGH voltage, source electrode connect the 6th NMOS tube source electrode and ground connection；6th PMOS tube and the 7th PMOS tube MP7
Current mirror is constituted with the switching tube in the current source module, for the bias current to be mirrored to the 6th PMOS tube and the 7th
Branch where PMOS tube MP7；
Double N tube voltage difference blocks include the 7th NMOS tube and the 8th NMOS tube, wherein the 7th NMOS tube and the 8th NMOS
Pipe is Low threshold NMOS tube and works in sub-threshold region；The grid leak of 7th NMOS tube is shorted and connects the high voltage,
Source electrode connects the drain electrode of the 8th NMOS tube and the output end as the voltage reference circuit；The grid of 8th NMOS tube connects institute
State low-voltage, source electrode ground connection.
2. the voltage reference circuit of ultralow pressure super low-power consumption according to claim 1, which is characterized in that the current source mould
Block includes fourth NMOS tube, fiveth NMOS tube, nineth NMOS tube, fourth PMOS tube and fiveth PMOS of the work in sub-threshold region
Pipe；The grid leak of 4th PMOS tube is shorted and connects the grid of the 5th PMOS tube and the drain electrode of the 4th NMOS tube and height electricity
The grid of the 6th PMOS tube and the 7th PMOS tube MP7 in generation module is pressed, source electrode connects the source electrode of the 5th PMOS tube and connection
Supply voltage；The grid leak of 5th NMOS tube is shorted and connects drain electrode and the grid of the 9th NMOS tube of the 5th PMOS tube, source electrode
Connect the grid of the 4th NMOS tube and the drain electrode of the 9th NMOS tube；The source electrode of 4th NMOS tube and the 9th NMOS tube ground connection.
3. the voltage reference circuit of ultralow pressure super low-power consumption according to claim 2, which is characterized in that the start-up circuit
Module includes the first NMOS tube, the second NMOS tube, third NMOS tube, the first PMOS tube, the second PMOS tube and third PMOS tube；The
The grid of one PMOS tube connects the grid of the 4th PMOS tube in the current source module, and source electrode connects the source electrode of the second PMOS tube
And supply voltage is connected, the grid of drain electrode the first NMOS tube of connection and the grid of drain electrode and third PMOS tube and the second NMOS tube
Pole；The source electrode of third PMOS tube connects grid and the drain electrode of the second PMOS tube, the drain electrode of drain electrode the second NMOS tube of connection and the
The grid of three NMOS tubes；The source electrode of second NMOS tube connects the source electrode of the first NMOS tube and ground connection；The drain electrode of third NMOS tube connects
The grid of the 4th PMOS tube in the current source module is connect, source electrode connects the grid of the 5th NMOS tube in the current source module
Pole.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811363674.2A CN109491432A (en) | 2018-11-16 | 2018-11-16 | A kind of voltage reference circuit of ultralow pressure super low-power consumption |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811363674.2A CN109491432A (en) | 2018-11-16 | 2018-11-16 | A kind of voltage reference circuit of ultralow pressure super low-power consumption |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110502056A (en) * | 2019-08-22 | 2019-11-26 | 成都飞机工业（集团）有限责任公司 | A kind of threshold voltage reference circuit |
| CN110568894A (en) * | 2019-08-22 | 2019-12-13 | 成都飞机工业（集团）有限责任公司 | Four-tube voltage reference circuit |
| CN112394766A (en) * | 2019-08-19 | 2021-02-23 | 圣邦微电子（北京）股份有限公司 | CMOS low-voltage band-gap reference voltage source capable of reducing power consumption and improving precision under low voltage |
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| CN107943183A (en) * | 2017-12-06 | 2018-04-20 | 电子科技大学 | A kind of voltage reference circuit of super low-power consumption |
| CN108415503A (en) * | 2018-05-30 | 2018-08-17 | 丹阳恒芯电子有限公司 | A kind of low-voltage and low-power dissipation reference circuit |
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| CN107943183A (en) * | 2017-12-06 | 2018-04-20 | 电子科技大学 | A kind of voltage reference circuit of super low-power consumption |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112394766A (en) * | 2019-08-19 | 2021-02-23 | 圣邦微电子（北京）股份有限公司 | CMOS low-voltage band-gap reference voltage source capable of reducing power consumption and improving precision under low voltage |
| CN110502056A (en) * | 2019-08-22 | 2019-11-26 | 成都飞机工业（集团）有限责任公司 | A kind of threshold voltage reference circuit |
| CN110568894A (en) * | 2019-08-22 | 2019-12-13 | 成都飞机工业（集团）有限责任公司 | Four-tube voltage reference circuit |
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Application publication date: 20190319 |