CN110568894A - Four-tube voltage reference circuit - Google Patents
Four-tube voltage reference circuit Download PDFInfo
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- CN110568894A CN110568894A CN201910775986.2A CN201910775986A CN110568894A CN 110568894 A CN110568894 A CN 110568894A CN 201910775986 A CN201910775986 A CN 201910775986A CN 110568894 A CN110568894 A CN 110568894A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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Abstract
The invention relates to a four-tube voltage reference circuit, which comprises a first NMOS tube MN1, a second NMOS tube MN2, a first PMOS tube MP1 and a second PMOS tube MP 2: the drain electrodes of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected and then connected with a power supply voltage; the grid electrode and the source electrode of the first NMOS transistor MN1 are in short circuit, the source electrode and the substrate of the first PMOS transistor MP1 are in short circuit, and the grid electrode and the drain electrode of the second PMOS transistor MP2 are in short circuit; the gate-drain short circuit of the first PMOS transistor MP1 is connected with the substrate of the first NMOS transistor MN1 and the second NMOS transistor MN 2; the source electrode and the substrate of the second PMOS pipe MP2 are in short circuit, and the source electrode and the substrate are connected after being in short circuit and are used as the output reference voltage of the reference circuit. The problem that the conventional band-gap reference circuit cannot work when the power supply voltage is lower than 0.7V starting voltage is solved through the four-tube voltage reference circuit with an ultra-wide temperature range and extremely low power consumption.
Description
Technical Field
the invention belongs to the technical field of integrated circuits, and particularly relates to a four-tube voltage reference circuit.
Background
the voltage reference circuit is an indispensable part in electronic systems including aviation, aerospace and the like, and in some special use environments of aviation and aerospace, the voltage reference circuit is required to be capable of generating a reference voltage source which does not change along with temperature within an ultra-wide temperature range. Also, the power consumption of the voltage reference circuit is as low as possible in view of the requirement for a battery weight as low as possible in aerospace applications. The most widely used traditional bandgap reference circuit cannot work under the ultra-low power supply voltage due to the limitation of the starting voltage, and generally cannot work normally under the voltage lower than 0.7V, so that the power consumption is relatively high.
Disclosure of Invention
The invention aims to overcome the problems in the prior art, and provides a four-tube voltage reference circuit which can be used for a four-tube voltage reference circuit with an ultra-wide temperature range and extremely low power consumption, can work under a power supply voltage of 0.45V, and solves the problem that the conventional band-gap reference circuit cannot work when the power supply voltage is lower than a 0.7V starting voltage.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows.
The utility model provides a four-tube voltage reference circuit, includes first NMOS pipe, second NMOS pipe, first PMOS pipe and second PMOS pipe, its characterized in that:
the drain electrodes of the first NMOS tube and the second NMOS tube are connected and then connected with a power supply voltage VDD;
The grid electrode and the source electrode of the first NMOS tube are in short circuit, the source electrode and the substrate of the first PMOS tube are in short circuit, the grid electrode and the drain electrode of the second PMOS tube are in short circuit, and the grid electrode and the drain electrode are connected after the short circuit and are used as the output voltage VCTAT of the reference circuit;
the grid-drain short circuit of the first PMOS tube is connected with the substrates of the first NMOS tube and the second NMOS tube, and the grid-drain short circuit of the first PMOS tube, the first NMOS tube and the second NMOS tube are grounded after being connected;
and the source electrode and the substrate of the second PMOS tube are in short circuit, and are connected after being in short circuit and are used as the output reference voltage of the reference circuit.
The first NMOS tube and the second NMOS tube are both NMOS tubes with threshold voltage less than or equal to 0.5V.
The first PMOS tube and the second PMOS tube are NMOS tubes with threshold voltage more than or equal to 0.7V.
The first NMOS tube, the second NMOS tube, the first PMOS tube and the second PMOS tube work in a voltage threshold value area.
The formula of the output voltage VCTAT is as follows:
Wherein m1 and m2 are sub-threshold slope factors of the first NMOS transistor and the first PMOS transistor respectively, VT is a thermal voltage, and mu 1 and mu 2 are electron mobilities of the first NMOS transistor and the first PMOS transistor respectively; c0x1 is the gate oxidation capacitance value of the first NMOS tube and the first PMOS tube respectively; VTH1, VTH2 are the threshold voltage of the first NMOS tube and the first PMOS tube respectively; (W/L) N1 and (W/L) P1 are the width-length ratios of the first NMOS transistor and the first PMOS transistor, respectively.
The output reference voltage VREFthe formula of (1) is as follows:
Wherein (W/L)N2、(W/L)P2The width-length ratios of the second NMOS tube and the second PMOS tube are respectively.
The formula is simplified as follows:
the invention has the advantages.
1. The four-tube voltage reference circuit with an ultra-wide temperature range and extremely low power consumption can work under a power supply voltage of 0.45V, and the problem that the conventional band-gap reference circuit cannot work when the power supply voltage is lower than a 0.7V starting voltage is solved; and the power consumption does not exceed two nanowatts, is far lower than that of the traditional band-gap reference, and can realize the work in an ultra-wide temperature range of-55 ℃ to 150 ℃.
drawings
FIG. 1 is a circuit diagram of the present invention.
FIG. 2 is a simulation diagram of the four-transistor voltage reference circuit of the present invention obtained by Hspice simulation.
The labels in the figure are: MN1, a first NMOS transistor, MN2, a second NMOS transistor, MP1, a first PMOS transistor, MP2 and a second PMOS transistor.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
example 1
As shown in fig. 1, a four-transistor voltage reference circuit includes a first NMOS transistor MN1, a second NMOS transistor MN2, a first PMOS transistor MP1, and a second PMOS transistor MP 2:
the drain electrodes of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected and then connected with a power supply Voltage (VDD);
The grid and the source of the first NMOS transistor MN1 are in short circuit, the source and the substrate of the first PMOS transistor MP1 are in short circuit, the grid and the drain of the second PMOS transistor MP2 are in short circuit, and the grid and the drain are connected after short circuit and used as the output voltage V of the reference circuitCTAT；
The grid-drain short circuit of the first PMOS tube MP1 is connected with the substrates of a first NMOS tube MN1 and a second NMOS tube MN2, and the three are grounded VSS after being connected;
The gate-source short circuit of the second NMOS transistor MN2, the source electrode and the substrate short circuit of the second PMOS transistor MP2, and the short circuit of the second NMOS transistor MN2 and the substrate are connected and used as the output reference voltage V of the reference circuitREF。
The four-tube voltage reference circuit with an ultra-wide temperature range and extremely low power consumption can work under a power supply voltage of 0.45V, and the problem that the conventional band-gap reference circuit cannot work when the power supply voltage is lower than a 0.7V starting voltage is solved; and the power consumption does not exceed two nanowatts, is far lower than that of the traditional band-gap reference, and can realize the work in an ultra-wide temperature range of-55 ℃ to 150 ℃.
example 2
As shown in fig. 1, a four-transistor voltage reference circuit includes a first NMOS transistor MN1, a second NMOS transistor MN2, a first PMOS transistor MP1, and a second PMOS transistor MP2, and is characterized in that:
the drain electrodes of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected and then connected with a power supply voltage VDD;
The grid electrode and the source electrode of the first NMOS transistor MN1 are in short circuit, the source electrode and the substrate of the first PMOS transistor MP1 are in short circuit, the grid electrode and the drain electrode of the second PMOS transistor MP2 are in short circuit, and the grid electrode and the drain electrode are connected after short circuit and are used as the output voltage VCTAT of the reference circuit;
The grid-drain short circuit of the first PMOS tube MP1 is connected with the substrates of a first NMOS tube MN1 and a second NMOS tube MN2, and the three are grounded after being connected;
the gate-source short circuit of the second NMOS transistor MN2, the source electrode and the substrate short circuit of the second PMOS transistor MP2, and the two short circuits are connected and used as the output reference voltage of the reference circuit.
The first NMOS transistor MN1 and the second NMOS transistor MN2 are both NMOS transistors with the threshold voltage less than or equal to 0.5V.
The first PMOS tube MP1 and the second PMOS tube MP2 are NMOS tubes with the threshold voltage being more than or equal to 0.7V.
The first NMOS transistor MN1, the second NMOS transistor MN2, the first PMOS transistor MP1 and the second PMOS transistor MP2 all work in a voltage threshold region.
The formula of the output voltage VCTAT is as follows:
Wherein m1 and m2 are sub-threshold slope factors of the first NMOS transistor MN1 and the first PMOS transistor MP1 respectively, VT is a thermal voltage, and μ 1 and μ 2 are electron mobilities of the first NMOS transistor MN1 and the first PMOS transistor MP1 respectively; c0x1 are gate oxidation capacitance values of the first NMOS transistor MN1 and the first PMOS transistor MP1, respectively; VTH1, VTH2 are the threshold voltage of the first NMOS transistor MN1 and the first PMOS transistor MP1 respectively; (W/L) N1, (W/L) P1 are the width-to-length ratios of the first NMOS transistor MN1 and the first PMOS transistor MP1, respectively.
The output reference voltage VREFThe formula of (1) is as follows:
Wherein (W/L)N2、(W/L)P2the width-to-length ratios of the second NMOS transistor MN2 and the second PMOS transistor MP2 are respectively.
The formula is simplified as follows:
the simulation graph shown in fig. 2 was obtained by Hspice simulation, which showed that the reference voltage VREF temperature coefficient generated at the standard process corner (tt corner) was only 32 ppm/deg.c over the temperature range from-55 deg.c to 150 deg.c. Typically (ttcorn, 27 ℃), the supply voltage VDD is 0.45V, the total current consumption is 3.4nA, and the total power consumption is 1.53 nW. The minimum working voltage is less than 0.7V, compared with the traditional reference source, the reference source can work at lower power supply voltage, the working power consumption of the reference source is only a few nanowatts, the extremely low power consumption is realized, and meanwhile, the reference source can work in a wide temperature range of-55 ℃ to 150 ℃, and can provide a stable and reliable reference voltage source for an aerospace electronic system with low power consumption.
The four-tube voltage reference circuit with an ultra-wide temperature range and extremely low power consumption can work under a power supply voltage of 0.45V, and the problem that the conventional band-gap reference circuit cannot work when the power supply voltage is lower than a 0.7V starting voltage is solved; and the power consumption does not exceed two nanowatts, is far lower than that of the traditional band-gap reference, and can realize the work in an ultra-wide temperature range of-55 ℃ to 150 ℃.
The above-mentioned embodiments only express the specific embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for those skilled in the art, without departing from the technical idea of the present application, several changes and modifications can be made, which are all within the protection scope of the present application.
Claims (6)
1. A four-transistor voltage reference circuit comprises a first NMOS transistor (MN1), a second NMOS transistor (MN2), a first PMOS transistor (MP1) and a second PMOS transistor (MP2), and is characterized in that:
The drain electrodes of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are connected and then connected with a power supply voltage VDD;
The grid electrode and the source electrode of the first NMOS transistor (MN1) are in short circuit, the source electrode and the substrate of the first PMOS transistor (MP1) are in short circuit, the grid electrode and the drain electrode of the second PMOS transistor (MP2) are in short circuit, and the grid electrode and the drain electrode are connected after the short circuit and are used as the output voltage VCTAT of the reference circuit;
The grid-drain short circuit of the first PMOS tube (MP1) is connected with the substrates of the first NMOS tube (MN1) and the second NMOS tube (MN2), and the three are grounded after being connected;
the gate-source of the second NMOS transistor (MN2) is in short circuit, the source of the second PMOS transistor (MP2) is in short circuit with the substrate, and the source of the second NMOS transistor and the substrate are connected after being in short circuit and are used as the output reference voltage of the reference circuit.
2. A four-transistor voltage reference circuit as claimed in claim 1, wherein: the first NMOS tube (MN1) and the second NMOS tube (MN2) are both NMOS tubes with the threshold voltage less than or equal to 0.5V.
3. a four-transistor voltage reference circuit as claimed in claim 1, wherein: the first PMOS tube (MP1) and the second PMOS tube (MP2) are NMOS tubes with the threshold voltage being more than or equal to 0.7V. .
4. a four-transistor voltage reference circuit as claimed in claim 1, wherein: the first NMOS transistor (MN1), the second NMOS transistor (MN2), the first PMOS transistor (MP1) and the second PMOS transistor (MP2) all work in a voltage threshold region.
5. A four-transistor voltage reference circuit as claimed in claim 1, wherein: the formula of the output voltage VCTAT is as follows:
Wherein m1 and m2 are sub-threshold slope factors of the first NMOS transistor MN1 and the first PMOS transistor MP1 respectively, VT is a thermal voltage, and μ 1 and μ 2 are electron mobilities of the first NMOS transistor MN1 and the first PMOS transistor MP1 respectively; c0x1 are gate oxidation capacitance values of the first NMOS transistor MN1 and the first PMOS transistor MP1, respectively; VTH1, VTH2 are the threshold voltage of the first NMOS transistor MN1 and the first PMOS transistor MP1 respectively; (W/L) N1, (W/L) P1 are the width-to-length ratios of the first NMOS transistor MN1 and the first PMOS transistor MP1, respectively.
6. a four-transistor voltage reference circuit as claimed in claim 1, wherein: the output reference voltage VREFthe formula of (1) is as follows:
Wherein (W/L)N2、(W/L)P2The width-to-length ratios of the second NMOS transistor MN2 and the second PMOS transistor MP2 are respectively.
the formula is simplified as follows:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910775986.2A CN110568894A (en) | 2019-08-22 | 2019-08-22 | Four-tube voltage reference circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910775986.2A CN110568894A (en) | 2019-08-22 | 2019-08-22 | Four-tube voltage reference circuit |
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| CN110568894A true CN110568894A (en) | 2019-12-13 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110932705A (en) * | 2019-12-18 | 2020-03-27 | 成都飞机工业（集团）有限责任公司 | Power rail switching circuit |
| CN111176361A (en) * | 2020-01-09 | 2020-05-19 | 电子科技大学 | Sub-threshold band-gap reference voltage source based on substrate bias regulation |
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|---|---|---|---|---|
| CN104503530A (en) * | 2015-01-09 | 2015-04-08 | 中国科学技术大学 | High-performance high-reliability reference voltage source of low-voltage complementary metal oxide semiconductor (CMOS) |
| CN107992145A (en) * | 2017-12-06 | 2018-05-04 | 电子科技大学 | A kind of voltage reference circuit with super low-power consumption characteristic |
| CN109491432A (en) * | 2018-11-16 | 2019-03-19 | 电子科技大学 | A kind of voltage reference circuit of ultralow pressure super low-power consumption |
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2019
- 2019-08-22 CN CN201910775986.2A patent/CN110568894A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104503530A (en) * | 2015-01-09 | 2015-04-08 | 中国科学技术大学 | High-performance high-reliability reference voltage source of low-voltage complementary metal oxide semiconductor (CMOS) |
| CN107992145A (en) * | 2017-12-06 | 2018-05-04 | 电子科技大学 | A kind of voltage reference circuit with super low-power consumption characteristic |
| CN109491432A (en) * | 2018-11-16 | 2019-03-19 | 电子科技大学 | A kind of voltage reference circuit of ultralow pressure super low-power consumption |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110932705A (en) * | 2019-12-18 | 2020-03-27 | 成都飞机工业（集团）有限责任公司 | Power rail switching circuit |
| CN111176361A (en) * | 2020-01-09 | 2020-05-19 | 电子科技大学 | Sub-threshold band-gap reference voltage source based on substrate bias regulation |
| CN111176361B (en) * | 2020-01-09 | 2021-03-26 | 电子科技大学 | Sub-threshold band-gap reference voltage source based on substrate bias regulation |
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Application publication date: 20191213 |