CN108415503A - A kind of low-voltage and low-power dissipation reference circuit - Google Patents
A kind of low-voltage and low-power dissipation reference circuit Download PDFInfo
- Publication number
- CN108415503A CN108415503A CN201810542492.5A CN201810542492A CN108415503A CN 108415503 A CN108415503 A CN 108415503A CN 201810542492 A CN201810542492 A CN 201810542492A CN 108415503 A CN108415503 A CN 108415503A
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- pipes
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- 230000005611 electricity Effects 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
Abstract
The invention discloses a kind of low-voltage and low-power dissipation reference circuits, including：One start-up circuit, the startup for completing the reference circuit；One current reference generation circuit, using automatic biasing structure, it is therefore an objective to provide as far as possible independently of the electric current of mains voltage variations, influence of the compensation temperature to reference voltage.One payload circuit, generates the reference current and reference voltage of core, and the precision for generating reference voltage is very high.Without using resistance in circuit of the present invention, also without using triode, entirely MOS transistor, all metal-oxide-semiconductors all to work in subthreshold region, significantly reduce supply voltage and power consumption is especially small.
Description
Technical field
The present invention relates to reference voltage circuit field more particularly to a kind of low-voltage and low-power dissipation reference circuits.
Background technology
In the application of Internet of Things and most of wireless telecommunications, associated receiver circuitry or radiating circuit etc. are all that needs are low
Power consumption, therefore the reference circuit that can generate low-power consumption is very crucial and very necessary for entirely applying.Benchmark electricity
Pith of the road as analog circuit is generally required and is worked normally within the scope of a wider temperature, therefore do not require nothing more than
It is low in energy consumption, it is also necessary to which that performance is stablized, and has preferable temperature characterisitic.Traditional mode may be used band-gap reference circuit and be set
Meter, but its power consumption is relatively large, and need to use resistance and triode, cause chip area larger.
Invention content
To overcome the above-mentioned problems of the prior art, the main purpose of the present invention is to provide a kind of low-voltage and low-power dissipation bases
Quasi- circuit, suitable for the circuit system of low-power consumption.
In view of the above and other objects, the present invention provides a kind of low-voltage and low-power dissipation reference circuit, include at least：
One start-up circuit, the startup for completing the reference circuit, while biasing being provided；
One current reference generation circuit, using automatic biasing structure, it is therefore an objective to provide as far as possible independently of the electricity of mains voltage variations
Stream, influence of the compensation temperature to reference voltage.
One payload circuit, generates the reference current and reference voltage of core, and the precision for generating reference voltage is very high.
The present invention proposes a kind of low-power consumption reference circuit, including：
The start-up circuit is by the first PMOS tube PM1, the second PMOS tube PM2, third PMOS tube PM3, the 4th PMOS tube PM4,
One NMOS tube NM1, the second NMOS tube NM2 and third NMOS tube NM3 are constituted；The source electrode of PM1 pipes and the source electrode of PM4 pipes all with power supply
Voltage VDD is connected；Drain electrode and the drain electrode of NM1 pipes, the grid phase of the grid of NM1 pipes, the grid of PM2 pipes and NM2 pipes of PM1 pipes
Connection；The grid of PM4 pipes is connected with the source electrode of the drain electrode of PM4 pipes and PM3 pipes；The grid of PM3 pipes and the drain electrode of PM3 pipes and
The source electrode of PM2 pipes is connected；The drain electrode of PM2 pipes is connected with the drain electrode of NM2 pipes with the grid of NM3 pipes；The source electrode of NM1 pipes and
The source electrode of NM2 pipes is grounded.
The current reference generates the 5th PMOS tube PM5, the 6th PMOS tube PM6, the 4th NMOS tube NM4, the 5th NMOS tube
NM5 and the 6th NMOS tube NM6 are constituted；The source electrode of PM5 pipes and the source electrode of PM6 pipes are all connected with supply voltage VDD；PM5 pipes
Grid is connected with the drain electrode of PM5 pipes, the grid of PM1 pipes, the drain electrode of NM3 pipes, the drain electrode of the grid of PM6 pipes and NM4 pipes；PM6
The drain electrode of pipe is connected with the grid of the source electrode of NM3 pipes, the grid of NM6 pipes, the drain electrode of NM6 pipes and NM5 pipes；The grid of NM4 pipes
It is connected with the drain electrode of the source electrode of NM6 pipes and NM5 pipes；The source electrode of NM4 pipes and the source electrode ground connection of NM5 pipes.
The payload circuit is made of the 7th PMOS tube PM7 and the 7th NMOS tube NM7；The source electrode and power supply of PM7 pipes
Voltage VDD is connected；The grid of PM7 pipes is connected with the grid of PM1 pipes；The drain electrode of PM7 pipes is managed with the grid and NM7 of NM7 pipes
Drain electrode be connected；The source electrode of NM7 pipes is grounded.
Description of the drawings
The attached drawing constituted part of this application is used to provide further understanding of the present invention, schematic reality of the invention
Example and its explanation are applied for explaining the present invention, is not constituted improper limitations of the present invention.In the accompanying drawings：
Fig. 1 is a kind of low-voltage and low-power dissipation reference circuit figure of the present invention.
Specific implementation mode
In conjunction with shown in Fig. 1, in the following embodiments, the low-voltage and low-power dissipation reference circuit, including：One start-up circuit,
Startup for completing the reference circuit, as a kind of prevention to ensure the biasing under required state；One current reference produces
Raw circuit, using automatic biasing structure, it is therefore an objective to provide as far as possible independently of the electric current of mains voltage variations, compensation temperature is to benchmark
The influence of voltage.One payload circuit generates the reference current and reference voltage of core, generates the precision of reference voltage very
It is high.Without using resistance in circuit of the present invention, also without using triode, entirely MOS transistor, all metal-oxide-semiconductors whole
Subthreshold region is worked in, supply voltage is significantly reduced and power consumption is especially small.
The start-up circuit is by the first PMOS tube PM1, the second PMOS tube PM2, third PMOS tube PM3, the 4th PMOS tube
PM4, the first NMOS tube NM1, the second NMOS tube NM2 and third NMOS tube NM3 are constituted；It is in the drain of the moment of startup, NM2 pipes
The grid of PM1 pipes is simultaneously dragged down then generation electric current by high level, the conducting of NM3 pipes, which flows through PM1 pipes and NM1 pipes, pass through
NM1 pipes are in the branch for being mirrored to NM2 pipes, so that the drain voltage of NM2 pipes reduces and closes NM3 pipes, it is whole to complete
The startup of a circuit.
The current reference generates the 5th PMOS tube PM5, the 6th PMOS tube PM6, the 4th NMOS tube NM4, the 5th NMOS tube
NM5 and the 6th NMOS tube NM6 are constituted；NM4 is managed, and NM5 pipes and NM6 pipes use automatic biasing structure, and are all operated in subthreshold region,
The current variation caused by voltage change is minimized, temperature-compensating is carried out to VREF；Wherein, in order to ensure each transistor all into
Enter sub-threshold status, NM5 pipes have selected HVT-MOSFET, that is, selected the metal-oxide-semiconductor of high threshold；PM5 and PM6 constitutes current mirror, production
The electric current I1 and I2 of generation ratio；Significantly improve the linear sensitivity and power supply rejection ratio of VREF.
The payload circuit is made of the 7th PMOS tube PM7 and the 7th NMOS tube NM7；By NM7 pipes by the electricity
In the transistor that the current mirror that stream reference generating circuit generates is connected to diode, i.e. NM7 pipes；In circuit design, NM7 pipes
Breadth length ratio be designed to W/L=1um/10um, emulated, as a result realistic temperature compensation best results.
The present invention proposes a kind of low-voltage and low-power dissipation reference circuit of no resistance, compared with other circuits, circuit all by
Transistor forms, and does not use resistance, does not also use triode, and structure is simpler.The circuit is set using 0.18 μm of CMOS technology
Meter, can work normally within the scope of the supply voltage of 0.6V to 2.2V, in -25 DEG C to 125 DEG C temperature ranges, output voltage
Variation is only 1.8mV；Power consumption is only 3.8nW.
Although the present invention is illustrated using specific embodiment, the present invention's is not intended to limit to the explanation of embodiment
Range.One skilled in the art is by reference to explanation of the invention, without departing substantially from the spirit and scope of the present invention
In the case of, it is easy to carry out various modifications or embodiment can be combined, these also should be regarded as protection scope of the present invention.
Claims (4)
1. a kind of low-voltage and low-power dissipation reference circuit, which is characterized in that including：
One start-up circuit, the startup for completing the reference circuit, while biasing being provided；
One current reference generation circuit, using automatic biasing structure, it is therefore an objective to provide as far as possible independently of the electricity of mains voltage variations
Stream, influence of the compensation temperature to reference voltage；One payload circuit generates the reference current and reference voltage of core, generates
The precision of reference voltage is very high.
2. a kind of low-voltage and low-power dissipation reference circuit as described in claim 1, it is characterised in that：The start-up circuit is by first
PMOS tube PM1, the second PMOS tube PM2, third PMOS tube PM3, the 4th PMOS tube PM4, the first NMOS tube NM1, the second NMOS tube
NM2 and third NMOS tube NM3 are constituted；The source electrode of PM1 pipes and the source electrode of PM4 pipes are all connected with supply voltage VDD；PM1 pipes
Drain electrode is connected with the grid of the drain electrode of NM1 pipes, the grid of NM1 pipes, the grid of PM2 pipes and NM2 pipes；The grid and PM4 of PM4 pipes
The drain electrode of pipe is connected with the source electrode of PM3 pipes；The grid of PM3 pipes is connected with the source electrode of the drain electrode of PM3 pipes and PM2 pipes；PM2 is managed
Drain electrode be connected with the grid of NM3 pipes with the drain electrode of NM2 pipes；The source electrode of NM1 pipes and the source electrode ground connection of NM2 pipes.
3. a kind of low-voltage and low-power dissipation reference circuit as described in claim 1, it is characterised in that：The current reference is generated by the
Five PMOS tube PM5, the 6th PMOS tube PM6, the 4th NMOS tube NM4, the 5th NMOS tube NM5 and the 6th NMOS tube NM6 are constituted；PM5
The source electrode of pipe and the source electrode of PM6 pipes are all connected with supply voltage VDD；The grid of PM5 pipes and the drain electrode of PM5 pipes, the grid of PM1 pipes
Pole, the drain electrode of NM3 pipes, PM6 pipes grid be connected with the drain electrode of NM4 pipes；The drain electrode of PM6 pipes is managed with the source electrode of NM3 pipes, NM6
The drain electrode of grid, NM6 pipes be connected with the grid of NM5 pipes；The grid of NM4 pipes and the source electrode of NM6 pipes and the drain electrode phase of NM5 pipes
Connection；The source electrode of NM4 pipes and the source electrode ground connection of NM5 pipes.
4. a kind of low-voltage and low-power dissipation reference circuit as described in claim 1, it is characterised in that：The payload circuit is by
Seven PMOS tube PM7 and the 7th NMOS tube NM7 are constituted；The source electrode of PM7 pipes is connected with supply voltage VDD；The grid of PM7 pipes with
The grid of PM1 pipes is connected；The drain electrode of PM7 pipes is connected with the drain electrode of the grid of NM7 pipes and NM7 pipes；The source electrode of NM7 pipes connects
Ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810542492.5A CN108415503A (en) | 2018-05-30 | 2018-05-30 | A kind of low-voltage and low-power dissipation reference circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810542492.5A CN108415503A (en) | 2018-05-30 | 2018-05-30 | A kind of low-voltage and low-power dissipation reference circuit |
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| CN108415503A true CN108415503A (en) | 2018-08-17 |
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| CN201810542492.5A Pending CN108415503A (en) | 2018-05-30 | 2018-05-30 | A kind of low-voltage and low-power dissipation reference circuit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109240407A (en) * | 2018-09-29 | 2019-01-18 | 北京兆易创新科技股份有限公司 | A kind of a reference source |
| CN109491432A (en) * | 2018-11-16 | 2019-03-19 | 电子科技大学 | A kind of voltage reference circuit of ultralow pressure super low-power consumption |
| CN109857183A (en) * | 2019-03-26 | 2019-06-07 | 成都锐成芯微科技股份有限公司 | A kind of reference current source with temperature-compensating |
| CN110377090A (en) * | 2019-07-29 | 2019-10-25 | 北方民族大学 | A kind of reference voltage source circuit |
| CN115328250A (en) * | 2022-08-25 | 2022-11-11 | 广东工业大学 | Low-power consumption CMOS voltage reference source based on DIBL effect compensation |
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| CN103529897A (en) * | 2013-11-01 | 2014-01-22 | 东南大学 | Pure metal oxide semiconductor (MOS) structure voltage reference source with high power supply rejection ratio |
| KR20140028447A (en) * | 2012-08-29 | 2014-03-10 | 엘지디스플레이 주식회사 | Current reference circuit |
| CN104156026A (en) * | 2014-08-26 | 2014-11-19 | 电子科技大学 | Non-resistance and total temperature compensation non-band-gap reference source |
| CN106527572A (en) * | 2016-12-08 | 2017-03-22 | 电子科技大学 | CMOS subthreshold reference circuit with low power dissipation and low temperature drift |
| CN208188713U (en) * | 2018-05-30 | 2018-12-04 | 丹阳恒芯电子有限公司 | A kind of low-voltage and low-power dissipation reference circuit |
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2018
- 2018-05-30 CN CN201810542492.5A patent/CN108415503A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140028447A (en) * | 2012-08-29 | 2014-03-10 | 엘지디스플레이 주식회사 | Current reference circuit |
| CN103529897A (en) * | 2013-11-01 | 2014-01-22 | 东南大学 | Pure metal oxide semiconductor (MOS) structure voltage reference source with high power supply rejection ratio |
| CN104156026A (en) * | 2014-08-26 | 2014-11-19 | 电子科技大学 | Non-resistance and total temperature compensation non-band-gap reference source |
| CN106527572A (en) * | 2016-12-08 | 2017-03-22 | 电子科技大学 | CMOS subthreshold reference circuit with low power dissipation and low temperature drift |
| CN208188713U (en) * | 2018-05-30 | 2018-12-04 | 丹阳恒芯电子有限公司 | A kind of low-voltage and low-power dissipation reference circuit |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109240407A (en) * | 2018-09-29 | 2019-01-18 | 北京兆易创新科技股份有限公司 | A kind of a reference source |
| CN109491432A (en) * | 2018-11-16 | 2019-03-19 | 电子科技大学 | A kind of voltage reference circuit of ultralow pressure super low-power consumption |
| CN109857183A (en) * | 2019-03-26 | 2019-06-07 | 成都锐成芯微科技股份有限公司 | A kind of reference current source with temperature-compensating |
| CN110377090A (en) * | 2019-07-29 | 2019-10-25 | 北方民族大学 | A kind of reference voltage source circuit |
| CN115328250A (en) * | 2022-08-25 | 2022-11-11 | 广东工业大学 | Low-power consumption CMOS voltage reference source based on DIBL effect compensation |
| CN115328250B (en) * | 2022-08-25 | 2024-01-05 | 广东工业大学 | Low-power consumption CMOS voltage reference source based on DIBL effect compensation |
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