CN105094207A - Band gap reference source eliminating bulk effect - Google Patents

Abstract

The invention discloses a band gap reference source eliminating the bulk effect. The band gap reference source eliminating the bulk effect comprises a starting circuit, a nanoampere magnitude-order reference current generating circuit, a temperature compensating circuit and a current mirror. By means of the MOS work characteristics of work in a sub-threshold area, a nanoampere magnitude-order reference current is generated, the cascade current mirror is adopted, power source noise is inhibited, a source electrode coupling differential pair is used for replacing a resistor and a Bipolar transistor adopted in a traditional band gap voltage source, and influences of the bulk effect are eliminated. The method that a MOS gate-to-source voltage with a negative temperature coefficient and a MOS gate-to-source voltage difference with a positive temperature coefficient are mutually adjusted is adopted so that a zero-temperature-drift reference voltage is obtained.

Description

Eliminate the band gap reference of bulk effect

Technical field

The present invention relates to integrated circuit (IC) design field, be specifically related to a kind of band gap reference eliminating bulk effect.

Background technology

At Analogous Integrated Electronic Circuits and hydrid integrated circuit design field, reference voltage source is very important module, be commonly used in the Circuits System such as analog to digital converter (ADC), digital to analog converter (DAC), dc-dc and power amplifier, its effect is for system provides one not with the voltage reference of temperature and mains voltage variations.

Since bandgap voltage reference framework is suggested, due to the performance that it is superior, bandgap voltage reference is widely used among a lot of system, and proposes a lot of improvement project for this kind of framework.But along with the continuous increase of integrated circuit (IC) system integrated level, low-voltage and low-power consumption become more and more important.But bandgap voltage reference causes power consumption comparatively large owing to needing large electric current, and need in the design process to use resistance, diode or BJT transistor to produce PTAT voltage, so this device all needs large chip area.In order to the remaining circuit of energy-conservation application device can be made compatible, bandgap voltage reference will use standard CMOS process, avoid using the device beyond metal-oxide-semiconductor.But the CMOS reference voltage source circuit proposed afterwards, owing to using the CMOS of saturation region, makes power consumption excessive, or owing to there is substrate mediating effect+6, makes poor performance.

Summary of the invention

Technical matters to be solved by this invention is the deficiency of existing reference voltage source poor performance, and provide a kind of band gap reference eliminating bulk effect, it can be operated in sub-threshold region.

For solving the problem, the present invention is achieved by the following technical solutions:

Eliminate the band gap reference of bulk effect, comprise start-up circuit, receive peace reference current generating circuit, temperature-compensation circuit, the first current mirror, the second current mirror and the 3rd current mirror;

Start-up circuit is connected to through the first current mirror and receives peace reference current generating circuit; There is provided electric current when reference voltage source is opened, make reference voltage source break away from degeneracy bias point;

Temperature-compensation circuit connects reference voltage source, and is connected with the 3rd current mirror with the first current mirror, the second current mirror respectively; The characteristic that the gate source voltage difference utilizing the gate source voltage of MOS to have negative temperature coefficient and metal-oxide-semiconductor has positive temperature coefficient (PTC) regulates mutually, obtains the reference voltage of a zero temp shift;

First current mirror connects start-up circuit, temperature-compensation circuit, receives and pacify reference current generating circuit, the second current mirror and the 3rd current mirror; Second current mirror connects temperature-compensation circuit, receives and pacify reference current generating circuit and the first current mirror; 3rd current mirror connects temperature-compensation circuit, receives and pacify reference current generating circuit and the first current mirror; 3 current mirrors copy reference current, for temperature-compensation circuit provides current offset;

Peace magnitude reference current generating circuit of receiving connects the first current mirror, the second current mirror and the 3rd current mirror respectively, utilization is operated in sub-threshold region MOS operating characteristic, produce the reference current received and pacify magnitude, adopt common-source common-gate current mirror, suppress power supply noise, source-coupled differential pair is adopted to eliminate the impact of bulk effect, for current mirror provides reference current.

In such scheme, start-up circuit comprises the 34 metal-oxide-semiconductor, the 35 metal-oxide-semiconductor, the 36 metal-oxide-semiconductor, the 37 metal-oxide-semiconductor and electric capacity Cq.The source electrode of the grid of the 37 metal-oxide-semiconductor, the bottom crown of electric capacity Cq and the 36 metal-oxide-semiconductor is connected to ground GND; The source electrode of the 37 metal-oxide-semiconductor and the source electrode of the 35 metal-oxide-semiconductor are connected to power vd D; The drain electrode of the 37 metal-oxide-semiconductor, the grid of the 34 metal-oxide-semiconductor, the grid of the 35 metal-oxide-semiconductor, the grid of the 36 metal-oxide-semiconductor are connected with the top crown of electric capacity Cq; The drain electrode of the 35 metal-oxide-semiconductor, the drain electrode of the 36 metal-oxide-semiconductor are connected with the source electrode of the 34 metal-oxide-semiconductor; The drain electrode of the 34 metal-oxide-semiconductor is connected to the first current mirror.

In such scheme, peace magnitude reference current generating circuit of receiving comprises the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor.The source electrode of the 8th metal-oxide-semiconductor and the source electrode of the 9th metal-oxide-semiconductor are connected to power vd D; The grid of the 3rd metal-oxide-semiconductor is connected with the grid of the 8th metal-oxide-semiconductor with drain electrode, and is connected to the first current mirror; The drain electrode of the 8th metal-oxide-semiconductor, the source electrode of the 3rd metal-oxide-semiconductor are connected with the source electrode of the 4th metal-oxide-semiconductor, and are connected to the second current mirror; The drain electrode of the 4th metal-oxide-semiconductor is connected to the first current mirror; The drain electrode of the grid of the 4th metal-oxide-semiconductor, the grid of the 5th metal-oxide-semiconductor and the 5th metal-oxide-semiconductor is connected to the first current mirror; The drain electrode of the source electrode of the 5th metal-oxide-semiconductor, the source electrode of the 6th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor is connected to the 3rd current mirror; The grid of the 6th metal-oxide-semiconductor is connected with the grid of the 9th metal-oxide-semiconductor with drain electrode, and is connected to the first current mirror.

In such scheme, temperature-compensation circuit comprises: the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 7th metal-oxide-semiconductor and electric capacity C.The drain electrode of the first metal-oxide-semiconductor, the grid of the first metal-oxide-semiconductor are connected with the top crown of electric capacity C, and are connected to reference voltage source and the second current mirror; The source electrode of the one MOS, the source electrode of the second metal-oxide-semiconductor are connected with the drain electrode of the 7th metal-oxide-semiconductor, and are connected to the first current mirror; The drain and gate of the second metal-oxide-semiconductor connects, and is connected to grid and the 3rd current mirror of the 7th metal-oxide-semiconductor; The source electrode of the 7th metal-oxide-semiconductor and electric capacity bottom crown are connected to ground GND.

In such scheme, the first current mirror comprises the tenth metal-oxide-semiconductor, the 11 metal-oxide-semiconductor, the 12 metal-oxide-semiconductor, the 13 metal-oxide-semiconductor, the 14 metal-oxide-semiconductor, the 15 metal-oxide-semiconductor, the 16 metal-oxide-semiconductor, the 17 metal-oxide-semiconductor, the 18 metal-oxide-semiconductor, the 19 metal-oxide-semiconductor, the 20 metal-oxide-semiconductor, the 21 metal-oxide-semiconductor, the 26 metal-oxide-semiconductor, the 27 metal-oxide-semiconductor, the 28 metal-oxide-semiconductor and the 29 metal-oxide-semiconductor.The source electrode of the 11 metal-oxide-semiconductor, the source electrode of the 13 metal-oxide-semiconductor, the source electrode of the 15 metal-oxide-semiconductor, the source electrode of the 17 metal-oxide-semiconductor, the source electrode of the 19 metal-oxide-semiconductor are connected with the source electrode of the 21 metal-oxide-semiconductor, and are connected to the drain electrode of the source electrode of a MOS, the source electrode of the second metal-oxide-semiconductor and the 7th metal-oxide-semiconductor in temperature-compensation circuit; The grid of the 11 metal-oxide-semiconductor, the grid of the 13 metal-oxide-semiconductor, the grid of the 15 metal-oxide-semiconductor, the grid of the 17 metal-oxide-semiconductor, the grid of the 19 metal-oxide-semiconductor, the grid of the 21 metal-oxide-semiconductor, the drain electrode of the 15 metal-oxide-semiconductor are connected with the source electrode of the 14 metal-oxide-semiconductor; The source electrode of the tenth metal-oxide-semiconductor is connected with the drain electrode of the 11 metal-oxide-semiconductor; The source electrode of the 12 metal-oxide-semiconductor is connected with the drain electrode of the 13 metal-oxide-semiconductor; The source electrode of the 16 metal-oxide-semiconductor is connected with the drain electrode of the 17 metal-oxide-semiconductor; The source electrode of the 18 metal-oxide-semiconductor is connected with the drain electrode of the 19 metal-oxide-semiconductor; The source electrode of the 20 metal-oxide-semiconductor is connected with the drain electrode of the 21 metal-oxide-semiconductor; The grid of the tenth metal-oxide-semiconductor, the grid of the 12 metal-oxide-semiconductor, the grid of the 14 metal-oxide-semiconductor, the grid of the 16 metal-oxide-semiconductor, the grid of the 18 metal-oxide-semiconductor, the grid of the 20 metal-oxide-semiconductor, the drain electrode of the 14 metal-oxide-semiconductor are connected with the drain electrode of the 28 metal-oxide-semiconductor, and are connected to the drain electrode of the 34 metal-oxide-semiconductor in start-up circuit; The drain electrode of the 16 metal-oxide-semiconductor is connected with the drain electrode of the 27 metal-oxide-semiconductor; The drain electrode of the 18 metal-oxide-semiconductor is connected with the drain electrode of the 26 metal-oxide-semiconductor; The grid of the grid of the 26 metal-oxide-semiconductor, the grid of the 27 metal-oxide-semiconductor, the 28 metal-oxide-semiconductor, the grid of the 29 metal-oxide-semiconductor, the drain electrode of the 29 metal-oxide-semiconductor and the drain electrode of the 12 metal-oxide-semiconductor; The source electrode of the 29 metal-oxide-semiconductor is connected to the grid of the grid of the 3rd metal-oxide-semiconductor received in peace magnitude reference current generating circuit, the drain electrode of the 3rd metal-oxide-semiconductor and the 8th metal-oxide-semiconductor; The source electrode of the 28 metal-oxide-semiconductor is connected to the drain electrode of the 4th metal-oxide-semiconductor received in peace magnitude reference current generating circuit; The source electrode of the 27 metal-oxide-semiconductor is connected to the grid of the grid of the 5th metal-oxide-semiconductor received in peace magnitude reference current generating circuit, drain electrode and the 4th metal-oxide-semiconductor; The source electrode of the 26 metal-oxide-semiconductor is connected to the grid of the grid of the 6th metal-oxide-semiconductor received in peace magnitude reference current generating circuit, the drain electrode of the 6th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor; The drain electrode of the tenth metal-oxide-semiconductor is connected to the grid of the grid of the 31 metal-oxide-semiconductor in the second current mirror, drain electrode and the 33 metal-oxide-semiconductor; The drain electrode of the 20 metal-oxide-semiconductor is connected to the grid of the 25 metal-oxide-semiconductor in the 3rd current mirror, the drain electrode of the 25 metal-oxide-semiconductor and the grid of the 23 metal-oxide-semiconductor.

In such scheme, the second current mirror comprises the 30 metal-oxide-semiconductor, the 31 metal-oxide-semiconductor, the 32 metal-oxide-semiconductor and the 33 metal-oxide-semiconductor.The source electrode of the 30 metal-oxide-semiconductor is connected with the source electrode of the 32 metal-oxide-semiconductor, and is connected to the drain electrode of the source electrode of the 3rd metal-oxide-semiconductor in reference current generating circuit, the source electrode of the 4th metal-oxide-semiconductor and the 8th metal-oxide-semiconductor; The drain electrode of the 32 metal-oxide-semiconductor is connected with the source electrode of the 33 metal-oxide-semiconductor; The drain electrode of the grid of the 32 metal-oxide-semiconductor, the grid of the 30 metal-oxide-semiconductor, the 30 metal-oxide-semiconductor is connected with the source electrode of the 31 metal-oxide-semiconductor; The grid of the 33 metal-oxide-semiconductor, the grid of the 31 metal-oxide-semiconductor, the drain electrode of the 31 metal-oxide-semiconductor are connected, and are connected to the drain electrode of the tenth metal-oxide-semiconductor in the first current mirror; The drain and gate that the drain electrode of the 33 metal-oxide-semiconductor is connected to the first metal-oxide-semiconductor in temperature-compensation circuit connects.

In such scheme, the 3rd current mirror comprises the 22 metal-oxide-semiconductor, the 23 metal-oxide-semiconductor, the 24 metal-oxide-semiconductor and the 25 metal-oxide-semiconductor.22, the source electrode of the 24 metal-oxide-semiconductor is connected, and is connected to the drain electrode of the source electrode of the 5th metal-oxide-semiconductor, the source electrode of the 6th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor received in peace magnitude reference current generating circuit; The drain electrode of the 22 metal-oxide-semiconductor is connected with the source electrode of the 23 metal-oxide-semiconductor; The drain electrode of the grid of the 22 metal-oxide-semiconductor, the grid of the 24 metal-oxide-semiconductor, the 24 metal-oxide-semiconductor is connected with the source electrode of the 25 metal-oxide-semiconductor; The grid of the 23 metal-oxide-semiconductor, the grid of the 25 metal-oxide-semiconductor are connected with the drain electrode of the 25 metal-oxide-semiconductor, and are connected to the drain electrode of the 20 metal-oxide-semiconductor in the first current mirror; The drain electrode of the 23 metal-oxide-semiconductor is connected to the drain and gate of the second metal-oxide-semiconductor in temperature-compensation circuit.

Beneficial effect of the present invention is, power consumption is extremely low, is only nanowatt magnitude; Only use the metal-oxide-semiconductor of a type, eliminate the impact of substrate mediating effect+6; And do not use passive resistance, BJT or diode, substantially reduce chip area, reduce production cost, the impact of the reference voltage of output not receptor effect, has high PSRR simultaneously, and low-voltage regulation, better performances.

Accompanying drawing explanation

Fig. 1 is circuit diagram of the present invention.

Fig. 2 is simplification structural representation of the present invention.

Embodiment

Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail:

Eliminate a band gap reference for bulk effect, as shown in Figure 1, comprise start-up circuit, receive and pacify magnitude reference current generating circuit, temperature-compensation circuit and current mirror.Utilization is operated in sub-threshold region MOS operating characteristic, produce the reference current received and pacify magnitude, adopt common-source common-gate current mirror, suppress power supply noise, the resistance adopting source-coupled differential pair to replace adopting in Traditional bandgap voltage source and Bipolar transistor, eliminate the impact of bulk effect, the gate source voltage difference adopting the gate source voltage of MOS to have negative temperature coefficient and metal-oxide-semiconductor has the method that positive temperature coefficient (PTC) regulates mutually, obtains the reference voltage of a zero temp shift.

Start-up circuit is connected to through the first current mirror and receives peace reference current generating circuit; There is provided electric current when reference voltage source is opened, make reference voltage source break away from degeneracy bias point.In a preferred embodiment of the invention, above-mentioned start-up circuit comprise the 34, the 35, the 36, the 37 metal-oxide-semiconductor and electric capacity Cq.The source electrode of the grid of the 37 metal-oxide-semiconductor, the bottom crown of electric capacity Cq, the 36 metal-oxide-semiconductor is connected to ground GND; 37, the source electrode of the 35 metal-oxide-semiconductor is connected to power vd D; The drain electrode of the 37 metal-oxide-semiconductor, the top crown of electric capacity Cq, the 34, the 35, the grid of the 36 metal-oxide-semiconductor connects; 35, the drain electrode of the 36 metal-oxide-semiconductor is connected with the source electrode of the 34 metal-oxide-semiconductor; The drain electrode of the 34 metal-oxide-semiconductor is connected to grid and the drain electrode of the 14 metal-oxide-semiconductor of the first current mirror, when power supply electrifying, provides grid bias, circuit is normally worked to the 14 metal-oxide-semiconductor.

Peace magnitude reference current generating circuit of receiving connects the first current mirror, the second current mirror and the 3rd current mirror respectively, utilization is operated in sub-threshold region MOS operating characteristic, produce the reference current received and pacify magnitude, adopt common-source common-gate current mirror, suppress power supply noise, source-coupled differential pair is adopted to eliminate the impact of bulk effect, for current mirror provides reference current.In a preferred embodiment of the invention, above-mentioned peace magnitude reference current generating circuit of receiving comprises the 3rd, the 4th, the 5th, the 6th, the 8th, the 9th metal-oxide-semiconductor.Eight, the source electrode of the 9th metal-oxide-semiconductor is connected to power vd D; The grid of the 3rd metal-oxide-semiconductor is connected with the grid of the 8th metal-oxide-semiconductor with drain electrode, and is connected to the source electrode of the 29 metal-oxide-semiconductor of the first current mirror; The drain electrode and the 3rd of the 8th metal-oxide-semiconductor, the source electrode of the 4th metal-oxide-semiconductor are connected, and be connected to the 32 of the second current mirror the, the source electrode of 30 metal-oxide-semiconductors; The drain electrode of the 4th metal-oxide-semiconductor is connected with the source electrode of the 28 metal-oxide-semiconductor in the first current mirror; Four, the grid of the 5th metal-oxide-semiconductor is connected, and is connected to the source electrode of the 27 metal-oxide-semiconductor in the drain electrode of the 5th metal-oxide-semiconductor and the first current mirror; Five, the source electrode of the 6th metal-oxide-semiconductor is connected with the drain electrode of the 9th metal-oxide-semiconductor, and is connected to the source electrode of the 22 in the 3rd current mirror, 24 metal-oxide-semiconductors; The grid of the 6th metal-oxide-semiconductor is connected with the grid of the 9th metal-oxide-semiconductor with drain electrode, and is connected to the source electrode of the 26 metal-oxide-semiconductor of the first current mirror; The reference current received and pacify magnitude is provided, and eliminates the impact of bulk effect.

Temperature-compensation circuit connects reference voltage source, and is connected with the 3rd current mirror with the first current mirror, the second current mirror respectively; The characteristic that the gate source voltage difference utilizing the gate source voltage of MOS to have negative temperature coefficient and metal-oxide-semiconductor has positive temperature coefficient (PTC) regulates mutually, obtains the reference voltage of a zero temp shift.In a preferred embodiment of the invention, said temperature compensating circuit comprise first, second, the 7th metal-oxide-semiconductor and electric capacity C.The drain and gate of the first metal-oxide-semiconductor connects, and the drain electrode of the 33 metal-oxide-semiconductor be connected in the second current mirror and the top crown of electric capacity C, as reference voltage output end; The source electrode of the one MOS, the second metal-oxide-semiconductor is connected with the drain electrode of the 7th metal-oxide-semiconductor, and with the 11 in the first current mirror, the 13, the 15, the 17, the 19, the source electrode of the 21 metal-oxide-semiconductor is connected; The drain and gate of the second metal-oxide-semiconductor connects, and is connected to the drain electrode of the 23 metal-oxide-semiconductor in the grid of the 7th metal-oxide-semiconductor and the 3rd current mirror; The source electrode of the 7th metal-oxide-semiconductor and electric capacity bottom crown are connected to ground GND; The gate source voltage difference adopting the gate source voltage of MOS to have negative temperature coefficient and metal-oxide-semiconductor has the method that positive temperature coefficient (PTC) regulates mutually, obtains the reference voltage of a zero temp shift.

Current mirror comprises: first, second, and third current mirror, copies reference current, for temperature-compensation circuit provides current offset.

First current mirror connects start-up circuit, temperature-compensation circuit, receives and pacify reference current generating circuit, the second current mirror and the 3rd current mirror.In a preferred embodiment of the invention, above-mentioned first current mirror comprise the tenth, the 11, the 12, the 13, the 14, the 15, the 16, the 17, the 18, the 19, the 20, the 21, the 26, the 27, the 28, the 29 metal-oxide-semiconductor.11, the 13, the 15, the 17, the 19, the source electrode of the 21 metal-oxide-semiconductor is connected; 11, the 13, the 15, the 17, the 19, the grid of the 21 metal-oxide-semiconductor is connected, and is connected to the drain electrode of the 15 metal-oxide-semiconductor and the source electrode of the 14 metal-oxide-semiconductor; The source electrode of the tenth metal-oxide-semiconductor is connected with the drain electrode of the 11 metal-oxide-semiconductor; The source electrode of the 12 metal-oxide-semiconductor is connected with the drain electrode of the 13 metal-oxide-semiconductor; The source electrode of the 16 metal-oxide-semiconductor is connected with the drain electrode of the 17 metal-oxide-semiconductor; The source electrode of the 18 metal-oxide-semiconductor is connected with the drain electrode of the 19 metal-oxide-semiconductor; The source electrode of the 20 metal-oxide-semiconductor is connected with the drain electrode of the 21 metal-oxide-semiconductor; Ten, the 12, the 14, the 16, the 18, the grid of the 20 metal-oxide-semiconductor is connected, and is connected to the drain electrode of the 34 metal-oxide-semiconductor in the drain electrode of the 14 metal-oxide-semiconductor, the drain electrode of the 28 metal-oxide-semiconductor and start-up circuit; Grid, the drain electrode of the drain electrode of the tenth metal-oxide-semiconductor and the 31 metal-oxide-semiconductor in the second current mirror are connected with the grid of the 33 metal-oxide-semiconductor; 16, the drain electrode of the 27 metal-oxide-semiconductor is connected; 18, the drain electrode of the 26 metal-oxide-semiconductor is connected; 26, the 27, the 28, the grid of the 29 metal-oxide-semiconductor is connected, and be connected to the 29, the drain electrode of the 12 metal-oxide-semiconductor; The grid of the source electrode of the 29 metal-oxide-semiconductor and the grid of the 3rd metal-oxide-semiconductor in Na An magnitude reference current generating circuit, drain electrode and the 8th metal-oxide-semiconductor is connected; The source electrode of the 28 metal-oxide-semiconductor is connected with the drain electrode of the 4th metal-oxide-semiconductor in Na An magnitude reference current generating circuit; The grid of the source electrode of the 27 metal-oxide-semiconductor and the grid of the 5th metal-oxide-semiconductor in Na An magnitude reference current generating circuit, drain electrode and the 4th metal-oxide-semiconductor is connected; The grid of the source electrode of the 26 metal-oxide-semiconductor and the grid of the 6th metal-oxide-semiconductor in Na An magnitude reference current generating circuit, drain electrode and the 9th metal-oxide-semiconductor is connected; The drain electrode of the 20 metal-oxide-semiconductor is connected with the grid of the 23 metal-oxide-semiconductor with the grid of the 25 metal-oxide-semiconductor in the 3rd current mirror, drain electrode.

Second current mirror connects temperature-compensation circuit, receives and pacify reference current generating circuit and the first current mirror.In a preferred embodiment of the invention, above-mentioned second current mirror comprise the 30, the 31, the 32, the 33 metal-oxide-semiconductor.30, the source electrode of the 32 metal-oxide-semiconductor is connected, and is connected to the source electrode of the 3rd, the 4th metal-oxide-semiconductor and the drain electrode of the 8th metal-oxide-semiconductor in reference current generating circuit; The drain electrode of the 32 metal-oxide-semiconductor is connected with the source electrode of the 33 metal-oxide-semiconductor; 32, the grid of the 30 metal-oxide-semiconductor is connected, and is connected to the drain electrode of the 30 metal-oxide-semiconductor and the source electrode of the 31 metal-oxide-semiconductor; 33, the grid of the 31 metal-oxide-semiconductor is connected, and is connected to the drain electrode of the tenth metal-oxide-semiconductor in the drain electrode of the 31 metal-oxide-semiconductor and the first current mirror.

3rd current mirror connects temperature-compensation circuit, receives and pacify reference current generating circuit and the first current mirror.In a preferred embodiment of the invention, above-mentioned 3rd current mirror comprise the 22, the 23, the 24, the 25 metal-oxide-semiconductor.22, the source electrode of the 24 metal-oxide-semiconductor is connected, and is connected to the source electrode of the 5th, the 6th metal-oxide-semiconductor and the drain electrode of the 9th metal-oxide-semiconductor in reference current generating circuit; The drain electrode of the 22 metal-oxide-semiconductor is connected with the source electrode of the 23 metal-oxide-semiconductor; 22, the grid of the 24 metal-oxide-semiconductor is connected, and is connected to the drain electrode of the 24 metal-oxide-semiconductor and the source electrode of the 25 metal-oxide-semiconductor; 23, the grid of the 25 metal-oxide-semiconductor is connected, and is connected to the drain electrode of the 20 metal-oxide-semiconductor in the drain electrode of the 25 metal-oxide-semiconductor and the first current mirror; Above-mentioned each current mirror is used for replica current.

Principle of work of the present invention is:

In start-up circuit, the 35, the 36 metal-oxide-semiconductor forms phase inverter, is used for the source electrode of insulating power supply and the 34 metal-oxide-semiconductor; 37 metal-oxide-semiconductor grounded-grid, is equivalent to a resistance.When circuit powers on, power supply is charged to electric capacity Cq by the 37 metal-oxide-semiconductor, now electric capacity Cq top crown voltage is low level, make the 36 metal-oxide-semiconductor cut-off, 34,35 metal-oxide-semiconductor conductings, by electric current by the 34,35 metal-oxide-semiconductors are injected in reference current generating circuit, break away from degeneracy point; When power supply is to electric capacity Cq charging complete, electric capacity top crown voltage is made to be high level, make the 36 metal-oxide-semiconductor conducting, 34,35 metal-oxide-semiconductor cut-offs, start-up circuit and reference source depart from, and the source potential of the 34 metal-oxide-semiconductor is pulled down to ground, avoids and directly contacts with power supply, reduce the impact of start-up circuit on reference source.

With reference to accompanying drawing 2, core circuit of the present invention comprises receiving pacifies magnitude reference current generating circuit and temperature-compensation circuit.Be made up of to receive the 3rd, the 4th, the 5th, the 6th, the 8th, the 9th metal-oxide-semiconductor and pacify magnitude reference current generating circuit, wherein, the 8th, the 9th metal-oxide-semiconductor is operated in saturation region, and the 3rd, the 4th, the 5th, the 6th metal-oxide-semiconductor is operated in sub-threshold region.The I-V characteristic that metal-oxide-semiconductor is operated in sub-threshold region can be expressed as:

$I_D={\mathrm{KI}}_0\exp \left(\frac{V_{GS}-V_{TH}}{{\mathrm{\ηV}}_T}\right)\[1-\exp (-\frac{V_{DS}}{V_T})\]$

In formula, I _dit is the drain current of metal-oxide-semiconductor; K=K/L is the breadth length ratio of metal-oxide-semiconductor; for characteristic current, μ=μ ₀(T ₀/ T) ^mthe electron mobility of metal-oxide-semiconductor, T ₀reference temperature, μ ₀reference temperature T ₀lower electron mobility, T is absolute temperature, and m is humidity index, C _oX=ε _oX/ t _oXgate oxide capacitance, ε _oXoxide dielectric constant, t _oXbe oxidated layer thickness, η is sub-threshold region slope factor, V _gSthe gate source voltage of metal-oxide-semiconductor, V _t=k _bt/q is thermal voltage, k _bbe Boltzmann constant, q is electron charge, V _tHthe threshold voltage of metal-oxide-semiconductor, V _dSit is the drain-source voltage of metal-oxide-semiconductor.

Work as V _dSbe greater than 3 times of V _ttime, can V be ignored _dSimpact, can obtain:

$I_D={\mathrm{KI}}_0\exp \left(\frac{V_{GS}-V_{TH}}{{\mathrm{\ηV}}_T}\right)$

And then the gate source voltage of MOSFETs can be obtained:

$V_{GS}=V_{TH}+{\mathrm{\ηV}}_T\ln \left(\frac{I_D}{K\·I_0}\right)$

η depends on the electric capacity of gate oxide and depletion layer, and the present invention supposes that η is a constant.

Be operated in the I-V characteristic of saturation region metal-oxide-semiconductor, can be expressed as:

$I_D=\frac{{\mathrm{\μC}}_{OX}K}{2}{(V_{GS}-V_{TH})}^2$

And then can obtain

$V_{GS}=V_{TH}+\sqrt{\frac{2I_D}{{\mathrm{\μC}}_{OX}K}}$

In formula, μ is electron mobility, C _oXfor gate oxide capacitance, K is breadth length ratio, I _dfor drain current, V _tHfor threshold voltage, V _gSfor gate source voltage.

Then, the gate source voltage difference of the 8th, the 9th metal-oxide-semiconductor can be expressed as:

${\mathrm{\ΔV}}_p=V_{GS8}-V_{GS9}=\sqrt{\frac{2I_D}{{\mathrm{\μ}}_p{C}_{OX}}}(\sqrt{\frac{1}{K_8}}-\sqrt{\frac{1}{K_9}})$

Meanwhile, the gate source voltage difference of the 8th, the 9th metal-oxide-semiconductor also can be expressed as:

${\mathrm{\ΔV}}_p=V_{GS3}-V_{GS4}+V_{GS5}-V_{GS6}={\mathrm{\ηV}}_T\ln \left(\frac{K_4}{K_3}\right)+{\mathrm{\ηV}}_T\ln \left(\frac{K_6}{K_5}\right)={\mathrm{\ηV}}_T\ln \left(\frac{K_4}{K_3}\·\frac{K_6}{K_5}\right)$

Then can in the hope of the reference current I of reference current source and drain current I _d:

$I=I_D=\frac{{\mathrm{\μ}}_p{C}_{OX}{K}_9}{2{(N-1)}^2}\·{\left({\mathrm{\ηV}}_T\ln \left(\frac{K_4}{K_3}\·\frac{K_6}{K_5}\right)\right)}^2$

Wherein, $N=\sqrt{K_9/K_8}$

By μ=μ ₀(T ₀/ T) ^m

The relation between reference current I and absolute temperature T can be drawn.

$I=\left({\mathrm{\μ}}_p\·V_T^2\right)\·\left(\frac{C_{OX}{K}_9}{2{\left(N-1\right)}^2}\·{\left(\mathrm{\η}\ln \left(\frac{K_2}{K_1}\·\frac{K_4}{K_3}\right)\right)}^2\right)=\left({\mathrm{\μ}}_{p0}\·V_{T0}^2\right)\·\left(\frac{C_{\mathrm{OX}}{K}_9}{2{\left(N-1\right)}^2}\·{\left(\mathrm{\η}\ln \left(\frac{K_2}{K_1}\·\frac{K_4}{K_3}\right)\right)}^2\right)\·{\left(\frac{T}{T_0}\right)}^{2-m}$

As can be seen from the above equation, reference current is not subject to the impact of substrate mediating effect+6, and to supply voltage and technique insensitive.Only have in the expression formula of reference current I last for the item of temperature correlation, humidity index m be one between 1.5 ~ 2 constant, therefore exponential factor 2-m is very little; Reference current shows good temperature characterisitic.

Temperature-compensation circuit by first, second, the 7th metal-oxide-semiconductor forms, the 7th metal-oxide-semiconductor is operated in saturation region, and first, second metal-oxide-semiconductor is operated in sub-threshold region.And then the expression formula that can obtain output reference voltage Vref is:

Vref＝V _GS1-V _GS2+V _GS7

Further derivation can obtain

$V_{ref}=V_{TH7}+\sqrt{\frac{4I}{{\mathrm{\μ}}_n{C}_{OX}{K}_7}}+{\mathrm{\ηV}}_T\ln \left(\frac{K_2}{K_1}\right)=V_{TH7}+{\mathrm{\ηV}}_T\ln \left(\frac{K_2}{K_1}\right)+{\mathrm{\ηV}}_T\ln \left(\frac{K_4}{K_3}\·\frac{K_6}{K_5}\right)\·\frac{1}{N-1}\·\sqrt{\frac{{\mathrm{\μ}}_p}{{\mathrm{\μ}}_n}}\·\sqrt{\frac{2K_9}{K_7}}$

Due to be similar to the constant of temperature, temperature-compensation circuit can obtain good temperature characterisitic.

Threshold voltage V _tHtemperature characterisitic: V _tH=V _tH0-κ T, wherein V _tH0threshold voltage when be absolute temperature being 0K, κ is threshold voltage V _tHtemperature coefficient.

To reference voltage differential, can obtain

$\frac{\∂V_{ref}}{\∂T}=-\mathrm{\κ}+\frac{{\mathrm{\ηk}}_B}{q}\ln \left(\frac{K_2}{K_1}\right)+\frac{{\mathrm{\ηk}}_B}{q}\ln \left(\frac{K_4}{K_3}\·\frac{K_6}{K_5}\right)\·\frac{1}{N-1}\·\sqrt{\frac{{\mathrm{\μ}}_p}{{\mathrm{\μ}}_n}}\·\sqrt{\frac{2K_9}{K_3}}$

In formula, k _bfor Boltzmann constant, as can be seen from the above equation, can by the reference voltage regulating the breadth length ratio of metal-oxide-semiconductor to obtain a zero-temperature coefficient.

The present invention mainly solves that prior art circuits power consumption is large, chip area is large, device does not mate with standard CMOS process and the problem of the impact of receptor effect.Be made up of four partial circuits: (1) start-up circuit, by the 34, the 35, the 36, the 37 metal-oxide-semiconductor and electric capacity Cq form, Main Function is: when power supply electrifying, helps reference source to break away from degeneracy bias point, enters normal operating conditions; (2) peace magnitude reference current generating circuit is received, be made up of the 3rd, the 4th, the 5th, the 6th, the 8th and the 9th metal-oxide-semiconductor, utilization is operated in sub-threshold region MOS operating characteristic, produce the reference current received and pacify magnitude, adopt common-source common-gate current mirror, suppress power supply noise, the resistance adopting source-coupled differential pair to replace adopting in Traditional bandgap voltage source and Bipolar transistor, not only reduce power consumption and chip area, and eliminate the impact of bulk effect; (3) temperature-compensation circuit, by first, second, the 7th metal-oxide-semiconductor and electric capacity C form, the gate source voltage difference adopting the gate source voltage of MOS to have negative temperature coefficient and metal-oxide-semiconductor has the method that positive temperature coefficient (PTC) regulates mutually, obtains the reference voltage of a zero temp shift; (4) current mirror, comprises: first, second, and third current mirror.First metal-oxide-semiconductor and the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor and the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor form three groups of PTAT voltage generation circuits respectively with current mirror; The PTAT circuit that first metal-oxide-semiconductor and the second metal-oxide-semiconductor form and the 7th metal-oxide-semiconductor form temperature-compensation circuit, and another two groups of PTAT circuit and the 8th, the 9th metal-oxide-semiconductor form to receive pacifies magnitude reference current source.Except the 7th, the 8th and the 9th metal-oxide-semiconductor is operated in saturation region in circuit, other metal-oxide-semiconductors are all operated in sub-threshold region.Circuit adopts the PMOS that electron mobility is less to produce reference current; And using being operated in the 7th metal-oxide-semiconductor of saturation region as the total load of circuit, avoiding it to become branch road separately, consuming multiple current.This structure can eliminate the impact of bulk effect, completely compatible common CMOS technology, has that power consumption is extremely low, chip area is little, Power Supply Rejection Ratio is high simultaneously, thus reduces system cost.

Claims (7)

1. eliminate the band gap reference of bulk effect, it is characterized in that: comprise start-up circuit, receive peace reference current generating circuit, temperature-compensation circuit, the first current mirror, the second current mirror and the 3rd current mirror;

Start-up circuit is connected to through the first current mirror and receives peace reference current generating circuit; There is provided electric current when reference voltage source is opened, make reference voltage source break away from degeneracy bias point;

Temperature-compensation circuit connects reference voltage source, and is connected with the 3rd current mirror with the first current mirror, the second current mirror respectively; The characteristic that the gate source voltage difference utilizing the gate source voltage of MOS to have negative temperature coefficient and metal-oxide-semiconductor has positive temperature coefficient (PTC) regulates mutually, obtains the reference voltage of a zero temp shift;

First current mirror connects start-up circuit, temperature-compensation circuit, receives and pacify reference current generating circuit, the second current mirror and the 3rd current mirror; Second current mirror connects temperature-compensation circuit, receives and pacify reference current generating circuit and the first current mirror; 3rd current mirror connects temperature-compensation circuit, receives and pacify reference current generating circuit and the first current mirror; 3 current mirrors copy reference current, for temperature-compensation circuit provides current offset;

Peace magnitude reference current generating circuit of receiving connects the first current mirror, the second current mirror and the 3rd current mirror respectively, utilization is operated in sub-threshold region MOS operating characteristic, produce the reference current received and pacify magnitude, adopt common-source common-gate current mirror, suppress power supply noise, source-coupled differential pair is adopted to eliminate the impact of bulk effect, for current mirror provides reference current.

2. the band gap reference of elimination bulk effect according to claim 1, is characterized in that: start-up circuit comprises the 34 metal-oxide-semiconductor, the 35 metal-oxide-semiconductor, the 36 metal-oxide-semiconductor, the 37 metal-oxide-semiconductor and electric capacity Cq;

Wherein, the source electrode of the grid of the 37 metal-oxide-semiconductor, the bottom crown of electric capacity Cq and the 36 metal-oxide-semiconductor is connected to ground GND; The source electrode of the 37 metal-oxide-semiconductor and the source electrode of the 35 metal-oxide-semiconductor are connected to power vd D; The drain electrode of the 37 metal-oxide-semiconductor, the grid of the 34 metal-oxide-semiconductor, the grid of the 35 metal-oxide-semiconductor, the grid of the 36 metal-oxide-semiconductor are connected with the top crown of electric capacity Cq; The drain electrode of the 35 metal-oxide-semiconductor, the drain electrode of the 36 metal-oxide-semiconductor are connected with the source electrode of the 34 metal-oxide-semiconductor; The drain electrode of the 34 metal-oxide-semiconductor is connected to the first current mirror.

3. the band gap reference of elimination bulk effect according to claim 1, is characterized in that: peace magnitude reference current generating circuit of receiving comprises the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor;

Wherein, the source electrode of the 8th metal-oxide-semiconductor and the source electrode of the 9th metal-oxide-semiconductor are connected to power vd D; The grid of the 3rd metal-oxide-semiconductor is connected with the grid of the 8th metal-oxide-semiconductor with drain electrode, and is connected to the first current mirror; The drain electrode of the 8th metal-oxide-semiconductor, the source electrode of the 3rd metal-oxide-semiconductor are connected with the source electrode of the 4th metal-oxide-semiconductor, and are connected to the second current mirror; The drain electrode of the 4th metal-oxide-semiconductor is connected to the first current mirror; The drain electrode of the grid of the 4th metal-oxide-semiconductor, the grid of the 5th metal-oxide-semiconductor and the 5th metal-oxide-semiconductor is connected to the first current mirror; The drain electrode of the source electrode of the 5th metal-oxide-semiconductor, the source electrode of the 6th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor is connected to the 3rd current mirror; The grid of the 6th metal-oxide-semiconductor is connected with the grid of the 9th metal-oxide-semiconductor with drain electrode, and is connected to the first current mirror.

4. the band gap reference of elimination bulk effect according to claim 1, is characterized in that: temperature-compensation circuit comprises: the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 7th metal-oxide-semiconductor and electric capacity C;

Wherein, the drain electrode of the first metal-oxide-semiconductor, the grid of the first metal-oxide-semiconductor are connected with the top crown of electric capacity C, and are connected to reference voltage source and the second current mirror; The source electrode of the one MOS, the source electrode of the second metal-oxide-semiconductor are connected with the drain electrode of the 7th metal-oxide-semiconductor, and are connected to the first current mirror; The drain and gate of the second metal-oxide-semiconductor connects, and is connected to grid and the 3rd current mirror of the 7th metal-oxide-semiconductor; The source electrode of the 7th metal-oxide-semiconductor and electric capacity bottom crown are connected to ground GND.

5. according to the band gap reference of the elimination bulk effect in Claims 1 to 4 described in any one, it is characterized in that: the first current mirror comprises the tenth metal-oxide-semiconductor, the 11 metal-oxide-semiconductor, the 12 metal-oxide-semiconductor, the 13 metal-oxide-semiconductor, the 14 metal-oxide-semiconductor, the 15 metal-oxide-semiconductor, the 16 metal-oxide-semiconductor, the 17 metal-oxide-semiconductor, the 18 metal-oxide-semiconductor, the 19 metal-oxide-semiconductor, the 20 metal-oxide-semiconductor, the 21 metal-oxide-semiconductor, the 26 metal-oxide-semiconductor, the 27 metal-oxide-semiconductor, the 28 metal-oxide-semiconductor and the 29 metal-oxide-semiconductor;

Wherein, the source electrode of the 11 metal-oxide-semiconductor, the source electrode of the 13 metal-oxide-semiconductor, the source electrode of the 15 metal-oxide-semiconductor, the source electrode of the 17 metal-oxide-semiconductor, the source electrode of the 19 metal-oxide-semiconductor are connected with the source electrode of the 21 metal-oxide-semiconductor, and are connected to the drain electrode of the source electrode of a MOS, the source electrode of the second metal-oxide-semiconductor and the 7th metal-oxide-semiconductor in temperature-compensation circuit; The grid of the 11 metal-oxide-semiconductor, the grid of the 13 metal-oxide-semiconductor, the grid of the 15 metal-oxide-semiconductor, the grid of the 17 metal-oxide-semiconductor, the grid of the 19 metal-oxide-semiconductor, the grid of the 21 metal-oxide-semiconductor, the drain electrode of the 15 metal-oxide-semiconductor are connected with the source electrode of the 14 metal-oxide-semiconductor; The source electrode of the tenth metal-oxide-semiconductor is connected with the drain electrode of the 11 metal-oxide-semiconductor; The source electrode of the 12 metal-oxide-semiconductor is connected with the drain electrode of the 13 metal-oxide-semiconductor; The source electrode of the 16 metal-oxide-semiconductor is connected with the drain electrode of the 17 metal-oxide-semiconductor; The source electrode of the 18 metal-oxide-semiconductor is connected with the drain electrode of the 19 metal-oxide-semiconductor; The source electrode of the 20 metal-oxide-semiconductor is connected with the drain electrode of the 21 metal-oxide-semiconductor; The grid of the tenth metal-oxide-semiconductor, the grid of the 12 metal-oxide-semiconductor, the grid of the 14 metal-oxide-semiconductor, the grid of the 16 metal-oxide-semiconductor, the grid of the 18 metal-oxide-semiconductor, the grid of the 20 metal-oxide-semiconductor, the drain electrode of the 14 metal-oxide-semiconductor are connected with the drain electrode of the 28 metal-oxide-semiconductor, and are connected to the drain electrode of the 34 metal-oxide-semiconductor in start-up circuit; The drain electrode of the 16 metal-oxide-semiconductor is connected with the drain electrode of the 27 metal-oxide-semiconductor; The drain electrode of the 18 metal-oxide-semiconductor is connected with the drain electrode of the 26 metal-oxide-semiconductor; The grid of the grid of the 26 metal-oxide-semiconductor, the grid of the 27 metal-oxide-semiconductor, the 28 metal-oxide-semiconductor, the grid of the 29 metal-oxide-semiconductor, the drain electrode of the 29 metal-oxide-semiconductor and the drain electrode of the 12 metal-oxide-semiconductor; The source electrode of the 29 metal-oxide-semiconductor is connected to the grid of the grid of the 3rd metal-oxide-semiconductor received in peace magnitude reference current generating circuit, the drain electrode of the 3rd metal-oxide-semiconductor and the 8th metal-oxide-semiconductor; The source electrode of the 28 metal-oxide-semiconductor is connected to the drain electrode of the 4th metal-oxide-semiconductor received in peace magnitude reference current generating circuit; The source electrode of the 27 metal-oxide-semiconductor is connected to the grid of the grid of the 5th metal-oxide-semiconductor received in peace magnitude reference current generating circuit, drain electrode and the 4th metal-oxide-semiconductor; The source electrode of the 26 metal-oxide-semiconductor is connected to the grid of the grid of the 6th metal-oxide-semiconductor received in peace magnitude reference current generating circuit, the drain electrode of the 6th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor; The drain electrode of the tenth metal-oxide-semiconductor is connected to the grid of the grid of the 31 metal-oxide-semiconductor in the second current mirror, drain electrode and the 33 metal-oxide-semiconductor; The drain electrode of the 20 metal-oxide-semiconductor is connected to the grid of the 25 metal-oxide-semiconductor in the 3rd current mirror, the drain electrode of the 25 metal-oxide-semiconductor and the grid of the 23 metal-oxide-semiconductor.

6. according to the band gap reference of the elimination bulk effect in Claims 1 to 4 described in any one, it is characterized in that: the second current mirror comprises the 30 metal-oxide-semiconductor, the 31 metal-oxide-semiconductor, the 32 metal-oxide-semiconductor and the 33 metal-oxide-semiconductor;

Wherein, the source electrode of the 30 metal-oxide-semiconductor is connected with the source electrode of the 32 metal-oxide-semiconductor, and is connected to the drain electrode of the source electrode of the 3rd metal-oxide-semiconductor in reference current generating circuit, the source electrode of the 4th metal-oxide-semiconductor and the 8th metal-oxide-semiconductor; The drain electrode of the 32 metal-oxide-semiconductor is connected with the source electrode of the 33 metal-oxide-semiconductor; The drain electrode of the grid of the 32 metal-oxide-semiconductor, the grid of the 30 metal-oxide-semiconductor, the 30 metal-oxide-semiconductor is connected with the source electrode of the 31 metal-oxide-semiconductor; The grid of the 33 metal-oxide-semiconductor, the grid of the 31 metal-oxide-semiconductor, the drain electrode of the 31 metal-oxide-semiconductor are connected, and are connected to the drain electrode of the tenth metal-oxide-semiconductor in the first current mirror; The drain and gate that the drain electrode of the 33 metal-oxide-semiconductor is connected to the first metal-oxide-semiconductor in temperature-compensation circuit connects.

7. according to the band gap reference of the elimination bulk effect in Claims 1 to 4 described in any one, it is characterized in that: the 3rd current mirror comprises the 22 metal-oxide-semiconductor, the 23 metal-oxide-semiconductor, the 24 metal-oxide-semiconductor and the 25 metal-oxide-semiconductor;

Wherein, the 22, the source electrode of the 24 metal-oxide-semiconductor is connected, and is connected to the drain electrode of the source electrode of the 5th metal-oxide-semiconductor, the source electrode of the 6th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor received in peace magnitude reference current generating circuit; The drain electrode of the 22 metal-oxide-semiconductor is connected with the source electrode of the 23 metal-oxide-semiconductor; The drain electrode of the grid of the 22 metal-oxide-semiconductor, the grid of the 24 metal-oxide-semiconductor, the 24 metal-oxide-semiconductor is connected with the source electrode of the 25 metal-oxide-semiconductor; The grid of the 23 metal-oxide-semiconductor, the grid of the 25 metal-oxide-semiconductor are connected with the drain electrode of the 25 metal-oxide-semiconductor, and are connected to the drain electrode of the 20 metal-oxide-semiconductor in the first current mirror; The drain electrode of the 23 metal-oxide-semiconductor is connected to the drain and gate of the second metal-oxide-semiconductor in temperature-compensation circuit.