CN104111682A - Low-power-consumption and low-temperature-coefficient reference source circuit - Google Patents

Abstract

The invention provides a low-power-consumption and low-temperature-coefficient reference source circuit, and relates to the field of analogue integrated circuits. The low-power-consumption and low-temperature-coefficient reference source circuit comprises a starting circuit, a current generating circuit, a reference voltage generating circuit and a substrate biasing circuit, wherein the current generating circuit is directly proportional to temperature; the current generating circuit which is directly proportional to the temperature is used for generating current with positive temperature coefficients, and provides required current for various branches in the circuit; the reference voltage generating circuit is used for generating reference voltage which is irrelevant to the temperature; and the substrate biasing circuit is used for generating substrate biasing voltage, and performs temperature consumption on the reference voltage generating circuit. By the low-power-consumption and low-temperature-coefficient reference source circuit, the problems that the existing reference source circuits are based on band-gap references, high power voltage is required, and requirements on low power consumption cannot be met are solved, and temperature characteristics are high on the premise that the requirements on the low power consumption are met.

Description

Low-power consumption, low-temperature coefficient reference source circuit

Technical field

The present invention relates to field of analog integrated circuit, refer to especially low-power consumption, low-temperature coefficient reference source circuit.

Background technology

Reference voltage source circuit is an indispensable unit module in integrated circuit (IC) design, is widely used in various Analogous Integrated Electronic Circuits, hybrid digital-analog integrated circuit and digital integrated circuit.Along with popularizing of various portable mobile communications and counting yield, low supply voltage and low-power consumption have become one of main theme of Analog Circuit Design.

Traditional reference source circuit is all based on band-gap reference, utilize standard CMOS (Complementary Metal Oxide Semiconductor FET, complementary metal oxide semiconductor field effect transistor) vertical BJT pipe in technique, obtain one and be similar to the irrelevant voltage source of temperature, output voltage is generally 1.25V, this means and need a higher supply voltage, can not meet the demand of low-power consumption.Therefore, current technical scheme is not well positioned to meet performance requirement at aspects such as circuit structure, power consumption and temperatures coefficient, and the reference voltage source of particularly realizing a low-temperature coefficient under the requirement of low-power consumption also exists very large difficulty.

Summary of the invention

The object of this invention is to provide low-power consumption, low-temperature coefficient reference source circuit, realize and under the prerequisite that meets low-power consumption, there is good temperature characterisitic.

For achieving the above object, embodiments of the invention provide a kind of low-power consumption, low-temperature coefficient reference source circuit, comprising:

Start-up circuit, the current generating circuit being directly proportional to temperature, reference voltage generating circuit and substrate biasing circuit; Wherein,

The described current generating circuit being directly proportional to temperature is for generation of the electric current of positive temperature coefficient (PTC), for each branch road in circuit provides required electric current;

Described reference voltage generating circuit is for generation of temperature independent reference voltage;

Described substrate biasing circuit, for generation of substrate bias voltage, carries out temperature compensation to described reference voltage generating circuit.

Wherein, the described current generating circuit being directly proportional to temperature comprises:

The first nmos pass transistor MN1, the second nmos pass transistor MN2, the 3rd nmos pass transistor MN3, the 4th nmos pass transistor MN4, a PMOS transistor MP1, the 2nd PMOS transistor MP2 and the 3rd PMOS transistor MP3, wherein,

The source electrode of the source electrode of described the first nmos pass transistor MN1, the substrate of described the first nmos pass transistor MN1, the source electrode of described the 3rd nmos pass transistor MN3, the substrate of described the 3rd nmos pass transistor MN3, described the 4th nmos pass transistor MN4 and the substrate ground connection GND of described the 4th nmos pass transistor MN4;

The grid of described the first nmos pass transistor MN1 connects the grid of described the second nmos pass transistor MN2, the drain electrode short circuit of the grid of described the first nmos pass transistor MN1 and described the first nmos pass transistor MN1;

The source electrode of described the second nmos pass transistor MN2 connects the drain electrode of described the 4th nmos pass transistor MN4, the substrate short circuit of the source electrode of described the second nmos pass transistor MN2 and described the second nmos pass transistor MN2;

The grid of described the 3rd nmos pass transistor MN3 connects the grid of described the 4th nmos pass transistor MN4, the drain electrode short circuit of the grid of described the 3rd nmos pass transistor MN3 and described the 3rd nmos pass transistor MN3;

The source electrode of a described PMOS transistor MP1, the substrate of a described PMOS transistor MP1, the source electrode of described the 2nd PMOS transistor MP2, the substrate of described the 2nd PMOS transistor MP2, the source electrode of described the 3rd PMOS transistor MP3 and the substrate of described the 3rd PMOS transistor MP3 meet supply voltage VDD;

The drain electrode of a described PMOS transistor MP1 connects the drain electrode of described the 3rd nmos pass transistor MN3, and the grid of a described PMOS transistor MP1 connects the grid of described the 3rd PMOS transistor MP3;

The drain electrode of described the 2nd PMOS transistor MP2 connects the drain electrode of described the first nmos pass transistor MN1, and the grid of described the 2nd PMOS transistor MP2 connects the grid of described the 3rd PMOS transistor MP3;

The drain electrode of described the 3rd PMOS transistor MP3 connects the drain electrode of described the second nmos pass transistor MN2, the drain electrode short circuit of the grid of described the 3rd PMOS transistor MP3 and described the 3rd PMOS transistor MP3;

After electric current I 2 mirror images of described the 4th nmos pass transistor MN4, for each branch road in circuit provides required electric current.

Wherein, described start-up circuit comprises:

The 5th nmos pass transistor MS0, the 6th nmos pass transistor MS1, the 7th nmos pass transistor MS2, the 4th PMOS transistor MS3 and a PMOS transistor capacitance MS4, wherein,

The source electrode of the substrate of described the 5th nmos pass transistor MS0, the source electrode of described the 6th nmos pass transistor MS1, the substrate of described the 6th nmos pass transistor MS1, described the 7th nmos pass transistor MS2 and the substrate ground connection GND of described the 7th nmos pass transistor MS2;

The grid of described the 5th nmos pass transistor MS0 connects the drain electrode of described the 6th nmos pass transistor MS1 and the grid of a described PMOS transistor capacitance MS4, and the source electrode of described the 5th nmos pass transistor MS0 connects the drain electrode of described the 3rd nmos pass transistor MN3 as a control end of described start-up circuit;

The grid of described the 6th nmos pass transistor MS1 connects the grid of described the 7th nmos pass transistor MS2;

The drain electrode short circuit of the grid of described the 7th nmos pass transistor MS2 and described the 7th nmos pass transistor MS2;

The source electrode of described the 4th PMOS transistor MS3, the substrate of described the 4th PMOS transistor MS3, the source electrode of a described PMOS transistor capacitance MS4, the drain electrode of a described PMOS transistor capacitance MS4 and the substrate of a described PMOS transistor capacitance MS4 meet supply voltage VDD;

The drain electrode of described the 4th PMOS transistor MS3 connects the drain electrode of described the 7th nmos pass transistor MS2, and the grid of described the 4th PMOS transistor MS3 connects the drain electrode of described the 5th nmos pass transistor MS0 and the grid of a described PMOS transistor MP1 another output terminal as the start-up circuit of described reference source.

Wherein, described reference voltage generating circuit comprises:

The 8th nmos pass transistor MN5, the 9th nmos pass transistor MN6 and the 5th PMOS transistor MP4, wherein

The drain electrode short circuit of the grid of described the 8th nmos pass transistor MN5 and described the 8th nmos pass transistor MN5, the source electrode of described the 8th nmos pass transistor MN5 connects the drain electrode of described the 9th nmos pass transistor MN6, and as the output terminal of described reference source circuit;

The source electrode of described the 9th nmos pass transistor MN6, the substrate ground connection GND of described the 9th nmos pass transistor MN6, the grid of described the 9th nmos pass transistor MN6 connects the grid of described the 8th nmos pass transistor MN5;

The source electrode of described the 5th PMOS transistor MP4, the substrate of described the 5th PMOS transistor MP4 meet supply voltage VDD, the grid of described the 5th PMOS transistor MP4 connects the grid of described the 3rd PMOS transistor MP3, and the drain electrode of described the 5th PMOS transistor MP4 connects the drain electrode of described the 8th nmos pass transistor MN5.

Wherein, described substrate biasing circuit comprises:

The tenth nmos pass transistor MN7 and the 6th PMOS transistor MP5, wherein,

The source electrode of described the tenth nmos pass transistor MN7 and substrate ground connection GND;

The grid of described the tenth nmos pass transistor MN7 and drain electrode short circuit also connect the substrate of described the 8th nmos pass transistor MN5;

Source class and the substrate of described the 6th PMOS transistor MP5 meet supply voltage VDD;

The grid of described the 6th PMOS transistor MP5 connects the grid of described the 5th PMOS transistor MP4, and the drain electrode of described the 6th PMOS transistor MP5 connects the drain electrode of described the tenth nmos pass transistor MN7;

The grid of described the tenth nmos pass transistor MN7 provides bias voltage for the substrate of described the 8th nmos pass transistor MN5.

Wherein, described the 2nd PMOS transistor MP2 is identical with the breadth length ratio of described the 6th PMOS transistor MP5;

Described the 3rd PMOS transistor MP3 is identical with the breadth length ratio of described the 5th PMOS transistor MP4, and is four times of breadth length ratio of described the 2nd PMOS transistor MP2 and described the 6th PMOS transistor MP5;

The breadth length ratio of a described PMOS transistor MP1 is the octuple of the breadth length ratio of described the 2nd PMOS transistor MP2 and described the 6th PMOS transistor MP5.

The beneficial effect of technique scheme of the present invention is as follows:

The low-power consumption of the embodiment of the present invention, low-temperature coefficient reference source circuit have good temperature characterisitic under the prerequisite that meets low-power consumption.

Brief description of the drawings

Fig. 1 is embodiment of the present invention low-power consumption, low-temperature coefficient reference source circuit schematic diagram.

Embodiment

For making the technical problem to be solved in the present invention, technical scheme and advantage clearer, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.

The present invention is directed to existing reference source circuit is all based on band-gap reference, need a high supply voltage, can not meet the problem of the demand of low-power consumption, a kind of low-power consumption, low-temperature coefficient reference source circuit are provided, realize and under the prerequisite that meets low-power consumption, there is good temperature characterisitic.

As shown in Figure 1, the low-power consumption of the embodiment of the present invention, low-temperature coefficient reference source circuit, comprising:

Start-up circuit, the current generating circuit being directly proportional to temperature, reference voltage generating circuit and substrate biasing circuit; Wherein,

The described current generating circuit being directly proportional to temperature is for generation of the electric current of positive temperature coefficient (PTC), for each branch road in circuit provides required electric current;

Described reference voltage generating circuit is for generation of temperature independent reference voltage;

Described substrate biasing circuit, for generation of substrate bias voltage, carries out temperature compensation to described reference voltage generating circuit.

Further, the described current generating circuit being directly proportional to temperature comprises: the first nmos pass transistor MN1, the second nmos pass transistor MN2, the 3rd nmos pass transistor MN3, the 4th nmos pass transistor MN4, the one PMOS transistor MP1, the 2nd PMOS transistor MP2 and the 3rd PMOS transistor MP3, wherein, the source electrode of described the first nmos pass transistor MN1, the substrate of described the first nmos pass transistor MN1, the source electrode of described the 3rd nmos pass transistor MN3, the substrate of described the 3rd nmos pass transistor MN3, the substrate ground connection GND of the source electrode of described the 4th nmos pass transistor MN4 and described the 4th nmos pass transistor MN4, the grid of described the first nmos pass transistor MN1 connects the grid of described the second nmos pass transistor MN2, the drain electrode short circuit of the grid of described the first nmos pass transistor MN1 and described the first nmos pass transistor MN1, the source electrode of described the second nmos pass transistor MN2 connects the drain electrode of described the 4th nmos pass transistor MN4, the substrate short circuit of the source electrode of described the second nmos pass transistor MN2 and described the second nmos pass transistor MN2, the grid of described the 3rd nmos pass transistor MN3 connects the grid of described the 4th nmos pass transistor MN4, the drain electrode short circuit of the grid of described the 3rd nmos pass transistor MN3 and described the 3rd nmos pass transistor MN3, the source electrode of a described PMOS transistor MP1, the substrate of a described PMOS transistor MP1, the source electrode of described the 2nd PMOS transistor MP2, the substrate of described the 2nd PMOS transistor MP2, the source electrode of described the 3rd PMOS transistor MP3 and the substrate of described the 3rd PMOS transistor MP3 meet supply voltage VDD, the drain electrode of a described PMOS transistor MP1 connects the drain electrode of described the 3rd nmos pass transistor MN3, and the grid of a described PMOS transistor MP1 connects the grid of described the 3rd PMOS transistor MP3, the drain electrode of described the 2nd PMOS transistor MP2 connects the drain electrode of described the first nmos pass transistor MN1, and the grid of described the 2nd PMOS transistor MP2 connects the grid of described the 3rd PMOS transistor MP3, the drain electrode of described the 3rd PMOS transistor MP3 connects the drain electrode of described the second nmos pass transistor MN2, the drain electrode short circuit of the grid of described the 3rd PMOS transistor MP3 and described the 3rd PMOS transistor MP3, after electric current I 2 mirror images of described the 4th nmos pass transistor MN4, for each branch road in circuit provides required electric current.

Further, described start-up circuit comprises: the 5th nmos pass transistor MS0, the 6th nmos pass transistor MS1, the 7th nmos pass transistor MS2, the 4th PMOS transistor MS3 and a PMOS transistor capacitance MS4, wherein, the substrate ground connection GND of the source electrode of the substrate of the source electrode of the substrate of described the 5th nmos pass transistor MS0, described the 6th nmos pass transistor MS1, described the 6th nmos pass transistor MS1, described the 7th nmos pass transistor MS2 and described the 7th nmos pass transistor MS2; The grid of described the 5th nmos pass transistor MS0 connects the drain electrode of described the 6th nmos pass transistor MS1 and the grid of a described PMOS transistor capacitance MS4, and the source electrode of described the 5th nmos pass transistor MS0 connects the drain electrode of described the 3rd nmos pass transistor MN3 as a control end of described start-up circuit; The grid of described the 6th nmos pass transistor MS1 connects the grid of described the 7th nmos pass transistor MS2; The drain electrode short circuit of the grid of described the 7th nmos pass transistor MS2 and described the 7th nmos pass transistor MS2; The source electrode of described the 4th PMOS transistor MS3, the substrate of described the 4th PMOS transistor MS3, the source electrode of a described PMOS transistor capacitance MS4, the drain electrode of a described PMOS transistor capacitance MS4 and the substrate of a described PMOS transistor capacitance MS4 meet supply voltage VDD; The drain electrode of described the 4th PMOS transistor MS3 connects the drain electrode of described the 7th nmos pass transistor MS2, and the grid of described the 4th PMOS transistor MS3 connects the drain electrode of described the 5th nmos pass transistor MS0 and the grid of a described PMOS transistor MP1 another output terminal as the start-up circuit of described reference source.

Further, described reference voltage generating circuit comprises: the 8th nmos pass transistor MN5, the 9th nmos pass transistor MN6 and the 5th PMOS transistor MP4, wherein, the drain electrode short circuit of the grid of described the 8th nmos pass transistor MN5 and described the 8th nmos pass transistor MN5, the source electrode of described the 8th nmos pass transistor MN5 connects the drain electrode of described the 9th nmos pass transistor MN6, and as the output terminal of described reference source circuit; The source electrode of described the 9th nmos pass transistor MN6, the substrate ground connection GND of described the 9th nmos pass transistor MN6, the grid of described the 9th nmos pass transistor MN6 connects the grid of described the 8th nmos pass transistor MN5; The source electrode of described the 5th PMOS transistor MP4, the substrate of described the 5th PMOS transistor MP4 meet supply voltage VDD, the grid of described the 5th PMOS transistor MP4 connects the grid of described the 3rd PMOS transistor MP3, and the drain electrode of described the 5th PMOS transistor MP4 connects the drain electrode of described the 8th nmos pass transistor MN5.

Further, described substrate biasing circuit comprises: the tenth nmos pass transistor MN7 and the 6th PMOS transistor MP5, wherein, the source electrode of described the tenth nmos pass transistor MN7 and substrate ground connection GND; The grid of described the tenth nmos pass transistor MN7 and drain electrode short circuit also connect the substrate of described the 8th nmos pass transistor MN5; Source class and the substrate of described the 6th PMOS transistor MP5 meet supply voltage VDD; The grid of described the 6th PMOS transistor MP5 connects the grid of described the 5th PMOS transistor MP4, and the drain electrode of described the 6th PMOS transistor MP5 connects the drain electrode of described the tenth nmos pass transistor MN7; The grid of described the tenth nmos pass transistor MN7 provides bias voltage for the substrate of described the 8th nmos pass transistor MN5.

Further, described the 2nd PMOS transistor MP2 is identical with the breadth length ratio of described the 6th PMOS transistor MP5; Described the 3rd PMOS transistor MP3 is identical with the breadth length ratio of described the 5th PMOS transistor MP4, and is four times of breadth length ratio of described the 2nd PMOS transistor MP2 and described the 6th PMOS transistor MP5; The breadth length ratio of a described PMOS transistor MP1 is the octuple of the breadth length ratio of described the 2nd PMOS transistor MP2 and described the 6th PMOS transistor MP5.

In the above-described embodiments, as shown in Figure 1, the 3rd nmos pass transistor MN3 is operated in saturation region, the 4th nmos pass transistor MN4 is operated in dark linear zone, all the other transistors are all operated in sub-threshold region, and the reference source of the embodiment of the present invention realizes the voltage Δ V of a positive temperature coefficient (PTC) on the one hand by current generating circuit _gS', wherein Δ V _gS' gate source voltage poor of the 9th nmos pass transistor MN6 and the 8th nmos pass transistor MN5 while being the substrate ground connection as the 8th nmos pass transistor MN5, produces the voltage V of a negative temperature coefficient on the other hand by substrate biasing circuit _{gS, N7}, wherein V _{gS, N7}be the gate source voltage of the tenth nmos pass transistor MN7, mutually superpose to realize the low-power consumption reference source circuit of a low-temperature coefficient by the voltage of Positive and Negative Coefficient Temperature.

In the time that nmos pass transistor is operated in saturation region, the drain-source current of nmos pass transistor is:

$I_D=\frac{1}{2}{\mathrm{\μ}}_n{C}_{\mathrm{ox}}K{(V_{\mathrm{CS}}-V_{\mathrm{TH}})}^2$ Formula (1)

Wherein, I _dinjection Current, μ _nthe mobility of channel carrier, C _oxbe unit area gate oxide electric capacity, K is transistorized breadth length ratio, V _gSgate source voltage, V _tHit is transistorized threshold voltage.Can find out from formula (1), for a given leakage current, transistorized gate source voltage can be expressed as:

$V_{\mathrm{GS}}=V_{\mathrm{TH}}+\sqrt{\frac{{2I}_D}{{\mathrm{\μ}}_n{C}_{\mathrm{ox}}K}}$ Formula (2)

In the time that nmos pass transistor is operated in dark linear zone, the drain-source current of nmos pass transistor is:

I _d=μ _nc _oxk (V _gS-V _tH) V _dSformula (3)

Wherein, V _dSit is transistorized drain-source voltage.Can find out drain current I from formula (3) _dv _dSlinear function, this linear function can be expressed as with a linear resistance:

$R_{\mathrm{on}}=\frac{1}{{\mathrm{\μ}}_n{C}_{\mathrm{ox}}K(V_{\mathrm{GS}}-V_{\mathrm{TH}})}$ Formula (4)

Wherein, R _onfor transistorized conducting resistance.

In the time that nmos pass transistor is operated in sub-threshold region, the drain-source current of nmos pass transistor is:

$I_D=(n-1){\mathrm{\μ}}_n{C}_{\mathrm{ox}}{{\mathrm{KV}}_T}^2\exp \left(\frac{V_{\mathrm{GS}}-V_{\mathrm{TH}}}{n{T}_T}\right)$ Formula (5)

Wherein, n is slope factor, V _tbe thermal voltage, size equals kT/q.Can find out from formula (5), for a given leakage current, transistorized gate source voltage can be expressed as:

$V_{\mathrm{GS}}=V_{\mathrm{TH}}+n{V}_T\ln \left(\frac{I_D}{(n-1){\mathrm{\μ}}_n{C}_{\mathrm{ox}}{{\mathrm{KV}}_T}^2}\right)$ Formula (6)

In formula (2) and formula (6), transistorized threshold voltage can be expressed as:

$V_{\mathrm{TH}}=V_{\mathrm{TH}0}+\mathrm{\γ}(\sqrt{{2\mathrm{\φ}}_f+V_{\mathrm{sb}}}-\sqrt{{2\mathrm{\φ}}_f})$ Formula (7)

Wherein, V _tH0threshold voltage while being transistor source and substrate short circuit, γ is body-effect coefficient, φ _ffermi potential, V _sbthe poor of nmos pass transistor source electrode and underlayer voltage.

In the present embodiment, the first nmos pass transistor MN1, the second nmos pass transistor MN2, the 8th nmos pass transistor MN5 and the 9th nmos pass transistor MN6 are operated in sub-threshold region, the 3rd nmos pass transistor MN3 is operated in saturation region, the 4th nmos pass transistor MN4 is operated in dark linear zone, and the 4th nmos pass transistor MN4 drain terminal is to the voltage V on ground ₀can be expressed as:

V ₀=V _{gS, N1}-V _{gS, N2}formula (8)

By in formula (6) substitution formula (8), can obtain:

$V_0=n{V}_T\ln \frac{K_{N2}}{a{K}_{N1}}$ Formula (9) wherein, a=I ₂i ₁.

The 4th nmos pass transistor MN4 drain terminal is to the voltage V on ground ₀can also be expressed as:

V ₀=I ₂r _{on, N4}formula (10)

Formula (4) and formula (9) substitution formula (10) abbreviation are obtained:

$I_1=\frac{2\mathrm{bn}{\mathrm{\μ}}_n{C}_{\mathrm{ox}}{K_{N4}}^2}{a^2{K}_{N3}}\·{\left(\ln \frac{K_{N2}}{a{K}_{N1}}\right)}^2\·{V_T}^2$ Formula (11) wherein, b=I ₃i ₁.

Output reference voltage can be expressed as:

V _ref＝V _GS,N6-V _GS,N5

$=\mathrm{\γ}(\sqrt{{2\mathrm{\φ}}_f}-\sqrt{{2\mathrm{\φ}}_f+V_{\mathrm{ref}}-V_{\mathrm{GS},N7}})+{\mathrm{nV}}_T\ln \frac{K_{N5}}{K_{N6}}$ Formula (12)

By formula (6) substitution formula (12) abbreviation, while obtaining, output reference voltage is:

$V_{\mathrm{ref}}=\frac{\mathrm{\γ}(\mathrm{\γ}+2\sqrt{{2\mathrm{\φ}}_f})}{2}+n{V}_T\ln \frac{K_{N5}}{K_{N6}}$

$-\mathrm{\γ}\sqrt{\mathrm{\γ}(\frac{\mathrm{\γ}}{4}+\sqrt{{2\mathrm{\φ}}_f})+{2\mathrm{\φ}}_f+{\mathrm{nV}}_T\ln \frac{K_{N5}}{K_{N6}}-V_{\mathrm{TH},N7-{\mathrm{nV}}_T\ln }[\frac{{{2\mathrm{bcK}}_{N4}}^2}{a^2{K}_{N3}{K}_{N7}}\·\frac{n}{n-1}\·{\left(\ln \frac{K_{N2}}{{\mathrm{aK}}_{N1}}\right)}^2]}$

Wherein, V _tpositive temperature coefficient, and V _{tH, N7}it is negative temperature coefficient.

From formula (13), can find out that threshold voltage is positioned at radical sign, so the second-order temperature coefficient of threshold voltage be can not ignore, the threshold voltage of the tenth nmos pass transistor MN7 be carried out to second order and be similar to:

V _{tH, N7}=V _{tH, N7}(T ₀)+α (T-T ₀)+β (T-T ₀) ²formula (14)

Wherein V _{tH, N7}(T ₀) be T ₀threshold voltage at temperature, α, β is respectively single order and the second-order temperature coefficient of threshold voltage.

Formula (14) substitution formula (13) formula abbreviation are obtained:

$V_{\mathrm{ref}}=A+B(T-T_0)-\mathrm{\γ}\sqrt{C+D(T-T_0)-\mathrm{\α}(T-T_0)-\mathrm{\β}{(T-T_0)}^2}$ Formula (15)

Wherein $A=\frac{\mathrm{\γ}(\mathrm{\γ}+2\sqrt{2{\mathrm{\φ}}_f})}{2},B=n\·\frac{k}{q}\ln \frac{K_{N5}}{K_{N6}},C=\mathrm{\γ}\·(\frac{\mathrm{\γ}}{4}+\sqrt{{2\mathrm{\φ}}_f})+{2\mathrm{\φ}}_f-V_{\mathrm{TH},N7}\left(T_0\right),$

$D=n\·\frac{k}{q}\·\left\{\begin{array}{c}\ln \frac{K_{N5}}{K_{N6}}-\ln \left[\begin{array}{c}\frac{{{2\mathrm{bcK}}_{N4}}^2}{{a^{2}K}_{N3}{K}_{N7}}\·\end{array}\frac{n}{n-1}\·{\left(\ln \frac{K_{N2}}{{\mathrm{aK}}_{N1}}\right)}^2\right]\end{array}\right\}.$

Want to realize the reference voltage source of zero-temperature coefficient, must meet:

$\frac{\∂V_{\mathrm{ref}}}{\∂}=0$ Formula (16)

Formula (15) substitution formula (16) abbreviation is obtained to two zero points,

$T_1=\frac{4(D-\mathrm{\α})({\mathrm{\β\γ}}^2+B^2)+\sqrt{\mathrm{\Δ}}}{8({\mathrm{\β}}^2{\mathrm{\γ}}^2+{\mathrm{\β\γ}}^2)}+T_0,T_2=\frac{4(D-\mathrm{\α})({\mathrm{\β\γ}}^2+{\mathrm{\β}}^2)-\sqrt{\mathrm{\Δ}}}{8({\mathrm{\β}}^2{\mathrm{\γ}}^2+{\mathrm{\β\γ}}^2)}+T_0$ Formula (17)

Wherein, $\mathrm{\Δ}=16{(D-\mathrm{\α})}^2{({\mathrm{\β\γ}}^2+B^2)}^2-16({\mathrm{\β}}^2{\mathrm{\γ}}^2+{\mathrm{\β\γ}}^2)[{\mathrm{\γ}}^2{(D-\mathrm{\α})}^2-{4B}^{2}C]{.}^{}$ Can find out, in the time meeting Δ > 0, there are two different zero points in this reference source, has realized second order compensation, thereby obtained the output reference voltage V of a low-temperature coefficient _ref.

In the embodiment of the present invention, because the 6th PMOS transistor is used to provide substrate bias current, in order to reduce system power dissipation, the 6th PMOS transistor MP5 is set identical with the breadth length ratio of the 2nd PMOS transistor MP2; Because the 3rd nmos pass transistor MN3 is operated in saturation region, the 4th nmos pass transistor MN4 is operated in dark linear zone, consider system power dissipation and circuit area, it is the octuple of the breadth length ratio of the 2nd PMOS transistor MP2 that the one PMOS transistor MP1 is set, and the 3rd PMOS transistor MP3 is four times of breadth length ratio of the 2nd PMOS transistor MP2; In benchmark output circuit, the 8th nmos pass transistor MN5 and the 9th nmos pass transistor MN6 are operated in sub-threshold region, consider the size of system power dissipation and output reference voltage, the 5th PMOS transistor MP4 is set is four times of breadth length ratio of the 2nd PMOS transistor MP2.

Low-power consumption reference source circuit provided by the invention is owing to having realized second order compensation, so there is good temperature characterisitic, and in reference source circuit, the 3rd nmos pass transistor MN3 is operated in saturation region, the 4th nmos pass transistor MN4 is operated in dark linear zone, all the other transistors are all operated in sub-threshold region, so the required supply voltage of this reference source circuit is very low, has finally realized and under the prerequisite that meets low-power consumption, have had good temperature characterisitic.

The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, do not departing under the prerequisite of principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (6)

1. low-power consumption, a low-temperature coefficient reference source circuit, is characterized in that, comprising:

Start-up circuit, the current generating circuit being directly proportional to temperature, reference voltage generating circuit and substrate biasing circuit; Wherein,

The described current generating circuit being directly proportional to temperature is for generation of the electric current of positive temperature coefficient (PTC), for each branch road in circuit provides required electric current;

Described reference voltage generating circuit is for generation of temperature independent reference voltage;

Described substrate biasing circuit, for generation of substrate bias voltage, carries out temperature compensation to described reference voltage generating circuit.

2. low-power consumption according to claim 1, low-temperature coefficient reference source circuit, is characterized in that, the described current generating circuit being directly proportional to temperature comprises:

The first nmos pass transistor (MN1), the second nmos pass transistor (MN2), the 3rd nmos pass transistor (MN3), the 4th nmos pass transistor (MN4), a PMOS transistor (MP1), the 2nd PMOS transistor (MP2) and the 3rd PMOS transistor (MP3), wherein

The source electrode of the source electrode of described the first nmos pass transistor (MN1), the substrate of described the first nmos pass transistor (MN1), the source electrode of described the 3rd nmos pass transistor (MN3), the substrate of described the 3rd nmos pass transistor (MN3), described the 4th nmos pass transistor (MN4) and the substrate ground connection (GND) of described the 4th nmos pass transistor (MN4);

The grid of described the first nmos pass transistor (MN1) connects the grid of described the second nmos pass transistor (MN2), the drain electrode short circuit of the grid of described the first nmos pass transistor (MN1) and described the first nmos pass transistor (MN1);

The source electrode of described the second nmos pass transistor (MN2) connects the drain electrode of described the 4th nmos pass transistor (MN4), the substrate short circuit of the source electrode of described the second nmos pass transistor (MN2) and described the second nmos pass transistor (MN2);

The grid of described the 3rd nmos pass transistor (MN3) connects the grid of described the 4th nmos pass transistor (MN4), the drain electrode short circuit of the grid of described the 3rd nmos pass transistor (MN3) and described the 3rd nmos pass transistor (MN3);

The source electrode of a described PMOS transistor (MP1), the substrate of a described PMOS transistor (MP1), the source electrode of described the 2nd PMOS transistor (MP2), the substrate of described the 2nd PMOS transistor (MP2), the source electrode of described the 3rd PMOS transistor (MP3) and the substrate of described the 3rd PMOS transistor (MP3) connect supply voltage (VDD);

The drain electrode of a described PMOS transistor (MP1) connects the drain electrode of described the 3rd nmos pass transistor (MN3), and the grid of a described PMOS transistor (MP1) connects the grid of described the 3rd PMOS transistor (MP3);

The drain electrode of described the 2nd PMOS transistor (MP2) connects the drain electrode of described the first nmos pass transistor (MN1), and the grid of described the 2nd PMOS transistor (MP2) connects the grid of described the 3rd PMOS transistor (MP3);

The drain electrode of described the 3rd PMOS transistor (MP3) connects the drain electrode of described the second nmos pass transistor (MN2), the drain electrode short circuit of the grid of described the 3rd PMOS transistor (MP3) and described the 3rd PMOS transistor (MP3);

After electric current (I2) mirror image of described the 4th nmos pass transistor (MN4), for each branch road in circuit provides required electric current.

3. low-power consumption according to claim 2, low-temperature coefficient reference source circuit, is characterized in that, described start-up circuit comprises:

The 5th nmos pass transistor (MS0), the 6th nmos pass transistor (MS1), the 7th nmos pass transistor (MS2), the 4th PMOS transistor (MS3) and a PMOS transistor capacitance (MS4), wherein,

The source electrode of the substrate of described the 5th nmos pass transistor (MS0), the source electrode of described the 6th nmos pass transistor (MS1), the substrate of described the 6th nmos pass transistor (MS1), described the 7th nmos pass transistor (MS2) and the substrate ground connection (GND) of described the 7th nmos pass transistor (MS2);

The grid of described the 5th nmos pass transistor (MS0) connects the drain electrode of described the 6th nmos pass transistor (MS1) and the grid of a described PMOS transistor capacitance (MS4), and the source electrode of described the 5th nmos pass transistor (MS0) connects the drain electrode of described the 3rd nmos pass transistor (MN3) as a control end of the start-up circuit of described reference source;

The grid of described the 6th nmos pass transistor (MS1) connects the grid of described the 7th nmos pass transistor (MS2);

The drain electrode short circuit of the grid of described the 7th nmos pass transistor (MS2) and described the 7th nmos pass transistor (MS2);

The source electrode of described the 4th PMOS transistor (MS3), the substrate of described the 4th PMOS transistor (MS3), the source electrode of a described PMOS transistor capacitance (MS4), the drain electrode of a described PMOS transistor capacitance (MS4) and the substrate of a described PMOS transistor capacitance (MS4) connect supply voltage (VDD);

The drain electrode of described the 4th PMOS transistor (MS3) connects the drain electrode of described the 7th nmos pass transistor (MS2), and the grid of described the 4th PMOS transistor (MS3) connects the drain electrode of described the 5th nmos pass transistor (MS0) and the grid of a described PMOS transistor (MP1) another output terminal as the start-up circuit of described reference source.

4. low-power consumption according to claim 2, low-temperature coefficient reference source circuit, is characterized in that, described reference voltage generating circuit comprises:

The 8th nmos pass transistor (MN5), the 9th nmos pass transistor (MN6) and the 5th PMOS transistor (MP4), wherein,

The drain electrode short circuit of the grid of described the 8th nmos pass transistor (MN5) and described the 8th nmos pass transistor (MN5), the source electrode of described the 8th nmos pass transistor (MN5) connects the drain electrode of described the 9th nmos pass transistor (MN6), and as the output terminal of described reference source circuit;

The source electrode of described the 9th nmos pass transistor (MN6), the substrate ground connection (GND) of described the 9th nmos pass transistor (MN6), the grid of described the 9th nmos pass transistor (MN6) connects the grid of described the 8th nmos pass transistor (MN5);

The source electrode of described the 5th PMOS transistor (MP4), the substrate of described the 5th PMOS transistor (MP4) connect supply voltage (VDD), the grid of described the 5th PMOS transistor (MP4) connects the grid of described the 3rd PMOS transistor (MP3), and the drain electrode of described the 5th PMOS transistor (MP4) connects the drain electrode of described the 8th nmos pass transistor (MN5).

5. low-power consumption according to claim 4, low-temperature coefficient reference source circuit, is characterized in that, described substrate biasing circuit comprises:

The tenth nmos pass transistor (MN7) and the 6th PMOS transistor (MP5), wherein,

The source electrode of described the tenth nmos pass transistor (MN7) and substrate ground connection (GND);

The grid of described the tenth nmos pass transistor (MN7) and drain electrode short circuit also connect the substrate of described the 8th nmos pass transistor (MN5);

The source class of described the 6th PMOS transistor (MP5) and substrate connect supply voltage (VDD);

The grid of described the 6th PMOS transistor (MP5) connects the grid of described the 5th PMOS transistor (MP4), and the drain electrode of described the 6th PMOS transistor (MP5) connects the drain electrode of described the tenth nmos pass transistor (MN7);

The grid of described the tenth nmos pass transistor (MN7) is that the substrate of described the 8th nmos pass transistor (MN5) provides bias voltage.

6. low-power consumption according to claim 5, low-temperature coefficient reference source circuit, is characterized in that, described the 2nd PMOS transistor (MP2) is identical with the breadth length ratio of described the 6th PMOS transistor (MP5);

Described the 3rd PMOS transistor (MP3) is identical with the breadth length ratio of described the 5th PMOS transistor (MP4), and is four times of breadth length ratio of described the 2nd PMOS transistor (MP2) and described the 6th PMOS transistor (MP5);

The breadth length ratio of a described PMOS transistor (MP1) is the octuple of the breadth length ratio of described the 2nd PMOS transistor (MP2) and described the 6th PMOS transistor (MP5).