CN104111687B - Low pressure, low-temperature coefficient reference source circuit - Google Patents

Abstract

Embodiments of the invention disclose a kind of low pressure, low-temperature coefficient reference source circuit, belong to field of analog integrated circuit.This circuit comprises: temperature independent current generating circuit, Substrate bias circuit and reference voltage generating circuit, wherein: described temperature independent current generating circuit for generation of the electric current of low-temperature coefficient, for the output stage of reference source provides electric current; Described Substrate bias circuit, for generation of Substrate bias voltage, carries out temperature compensation to temperature independent current generating circuit; Described reference voltage generating circuit is for generation of temperature independent reference voltage.Reference source of the present invention has good temperature characterisitic under the prerequisite meeting low output voltage.

Description

Low pressure, low-temperature coefficient reference source circuit

Technical field

The present invention relates to field of analog integrated circuit, refer to a kind of low voltage reference source circuit with low-temperature coefficient especially.

Background technology

Reference voltage source, as the Key Circuit unit of Analogous Integrated Electronic Circuits, is widely used in precision comparator, A/D and the integrated circuit such as D/A converter, dynamic RAM.

In portable set widely used today, low supply voltage and low-power consumption be one of main subject matter becoming Analog Circuit Design.Wherein voltage-reference is the key modules in Analog Circuit Design, General Requirements low supply voltage susceptibility, low excursion with temperature characteristic.Traditional reference source circuit is all based on band-gap reference, utilize the vertical PNP pipe in standard CMOS process, but output voltage is generally about 1.2V.Utilize the △ V of nmos pass transistor (N-channel Metal Oxide Semiconductor FET, n channel metal oxide semiconductor field effect transistor) _gSnegative temperature coefficient be multiplied by weight, with the △ V of PMOS transistor (P-channel Metal Oxide Semiconductor FET, P-channel metal-oxide-semiconductor field effect transistor) _gSnegative temperature coefficient subtract each other, obtaining temperature independent reference voltage is a kind of method for designing, but has very large non-linear due to the threshold voltage of metal-oxide-semiconductor, therefore the temperature coefficient that this benchmark exports generally is greater than 30ppm/ DEG C, only belongs to single order technique for temperature compensation.Current technical scheme is not well positioned to meet performance requirement in circuit structure, power consumption and temperature coefficient etc., also there is very large difficulty in the reference voltage source particularly realizing a low-temperature coefficient under the requirement of low supply voltage, so be necessary to take a kind of new circuit structure to realize the reference voltage source of low-temperature coefficient.

Summary of the invention

The technical problem to be solved in the present invention is low pressure, low-temperature coefficient reference source circuit, can have good temperature characterisitic under the prerequisite meeting low output voltage.

For solving the problems of the technologies described above, embodiments of the invention provide a kind of low pressure, low-temperature coefficient reference source circuit, comprising:

Temperature independent current generating circuit, Substrate bias circuit and reference voltage generating circuit, wherein:

Described temperature independent current generating circuit for generation of the electric current of low-temperature coefficient, for the output stage of reference source provides electric current;

Described Substrate bias circuit, for generation of Substrate bias voltage, carries out temperature compensation to temperature independent current generating circuit;

Described reference voltage generating circuit is for generation of temperature independent reference voltage.

Wherein, described temperature independent current generating circuit comprises:

First nmos pass transistor MN1, the second nmos pass transistor MN2, the first PMOS transistor MP1, the second PMOS transistor MP2 and the first resistance R1, wherein,

The source ground GND of the source electrode of described first nmos pass transistor MN1, the substrate of described first nmos pass transistor MN1 and described second nmos pass transistor MN2;

The substrate of described second nmos pass transistor MN2 connects described Substrate bias circuit;

The grid of described first nmos pass transistor MN1 and the drain electrode of described first PMOS transistor MP1 connect the positive pole of described first resistance R1;

The grid of described second nmos pass transistor MN2 and the drain electrode of described first nmos pass transistor MN1 connect the negative pole of described first resistance R1;

The drain electrode of described second nmos pass transistor MN2 connects the drain electrode of described second PMOS transistor MP2;

The source electrode of described first PMOS transistor MP1 and the source electrode of described second PMOS transistor MP2 meet supply voltage VDD;

The substrate of described first PMOS transistor MP1 and the substrate of described second PMOS transistor MP2 meet supply voltage VDD;

The grid of described first PMOS transistor MP1 connects the grid of described second PMOS transistor MP2, the grid of described second PMOS transistor MP2 and the drain electrode short circuit of described second PMOS transistor MP2;

The electric current I 1 of described first resistance R1 is as the electric current of described reference voltage generating circuit.

Wherein, described Substrate bias circuit comprises:

3rd nmos pass transistor MN3 and the 3rd PMOS transistor MP3, wherein,

The source electrode of described 3rd nmos pass transistor MN3 and Substrate ground GND;

The grid of described 3rd nmos pass transistor MN3 and drain electrode short circuit also connect the substrate of described second nmos pass transistor MN2 and the drain electrode of described 3rd PMOS transistor MP3;

Source electrode and the substrate of described 3rd PMOS transistor MP3 meet supply voltage VDD;

The grid of described 3rd PMOS transistor MP3 connects the described first PMOS transistor (grid of MP1 and described second PMOS transistor MP2;

The grid of described 3rd nmos pass transistor MN3 provides bias voltage for the substrate of described second nmos pass transistor MN2.

Wherein, described temperature independent current generating circuit also comprises: the start-up circuit of reference source, and the start-up circuit of described reference source comprises:

4th PMOS transistor MS1, the 4th nmos pass transistor MS2 and the 5th nmos pass transistor MS3, wherein,

Source electrode and the substrate of described 4th PMOS transistor MS1 meet supply voltage VDD, the drain electrode of described 4th PMOS transistor MS1 connects the drain electrode of described 4th nmos pass transistor MS2 and the grid of described 5th nmos pass transistor MS3, the source electrode of described 4th nmos pass transistor MS2 and Substrate ground GND, the grid of described 4th nmos pass transistor MS2 is connected a control end of the start-up circuit as described reference source with the grid of described 4th PMOS transistor MS1;

The source electrode of described 5th nmos pass transistor MS3 and Substrate ground GND, the drain electrode of described 5th nmos pass transistor MS3 is as another output terminal of the start-up circuit of described reference source.

Wherein, described reference voltage generating circuit comprises: the 5th PMOS transistor MP4 and the second resistance R2, wherein

Source electrode and the substrate of described 5th PMOS transistor MP4 meet supply voltage VDD, the grid of described 5th PMOS transistor MP4 connects the grid of described first PMOS transistor MP1, described second PMOS transistor MP2 and described 3rd PMOS transistor MP3, the minus earth of described second resistance R2, the positive pole of described second resistance R2 connects the drain electrode of described 5th PMOS transistor MP4, and as the output of described reference voltage generating circuit.

Wherein, described first PMOS transistor MP1, described second PMOS transistor MP2 are identical with the breadth length ratio of described 5th PMOS transistor MP4.

The above embodiment of the present invention has following beneficial effect:

In such scheme, the low voltage reference source circuit of low-temperature coefficient has good temperature characterisitic under the prerequisite meeting low output voltage.

Accompanying drawing explanation

Fig. 1 is that the embodiment of the present invention has low pressure, low-temperature coefficient reference source circuit schematic diagram.

Embodiment

For making the technical problem to be solved in the present invention, technical scheme and advantage clearly, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.

Embodiments provide a kind of low voltage reference source circuit with low-temperature coefficient, good temperature characterisitic can be had under the prerequisite meeting low output voltage.

As shown in Figure 1, the low pressure of embodiments of the invention, low-temperature coefficient reference source circuit comprise:

Temperature independent current generating circuit, Substrate bias circuit and reference voltage generating circuit, wherein:

Described temperature independent current generating circuit for generation of the electric current of low-temperature coefficient, for the output stage of reference source provides electric current;

Described Substrate bias circuit, for generation of Substrate bias voltage, carries out temperature compensation to temperature independent current generating circuit;

Described reference voltage generating circuit is for generation of temperature independent reference voltage.

Further, described temperature independent current generating circuit comprises: the first nmos pass transistor MN1, the second nmos pass transistor MN2, the first PMOS transistor MP1, the second PMOS transistor MP2 and the first resistance R1, wherein,

The source ground GND of the source electrode of described first nmos pass transistor MN1, the substrate of described first nmos pass transistor MN1 and described second nmos pass transistor MN2; The substrate of described second nmos pass transistor MN2 connects described Substrate bias circuit; The grid of described first nmos pass transistor MN1 and the drain electrode of described first PMOS transistor MP1 connect the positive pole of described first resistance R1; The grid of described second nmos pass transistor MN2 and the drain electrode of described first nmos pass transistor MN1 connect the negative pole of described first resistance R1; The drain electrode of described second nmos pass transistor MN2 connects the drain electrode of described second PMOS transistor MP2; The source electrode of described first PMOS transistor MP1 and the source electrode of described second PMOS transistor MP2 meet supply voltage VDD; The substrate of described first PMOS transistor MP1 and the substrate of described second PMOS transistor MP2 meet supply voltage VDD; The grid of described first PMOS transistor MP1 connects the grid of described second PMOS transistor MP2, the grid of described second PMOS transistor MP2 and the drain electrode short circuit of described second PMOS transistor MP2; The electric current I 1 of described first resistance R1 is as the electric current of described reference voltage generating circuit.

Further, described Substrate bias circuit comprises: the 3rd nmos pass transistor MN3 and the 3rd PMOS transistor MP3, wherein, and the source electrode of described 3rd nmos pass transistor MN3 and Substrate ground GND; The grid of described 3rd nmos pass transistor MN3 and drain electrode short circuit also connect the substrate of described second nmos pass transistor MN2 and the drain electrode of described 3rd PMOS transistor MP3; Source electrode and the substrate of described 3rd PMOS transistor MP3 meet supply voltage VDD; The grid of described 3rd PMOS transistor MP3 connects the grid of described first PMOS transistor MP1 and described second PMOS transistor MP2; The grid of described 3rd nmos pass transistor MN3 provides bias voltage for the substrate of described second nmos pass transistor MN2.

Further, described temperature independent current generating circuit also comprises: the start-up circuit of reference source, the start-up circuit of described reference source comprises: the 4th PMOS transistor MS1, 4th nmos pass transistor MS2 and the 5th nmos pass transistor MS3, wherein, source electrode and the substrate of described 4th PMOS transistor MS1 meet supply voltage VDD, the drain electrode of described 4th PMOS transistor MS1 connects the drain electrode of described 4th nmos pass transistor MS2 and the grid of described 5th nmos pass transistor MS3, the source electrode of described 4th nmos pass transistor MS2 and Substrate ground GND, the grid of described 4th nmos pass transistor MS2 is connected a control end of the start-up circuit as described reference source with the grid of described 4th PMOS transistor MS1, the source electrode of described 5th nmos pass transistor MS3 and Substrate ground GND, the drain electrode of described 5th nmos pass transistor MS3 is as another output terminal of the start-up circuit of described reference source.

Further, described reference voltage generating circuit comprises: the 5th PMOS transistor MP4 and the second resistance R2, wherein, source electrode and the substrate of described 5th PMOS transistor MP4 meet supply voltage VDD, the grid of described 5th PMOS transistor MP4 connects the grid of described first PMOS transistor MP1, described second PMOS transistor MP2 and described 3rd PMOS transistor MP3, the minus earth of described second resistance R2, the positive pole of described second resistance R2 connects the drain electrode of described 5th PMOS transistor MP4, and as the output of described reference voltage generating circuit.

Further, described first PMOS transistor MP1, described second PMOS transistor MP2 are identical with the breadth length ratio of described 5th PMOS transistor MP4.

In the above-described embodiments, as shown in Figure 1, temperature independent current generating circuit utilizes Substrate bias technology, makes two △ V being operated in the metal-oxide-semiconductor of saturation region and sub-threshold region respectively _gStemperature coefficient is 0, realizes the low voltage reference source circuit of a low-temperature coefficient.

When nmos pass transistor is operated in saturation region, the drain-source current of nmos pass transistor is:

$I_D=\frac{1}{2}{\mathrm{\μ}}_n{C}_{\mathrm{ox}}(W/L){(V_{\mathrm{GS}}-V_{\mathrm{TH}})}^2$ Formula (1)

Wherein, I _dinjection Current, μ _nthe mobility of channel carrier, C _oxbe unit area gate oxide capacitance, (W/L) is the breadth length ratio of transistor, V _gSgate source voltage, V _tHit is the threshold voltage of transistor.As can be seen from formula (1), for a given leakage current, the gate source voltage of transistor can be expressed as:

$V_{\mathrm{GS}}=V_{\mathrm{TH}}+\sqrt{\frac{2I_D}{{\mathrm{\μ}}_n{C}_{\mathrm{ox}}(W/L)}}$ Formula (2)

When nmos pass transistor is operated in sub-threshold region, the drain-source current of nmos pass transistor is:

$I_D=(n-1){\mathrm{\μ}}_n{C}_{\mathrm{ox}}(W/L){V_T}^2\exp \left(\frac{V_{\mathrm{GS}}-V_{\mathrm{TH}}}{{\mathrm{nV}}_T}\right)$ Formula (3)

Wherein, n is slope factor, V _tbe thermal voltage, size equals kT/q.As can be seen from formula (3), for a given leakage current, the gate source voltage of transistor can be expressed as:

$V_{\mathrm{GS}}=V_{\mathrm{TH}}+n{V}_T\ln \left(\frac{I_D}{(n-1){\mathrm{\μ}}_n{C}_{\mathrm{ox}}(W/L){V_T}^2}\right)$ Formula (4)

In formula (2) and formula (4), the threshold voltage of transistor can be expressed as:

$V_{\mathrm{TH}}=V_{\mathrm{TH}0}+\mathrm{\γ}(\sqrt{2{\mathrm{\φ}}_f+V_{\mathrm{sb}}}-\sqrt{2{\mathrm{\φ}}_f})$ Formula (5)

Wherein, V _tH0be transistor source and substrate short circuit time threshold voltage, γ is body-effect coefficient, φ _ffermi potential, V _sbit is the difference of nmos pass transistor source electrode and underlayer voltage.

In the present embodiment, the first nmos pass transistor MN1 is operated in saturation region, and the second nmos pass transistor MN2 and the 3rd nmos pass transistor MN3 is operated in sub-threshold region, and the voltage at resistance R1 two ends can be expressed as:

V _r=V _{gS, N1}-V _{gS, N2}formula (6)

Formula (2), formula (4) and formula (5) to be substituted in formula (6) and to arrange, can obtain

$V_R=\mathrm{\γ}\sqrt{2{\mathrm{\φ}}_f}-\mathrm{\γ}\sqrt{{2\mathrm{\φ}}_f-n{V}_T\ln \left(\frac{I_2}{{\mathrm{\μ}}_n{C}_{\mathrm{ox}}{(W/L)}_{N3}(n-1){V_T}^2}\right)-V_{\mathrm{TH},N3}}$

$+\sqrt{\frac{{2I}_1}{\mathrm{\μ}{C}_{\mathrm{ox}}{(W/L)}_{N1}}}-n{V}_T\ln \left(\frac{I_1}{{\mathrm{\μ}}_n{C}_{\mathrm{ox}}{(W/L)}_{N2}(n-1){V_T}^2}\right)$ Formula (7) wherein, $I_1=\frac{V_R}{R1},$ $I_2=\frac{{(W/L)}_{P3}}{{(W/L)}_{P1}}{I}_1.$

Output reference voltage can be expressed as:

$V_{\mathrm{ref}}=V_R\frac{R2}{R1}$ Formula (8)

Formula (7) to be brought in formula (8) and to ask V _refto the differential of T,

$\frac{{\mathrm{dV}}_{\mathrm{ref}}}{\mathrm{dT}}=\frac{R2}{R1}\frac{{\mathrm{dV}}_R}{\mathrm{dT}}$ Formula (9)

Make it equal 0, can find out, by the breadth length ratio of adjustment transistor MN1, MN2, MN3 and MP3, just can obtain temperature independent output reference voltage V _ref.

By adjusting the size of R1 and R2, the different output voltage values of low-temperature coefficient just can be obtained.

In the embodiment of the present invention, the first PMOS transistor MP1, the second PMOS transistor MP2 are identical with the breadth length ratio of the 5th PMOS transistor MP4.

Low voltage reference source circuit provided by the invention has good temperature characterisitic, and the power consumption of this reference source circuit is very low.

The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (4)

1. low pressure, a low-temperature coefficient reference source circuit, is characterized in that, comprising:

Temperature independent current generating circuit, Substrate bias circuit and reference voltage generating circuit, wherein:

Described temperature independent current generating circuit for generation of the electric current of low-temperature coefficient, for the output stage of reference source provides electric current;

Described Substrate bias circuit, for generation of Substrate bias voltage, carries out temperature compensation to temperature independent current generating circuit;

Described reference voltage generating circuit is for generation of temperature independent reference voltage;

Described temperature independent current generating circuit comprises:

First nmos pass transistor (MN1), the second nmos pass transistor (MN2), the first PMOS transistor (MP1), the second PMOS transistor (MP2) and the first resistance (R1), wherein,

The source ground (GND) of the source electrode of described first nmos pass transistor (MN1), the substrate of described first nmos pass transistor (MN1) and described second nmos pass transistor (MN2);

The substrate of described second nmos pass transistor (MN2) connects described Substrate bias circuit;

The grid of described first nmos pass transistor (MN1) and the drain electrode of described first PMOS transistor (MP1) connect the positive pole of described first resistance (R1);

The grid of described second nmos pass transistor (MN2) and the drain electrode of described first nmos pass transistor (MN1) connect the negative pole of described first resistance (R1);

The drain electrode of described second nmos pass transistor (MN2) connects the drain electrode of described second PMOS transistor (MP2);

The source electrode of described first PMOS transistor (MP1) and the source electrode of described second PMOS transistor (MP2) connect supply voltage (VDD);

The substrate of described first PMOS transistor (MP1) and the substrate of described second PMOS transistor (MP2) connect supply voltage (VDD);

The grid of described first PMOS transistor (MP1) connects the grid of described second PMOS transistor (MP2), the described grid of the second PMOS transistor (MP2) and the drain electrode short circuit of described second PMOS transistor (MP2);

The electric current (I1) of described first resistance (R1) is as the electric current of described reference voltage generating circuit;

Described Substrate bias circuit comprises:

3rd nmos pass transistor (MN3) and the 3rd PMOS transistor (MP3), wherein,

The source electrode of described 3rd nmos pass transistor (MN3) and Substrate ground (GND);

The grid of described 3rd nmos pass transistor (MN3) and drain electrode short circuit also connect the substrate of described second nmos pass transistor (MN2) and the drain electrode of described 3rd PMOS transistor (MP3);

Source electrode and the substrate of described 3rd PMOS transistor (MP3) connect supply voltage (VDD);

The grid of described 3rd PMOS transistor (MP3) connects the grid of described first PMOS transistor (MP1) and described second PMOS transistor (MP2);

The grid of described 3rd nmos pass transistor (MN3) is that the substrate of described second nmos pass transistor (MN2) provides bias voltage.

2. low pressure according to claim 1, low-temperature coefficient reference source circuit, is characterized in that, described temperature independent current generating circuit also comprises: the start-up circuit of reference source, and the start-up circuit of described reference source comprises:

4th PMOS transistor (MS1), the 4th nmos pass transistor (MS2) and the 5th nmos pass transistor (MS3), wherein,

Source electrode and the substrate of described 4th PMOS transistor (MS1) connect supply voltage (VDD), the drain electrode of described 4th PMOS transistor (MS1) connects the drain electrode of described 4th nmos pass transistor (MS2) and the grid of described 5th nmos pass transistor (MS3), the source electrode of described 4th nmos pass transistor (MS2) and Substrate ground (GND), the grid of described 4th nmos pass transistor (MS2) is connected a control end of the start-up circuit as described reference source with the grid of described 4th PMOS transistor (MS1);

The source electrode of described 5th nmos pass transistor (MS3) and Substrate ground (GND), the drain electrode of described 5th nmos pass transistor (MS3) is as another output terminal of the start-up circuit of described reference source.

3. low pressure according to claim 1, low-temperature coefficient reference source circuit, is characterized in that, described reference voltage generating circuit comprises: the 5th PMOS transistor (MP4) and the second resistance (R2), wherein

Source electrode and the substrate of described 5th PMOS transistor (MP4) connect supply voltage (VDD), the grid of described 5th PMOS transistor (MP4) connects the grid of described first PMOS transistor (MP1), described second PMOS transistor (MP2) and described 3rd PMOS transistor (MP3), the minus earth of described second resistance (R2), the positive pole of described second resistance (R2) connects the drain electrode of described 5th PMOS transistor (MP4), and as the output of described reference voltage generating circuit.

4. low pressure according to claim 3, low-temperature coefficient reference source circuit, it is characterized in that, described first PMOS transistor (MP1), described second PMOS transistor (MP2) are identical with the breadth length ratio of described 5th PMOS transistor (MP4).