CN102662427A - Voltage source circuit - Google Patents

Abstract

An embodiment of the present invention provides a voltage source circuit, including a current source circuit and a reference voltage output stage, the reference voltage output stage includes: a first NMOS transistor, the source is grounded, and the gate is connected to the drain; the first PMOS transistor, The source is connected to the power supply, the gate is connected to the output terminal of the current source circuit, and the drain is connected to the drain of the first NMOS transistor; the current source circuit is composed of a MOS transistor and a resistor. The voltage source circuit in the embodiment of the present invention only uses MOS transistors and resistors, does not need bipolar transistors and other types of transistors, has a simple structure, occupies a small chip area, and has low manufacturing costs, and can be used in digital circuits compatible In the standard CMOS process, the compatibility of analog circuits and digital circuits is improved.

Description

A voltage source circuit

technical field

The invention relates to the technical field of integrated circuits, in particular to a voltage source circuit.

Background technique

The voltage source circuit is one of the very important basic circuits in the integrated circuit system. It provides the necessary bias voltage for the normal operation of other modules in the chip. Therefore, the performance of the voltage source circuit greatly affects the overall performance of the chip. With the development of microelectronics manufacturing process technology and the rapid increase of consumer markets such as personal portable devices and wireless receivers, the design challenges for voltage source circuits are also increasing.

However, most of the voltage source circuits widely used at present come from bipolar bandgap references. This type of voltage source circuit requires high-performance bipolar transistors, which occupy a large area and are expensive to manufacture. Some even require bipolar transistors in BiCMOS or bipolar transistors. It cannot be compatible with the standard CMOS process, and cannot meet the requirements of integrated circuit design under the deep submicron process.

Contents of the invention

In view of this, the present invention aims to provide a voltage source circuit compatible with the CMOS process, so as to solve the defect that the voltage source circuit in the prior art is not compatible with the CMOS process.

To this end, the technical solution of the present invention provides a voltage source circuit compatible with the CMOS process, including a current source circuit and a reference voltage output stage, the current source circuit is composed of a MOS tube and a resistor, the current source circuit is connected to a power supply and ground for providing an output current proportional to temperature;

The reference voltage output stage includes a first PMOS transistor and a first NMOS transistor,

The source of the first PMOS transistor is connected to the power supply, the gate is connected to the output terminal of the current source circuit, and the drain is connected to the drain of the first NMOS transistor, which is used to output the current source circuit the output current mirror;

The source of the first NMOS transistor is grounded, and the gate is connected to the drain for converting the mirrored output current into an output voltage.

Preferably, the current source circuit includes a second NMOS transistor, a third NMOS transistor, a second PMOS transistor, a third PMOS transistor and a compensation resistor, wherein,

The source of the second NMOS transistor is grounded, and the gate is connected to the drain;

The source of the third NMOS transistor is grounded through the compensation resistor, and the gate is connected to the gate of the second NMOS transistor;

The source of the second PMOS transistor is connected to the power supply, and the drain is connected to the drain of the second NMOS transistor;

The source of the third PMOS transistor is connected to the power supply, the gate is connected to the gate of the second PMOS transistor, and constitutes the output end of the current source circuit, and the drain is connected to the drain of the third NMOS transistor. The pole is connected, and the gate is connected to the drain.

Preferably, the voltage source circuit also includes a start-up circuit, and the start-up circuit includes:

For a fourth PMOS transistor, the source is connected to the power supply, and the gate is connected to the drain of the second PMOS transistor;

The source of the fourth NMOS transistor is grounded, the gate is connected to the gate of the fourth PMOS transistor, and the drain is connected to the drain of the fourth PMOS transistor;

The source of the fifth NMOS transistor is grounded, the gate is connected to the drain of the fourth PMOS transistor, and the drain is connected to the gate of the second PMOS transistor.

Preferably, the channel width-to-length ratio of the second PMOS transistor is different from that of the third PMOS transistor.

Preferably, the second NMOS transistor and the third NMOS transistor work in a sub-threshold region.

Preferably, the second PMOS transistor and the third PMOS transistor work in a sub-threshold region.

The voltage source circuit in the embodiment of the present invention only uses MOS transistors and resistors, does not need bipolar transistors and other types of transistors, has a simple structure, occupies a small chip area, and has low manufacturing costs, and can be used in digital circuits compatible In the standard CMOS process, the compatibility of analog circuits and digital circuits is improved.

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are For some embodiments of the present invention, those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 is the circuit structural diagram of the voltage source circuit of embodiment one of the present invention;

Fig. 2 is the circuit structural diagram of the voltage source circuit of embodiment 2 of the present invention;

3 is a schematic diagram of a reference voltage variation curve with temperature of a voltage source circuit according to Embodiment 2 of the present invention;

FIG. 4 is a circuit structure diagram of a voltage source circuit according to Embodiment 3 of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

In the prior art, the traditional voltage source circuit is composed of MOS transistors, operational amplifiers and triodes. The circuit structure is complex, the chip area is relatively large, and the manufacturing cost is high; moreover, the traditional voltage source circuit cannot be compatible with the CMOS standard process. , in the process of continuous development of deep submicron technology, it is necessary to improve the compatibility of analog circuits and digital circuits. The embodiment of the present invention aims to provide a voltage source circuit compatible with the CMOS standard process, so as to improve the compatibility of analog circuits and digital circuits, and meet the requirements of deep submicron process technology.

Embodiment one

Embodiment 1 of the present invention provides a voltage source circuit, as shown in FIG. 1 , which is a circuit structure diagram of the voltage source circuit in Embodiment 1 of the present invention. The voltage source circuit includes a current source circuit 101 and a reference voltage output stage 102, wherein the current source circuit 101 is composed of a MOS tube and a resistor, and the current source circuit 101 is connected to the power supply Vdd and grounded, and the current source circuit 101 is used to provide temperature-dependent proportional to the output current;

The reference voltage output stage 102 includes:

The source of the first PMOS transistor M2 is connected to the power supply Vdd, the gate is connected to the output terminal of the current source circuit, and the drain is connected to the drain of the first NMOS transistor M1 for mirroring the output current output by the current source circuit 101 ;

The source of the first NMOS transistor M1 is grounded, and the gate is connected to the drain, and is used for converting the mirrored output current of the first PMOS transistor M2 into an output voltage.

It can be seen from FIG. 1 that the first NMOS transistor M1 and the first PMOS transistor M2 are connected in the form of a diode, and the reference voltage V _ref can be output from the node 103 .

It should be noted that the current source circuit in Embodiment 1 of the present invention can be any current source circuit in the prior art that is only composed of MOS tubes and resistors and whose output current is proportional to temperature; the current source circuit 101 can include connections A MOS transistor in the form of a cascode current mirror, the cascode MOS transistor acts as a current mirror to ensure that the currents of each branch of the current source circuit are equal or proportional. Wherein, the gate of the first PMOS transistor M2 may be connected to the common gate of the current mirror.

If an op amp is used in the current source circuit, the structure of the voltage source circuit will be complicated, and at the same time it will consume a large power consumption, which cannot meet the requirements of a simple integrated circuit structure; In the compatible standard CMOS process, high-performance transistors cannot be produced. Therefore, many high-performance current sources need to be realized in the BiCMOS process, which greatly increases the manufacturing cost of the chip and reduces the compatibility between analog and digital circuits. However, the voltage source circuit of Embodiment 1 of the present invention only uses MOS transistors and resistors, so that the structure of the voltage source circuit is simple and the chip area occupied is small; at the same time, the manufacturing cost of the chip is reduced, and the compatibility between analog circuits and digital circuits is improved. .

Embodiment two

Embodiment 2 of the present invention provides a voltage source circuit, as shown in FIG. 2 , which is a circuit structure diagram of the voltage source circuit in Embodiment 2 of the present invention. The voltage source circuit includes a current source circuit 201 and a reference voltage output stage 202, wherein the reference voltage output stage 202 includes:

The source of the first NMOS transistor M1 is grounded, and the gate is connected to the drain;

The source of the first PMOS transistor M2 is connected to the power supply Vdd, the gate is connected to the output terminal (node 203) of the current source circuit, and the drain is connected to the drain of the first NMOS transistor M1;

The current source circuit 201 in the voltage source circuit of Embodiment 2 of the present invention includes:

The second NMOS transistor M3, the third NMOS transistor M4, the second PMOS transistor M5, the third PMOS transistor M6 and the compensation resistor R, wherein,

The source of the second NMOS transistor M3 is grounded, and the gate is connected to the drain;

The source of the third NMOS transistor M4 is grounded through the compensation resistor R, and the gate is connected to the gate of the second NMOS transistor M3;

The source of the second PMOS transistor M5 is connected to the power supply Vdd, and the drain is connected to the drain of the second NMOS transistor M3;

The source of the third PMOS transistor M6 is connected to the power supply Vdd, the gate is connected to the gate of the second PMOS transistor M5, and constitutes the output terminal 203 of the current source circuit 201, and the drain is connected to the drain of the third NMOS transistor M4, and Its gate is connected to the drain.

Specifically, the compensation resistor R can be a variable resistor, such as a slide-wire rheostat, or a fixed resistor.

Specifically, the second NMOS transistor M3 and the third NMOS transistor M4 can work in a saturation region, and can also work in a sub-threshold region. When the second NMOS transistor M3 and the third NMOS transistor M4 work in the saturation region, they can form a voltage source circuit, and the voltage source circuit can be compatible with the CMOS process; when the second NMOS transistor M3 and the third NMOS transistor M4 work in the subthreshold region , the voltage source circuit is not only compatible with the CMOS process, but also can work at a power supply voltage below 1V, and the voltage source circuit can also have the characteristics of low temperature coefficient and low power consumption.

It should be noted that the second PMOS transistor M5 and the third PMOS transistor M6 in Embodiment 2 of the present invention can work in the same working region, for example, both can work in the saturation region or the sub-threshold region, so as to ensure that the second PMOS transistor M5 It is the same as the ratio of the source-to-drain current of the third PMOS transistor M6 and the ratio of the channel size, so as to form a relationship of a current mirror in a saturation region or a sub-threshold region.

It should be noted that, for the voltage source circuit structure of Embodiment 2 of the present invention, an output reference voltage V _ref with an extremely low temperature coefficient or even close to zero can be obtained by adjusting the width-to-length ratio of the MOS transistor and the resistance value of the compensation resistor. The temperature coefficient value of the voltage source circuit will be described in detail below through specific formula derivation.

When the second NMOS transistor M3 and the third NMOS transistor M4 work in the subthreshold region, the source-drain current I _DS of the second NMOS transistor M3 can be expressed as:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; DS</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; ox</span>}}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; exp</span>}}^{\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; GS</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; TH</span>}}}{{\mathrm{<span\; class="notranslate">\; \&zeta;V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

Among them, μ _n is the mobility of the second NMOS transistor M3, C _ox is the gate oxide layer capacitance per unit area of the second NMOS transistor M3, (W/L) is the channel width-to-length ratio of the second NMOS transistor M3, V _T is the thermoelectric potential kT/q of the second NMOS tube (M3), k is the Boltzmann constant, that is, k=1.3806505×10-23J/K, T is the absolute temperature, and q is the elementary charge, that is, q=1.6× 10-19 coulombs, V _GS is the gate-source voltage difference of the second NMOS transistor M3, and V _TH is the threshold voltage of the second NMOS transistor M3.

According to Kirchhoff's voltage law, the following equation can be listed for node 205:

V _GS3 =V _GS4 +I _DS R…………………………………………………………(2)

Wherein, V _GS3 is the gate-source voltage difference of the second NMOS transistor M3 , V _GS4 is the gate-source voltage difference of the third NMOS transistor M4 , and R is the resistance value of the compensation resistor.

Substituting formula (1) into formula (2), and assuming that the threshold voltages of the second NMOS transistor M3 and the third NMOS transistor M4 are equal, it can be obtained:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; DS</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; \&zeta;V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; m</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

Wherein, assuming that the aspect ratio of the second PMOS transistor M5 , the third PMOS transistor M6 and the first PMOS transistor M2 is 1:M:N, the currents flowing through them are I _DS , MI _DS , and NI _DS respectively.

It can be seen from equation (3) that the second NMOS transistor M3 and the third NMOS transistor M4 work in the subthreshold region, which can ensure the bias determined by the second NMOS transistor M3, the third NMOS transistor M4 and the compensation resistor R The current is a current that is strictly proportional to temperature, and enables the current source circuit 201 to work at a very low power supply voltage, such as hundreds of millivolts.

The working area of the first NMOS transistor M1 in the reference voltage output stage 202 in FIG. 2 is determined by the output reference voltage V _ref . If the output reference voltage V _ref is lower than the threshold voltage of the NMOS tube, the first NMOS tube M1 works in the sub-threshold region; if the output reference voltage V _ref is higher than the threshold voltage of the NMOS tube, the first NMOS tube M1 can work in the adjacent Subthreshold region or even saturation region.

则第二PMOS管M5的源漏电流也是

进一步可以得到第一PMOS管M2的源漏电流是则第一NMOS管M1的源漏电流也是

根据（1）式可以得到：If the source-drain current of the second NMOS transistor M3 is

Then the source-drain current of the second PMOS transistor M5 is also

Further, it can be obtained that the source-drain current of the first PMOS transistor M2 is Then the source-drain current of the first NMOS transistor M1 is also

According to formula (1), we can get:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; ref</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; TH</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; \&zeta;V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\frac{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}{{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

是一个与温度无关的比例系数，热电势V_T的值与温度成正比，第一NMOS管M1的阈值电压V_TH1及迁移率μ_n都具有负的温度系数，它们分别可以表示为：in,

is a temperature-independent proportionality coefficient, the thermoelectric potential V _T is proportional to the temperature, the threshold voltage V _TH1 of the first NMOS transistor M1 and the mobility μ _n have negative temperature coefficients, which can be expressed as:

V _TH1 (T)=V _TH1 (T ₀ )-α×(TT ₀ )…………………………………………(5)

${\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; )</span>{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; )</span>}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; \&gamma;</span>}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; )</span>$

Wherein, T ₀ is the reference temperature of the room temperature, and -α is the temperature coefficient of the threshold voltage of the first NMOS transistor M1, which is a negative value in most processes. V _TH1 (T) is the threshold voltage of the first NMOS transistor M1 when the temperature is T; -γ is the temperature coefficient of the mobility of the first NMOS transistor M1, generally around -1.5, μ _n (T) is the NMOS transistor M1 when the temperature is T tube mobility.

Deriving both ends of equation (4) with respect to temperature, the first-order temperature coefficient of the reference voltage V _ref can be obtained:

$\frac{{\mathrm{<span\; class="notranslate">\; dV</span>}}_{\mathrm{<span\; class="notranslate">\; ref</span>}}}{\mathrm{<span\; class="notranslate">\; dT</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; dV</span>}}_{\mathrm{<span\; class="notranslate">\; TH</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; dT</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; \&zeta;</span>}\frac{{\mathrm{<span\; class="notranslate">\; dV</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}}{\mathrm{<span\; class="notranslate">\; dT</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\frac{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}{{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; \&zeta;</span>}\frac{{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}\frac{{\mathrm{<span\; class="notranslate">\; dV</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}}{\mathrm{<span\; class="notranslate">\; dT</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\frac{{\mathrm{<span\; class="notranslate">\; d\&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}}{\mathrm{<span\; class="notranslate">\; dT</span>}}}{{\mathrm{<span\; class="notranslate">\; \&beta;\&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 7</span>}<span\; class="notranslate">\; )</span>$

Setting equation (7) equal to zero, we get:

$\mathrm{<span\; class="notranslate">\; \&zeta;</span>}\frac{{\mathrm{<span\; class="notranslate">\; dV</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}}{\mathrm{<span\; class="notranslate">\; dT</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; ln</span>}\frac{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}{{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; \&zeta;</span>}\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\frac{{\mathrm{<span\; class="notranslate">\; d\&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}}{\mathrm{<span\; class="notranslate">\; dT</span>}}}{{\mathrm{<span\; class="notranslate">\; \&beta;\&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; dV</span>}}_{\mathrm{<span\; class="notranslate">\; TH</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; dT</span>}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; )</span>$

所以β的值与MOS管的沟道宽长比，第二PMOS管M5、第三PMOS管M6以及第一PMOS管M2的宽长比之比，补偿电阻R的阻值，MOS管的单位面积栅氧化层电容等有关。因此，可以通过调节MOS管的宽长比以及补偿电阻的阻值来设计β的值来得到一个温度系数极低甚至接近于零的输出参考电压V_ref。because

Therefore, the value of β and the channel width-to-length ratio of the MOS transistor, the ratio of the width-to-length ratio of the second PMOS transistor M5, the third PMOS transistor M6, and the first PMOS transistor M2, the resistance value of the compensation resistor R, and the unit area of the MOS transistor Gate oxide capacitance and so on. Therefore, the value of β can be designed by adjusting the width-to-length ratio of the MOS transistor and the resistance value of the compensation resistor to obtain an output reference voltage V _ref with an extremely low temperature coefficient or even close to zero.

It can be seen that the negative temperature coefficient of the mobility of the first NMOS transistor M1, the negative temperature coefficient of the threshold voltage of the first NMOS transistor M1, and the positive temperature coefficient of the thermoelectric potential kT/q of the first NMOS transistor M1 can be used to make the first NMOS transistor M1 The gate-source voltage difference of the transistor M1, that is, the output reference voltage V _ref has a zero temperature coefficient.

It should be noted that the second PMOS transistor M5 and the third PMOS transistor M6 in Embodiment 2 of the present invention can work in a saturation region or in a sub-threshold region. When the second PMOS transistor M5 and the third PMOS transistor M6 can work in the saturation region, the second PMOS transistor M5 and the third PMOS transistor M6 are connected in the form of a saturation current mirror, and the voltage source circuit of Embodiment 2 of the present invention can still work in Under lower power supply voltage; when the second PMOS transistor M5 and the third PMOS transistor M6 can work in the sub-threshold region, the second PMOS transistor M5 and the third PMOS transistor M6 are connected in the form of a sub-threshold current mirror, which can further reduce the cost. The power supply voltage required for the operation of the voltage source circuit in the second embodiment of the invention can further reduce the power consumption of the voltage source circuit.

When the power supply voltage Vdd is 0.8V, the variation curve of the output reference voltage V _ref with the temperature is shown in Figure 3, the curve is the second NMOS transistor M3 and the third NMOS transistor M4 and the second PMOS transistor M5 and the third PMOS transistor Tube M6 is obtained when both work in the sub-threshold region. It can be seen that in the temperature range of -40°C to 80°C, the change rate of the output reference voltage V _ref is extremely small, only 31.5ppm/°C.

It should be noted that the channel width-to-length ratio of the second PMOS transistor M5 and the channel width-to-length ratio of the third PMOS transistor M6 in the voltage source circuit of Embodiment 2 of the present invention may be the same or different, if the second The channel width-to-length ratio of the PMOS transistor M5 is the same as the channel width-to-length ratio of the third PMOS transistor M6, then the source-drain current of the second PMOS transistor M5 is the same as the source-drain current of the third PMOS transistor M6, to ensure that the equation ( 2) To be established, it is necessary to ensure that the channel width-to-length ratio of the second NMOS transistor M3 is different from the channel width-to-length ratio of the third NMOS transistor M4; if the channel width-to-length ratio of the second PMOS transistor M5 is different from that of the third PMOS transistor M6 The channel width-to-length ratio of the second PMOS transistor M5 is not the same as that of the third PMOS transistor M6. Equation (2) must be true. At this time, the channel of the second NMOS transistor M3 The channel width-to-length ratio and the channel width-to-length ratio of the third NMOS transistor M4 are not limited. It can be seen that when the channel width-to-length ratio of the second PMOS transistor M5 is different from the channel width-to-length ratio of the third PMOS transistor M6, the channel width-to-length ratio of the third PMOS transistor M6 The channel width-to-length ratios of the second NMOS transistor M3 and the third NMOS transistor M4 are not limited.

Compared with the voltage source circuit in the prior art whose temperature coefficient is generally higher than several hundred ppm/°C, the temperature coefficient of the voltage source circuit in Embodiment 2 of the present invention can reach a very low level, which can meet the requirements of the high-precision circuit for the reference voltage source. circuit requirements.

It should be noted that, compared with the traditional bandgap reference voltage source circuit, the output reference voltage V _ref provided by Embodiment 2 of the present invention is not fixed at a specific value, but is related to the width-to-length ratio of the MOS tube, the threshold value The voltage is related to the resistance value of the compensation resistor, and different output reference voltage requirements can be met through reasonable circuit design.

When the second NMOS transistor M3 and the third NMOS transistor M4 as well as the second PMOS transistor M5 and the third PMOS transistor M6 work in the sub-threshold region, the voltage source circuit of Embodiment 2 of the present invention can achieve circuit operation under deep submicron technology The power supply voltage is lower than the requirement of 1V, and its overall circuit power consumption can reach the nW level. The voltage source circuit of the second embodiment of the present invention can provide a working power supply voltage for the circuit under the deep submicron process, which overcomes the traditional bandgap reference voltage The high output voltage of the source cannot provide a working power supply voltage for the circuit under the deep submicron process.

The voltage source circuit of the second embodiment of the present invention is only composed of MOS tubes and compensation resistors, has a simple structure, occupies a small area of the chip, is compatible with standard CMOS technology, and reduces the manufacturing cost of the chip; the second embodiment of the present invention The NMOS transistor and the third NMOS transistor can work in the sub-threshold region, and can provide an output reference voltage lower than 1V that meets the needs of circuits operating in deep submicron processes. Compared with working in the saturation region, it can reduce the overall power consumption of the voltage source circuit ; In addition, the value of β can be designed by adjusting the width-to-length ratio of the MOS tube and the resistance value of the compensation resistor to obtain an output reference voltage with an extremely low temperature coefficient or even close to zero. Embodiment 2 of the present invention can provide a voltage source circuit with low power consumption and low temperature coefficient whose output reference voltage is less than 1V, and the voltage source circuit meets the requirements in the field of integrated circuit design.

Embodiment three

Embodiment 3 of the present invention provides a voltage source circuit, as shown in FIG. 4 , which is a schematic diagram of the circuit structure of the voltage source circuit. The voltage source circuit includes a current source circuit 401, a reference voltage output stage 402 and a startup circuit 403, wherein the reference voltage output stage 402 includes:

The source of the first NMOS transistor M1 is grounded, the gate is connected to the drain, and the node 406 constitutes a reference voltage output terminal;

The source of the first PMOS transistor M2 is connected to the power supply Vdd, the gate is connected to the output terminal (node 404 ) of the current source circuit, and the drain is connected to the drain of the first NMOS transistor M1;

The current source circuit 401 in the voltage source circuit of Embodiment 3 of the present invention includes:

The second NMOS transistor M3, the third NMOS transistor M4, the second PMOS transistor M5, the third PMOS transistor M6 and the compensation resistor R, wherein,

The source of the second NMOS transistor M3 is grounded, and the gate is connected to the drain;

The source of the third NMOS transistor M4 is grounded through the compensation resistor R, and the gate is connected to the gate of the second NMOS transistor M3;

The source of the second PMOS transistor M5 is connected to the power supply Vdd, and the drain is connected to the drain of the second NMOS transistor M3;

The source of the third PMOS transistor M6 is connected to the power supply Vdd, the gate is connected to the gate of the second PMOS transistor M5, and constitutes the output terminal 404 of the current source circuit 401, and the drain is connected to the drain of the third NMOS transistor M4, and Its gate is connected to the drain;

The startup circuit 403 of Embodiment 3 of the present invention includes:

The source of the fourth PMOS transistor M7 is connected to the power supply Vdd, and the gate is connected to the drain of the second PMOS transistor M5;

The source of the fourth NMOS transistor M8 is grounded, the gate is connected to the gate of the fourth PMOS transistor M7, and the drain is connected to the drain of the fourth PMOS transistor M7;

The source of the fifth NMOS transistor M9 is grounded, the gate is connected to the drain of the fourth PMOS transistor M7, and the drain is connected to the gate of the second PMOS transistor M5.

Specifically, the fourth PMOS transistor M7 and the fourth NMOS transistor M8 are connected in an inverter mode, the input terminal of the inverter is connected to the drain of the second NMOS transistor M3, and the output terminal of the inverter is connected to the fifth NMOS transistor M3. Gate of tube M9.

Specifically, when the power supply voltage is turned on, if the voltage source circuit operates at a static operating point where the current is zero, the start-up circuit 403 operates. As shown in Figure 4, when the voltage source circuit works at the static operating point where the current is zero, the collector junctions of the second PMOS transistor M5 and the third PMOS transistor M6 are both in reverse bias, and the emitter junction is not turned on, M5 and M6 works in the cut-off region; the collector junctions of the second NMOS transistor M3 and the third NMOS transistor M4 are also in reverse bias, the emitter junction is not turned on, and they also work in the cut-off region, so the level of the node 404 is the power supply voltage, The level of node 405 is zero, then the fourth PMOS transistor M7 works in the linear region, that is, the emitter junction of M7 is forward biased, the collector junction is reverse biased, and M7 is turned on; the fourth NMOS transistor M8 works in The cut-off region, that is, the collector junction of M8 is in reverse bias, and the emitter junction is not turned on. At this time, the output level of the node 407 is the power supply voltage, so that the fourth NMOS transistor M8 is turned on and operates in the linear region, so the level of the node 404 is pulled down, and then the voltage source circuit 401 returns to a non-zero current stable working point.

It should be noted that after the voltage source circuit 401 works at a stable operating point with non-zero current, the fourth PMOS transistor M7 , the fourth NMOS transistor M8 and the fifth NMOS transistor M9 all work in the cut-off region. That is: after completing the start-up operation of the voltage source circuit, the start-up circuit 403 turns to the cut-off state. At this time, the start-up circuit 403 does not consume any DC power consumption; If the static operating point is zero, the startup circuit 403 does not work.

In this working mode, the start-up circuit 403 does not consume any DC power consumption in other processes except for a certain power consumption during the start-up process of the voltage source circuit. Therefore, the overall DC power consumption of the voltage source circuit is relatively low.

It should be noted that, according to design requirements, the size of the fourth PMOS transistor M7 and the fourth NMOS transistor M8 can be designed within a certain range, so that the level of the node 408 is higher than the threshold voltage of the inverter, so that the node 408 407 output low level.

In addition, the start-up circuit 403 in the embodiment of the present invention may also adopt other start-up circuits commonly used in the field.

In the embodiment of the present invention, when the voltage source circuit is working at the static operating point where the current is zero, the starting circuit is used to start the voltage source circuit, which ensures the normal operation of the voltage source circuit; after completing the starting operation of the voltage source circuit, the starting circuit turns to In the cut-off state, at this time, the startup circuit does not consume any DC power consumption; in addition, after the power is turned on, if the voltage source circuit works at a non-zero current static operating point, the startup circuit does not work. It can be seen that the start-up circuit does not consume any DC power consumption in other processes except that it consumes a certain amount of power in the process of starting the voltage source circuit, which can greatly reduce the overall DC power consumption of the voltage source circuit.

The above is only a preferred embodiment of the present invention, it should be pointed out that, for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications can also be made. It should be regarded as the protection scope of the present invention.

Claims (6)

1. A voltage source circuit, comprising a current source circuit and a reference voltage output stage, characterized in that, The current source circuit is composed of a MOS tube and a resistor, and the current source circuit is connected to a power supply and grounded to provide an output current proportional to temperature; The reference voltage output stage includes a first PMOS transistor and a first NMOS transistor, The source of the first PMOS transistor is connected to the power supply, the gate is connected to the output terminal of the current source circuit, and the drain is connected to the drain of the first NMOS transistor, which is used to output the current source circuit the output current mirror; The source of the first NMOS transistor is grounded, and the gate is connected to the drain for converting the mirrored output current into an output voltage. 2. The voltage source circuit according to claim 1, wherein the current source circuit comprises a second NMOS transistor, a third NMOS transistor, a second PMOS transistor, a third PMOS transistor and a compensation resistor, wherein, The source of the second NMOS transistor is grounded, and the gate is connected to the drain; The source of the third NMOS transistor is grounded through the compensation resistor, and the gate is connected to the gate of the second NMOS transistor; The source of the second PMOS transistor is connected to the power supply, and the drain is connected to the drain of the second NMOS transistor; The source of the third PMOS transistor is connected to the power supply, the gate is connected to the gate of the second PMOS transistor, and constitutes the output end of the current source circuit, and the drain is connected to the drain of the third NMOS transistor. The pole is connected, and the gate is connected to the drain. 3. The voltage source circuit according to claim 2, wherein the voltage source circuit further comprises a startup circuit, and the startup circuit comprises: For a fourth PMOS transistor, the source is connected to the power supply, and the gate is connected to the drain of the second PMOS transistor; The source of the fourth NMOS transistor is grounded, the gate is connected to the gate of the fourth PMOS transistor, and the drain is connected to the drain of the fourth PMOS transistor; The source of the fifth NMOS transistor is grounded, the gate is connected to the drain of the fourth PMOS transistor, and the drain is connected to the gate of the second PMOS transistor. 4. The voltage source circuit according to claim 2 or 3, wherein the channel width-to-length ratio of the second PMOS transistor is different from that of the third PMOS transistor. 5. The voltage source circuit according to claim 2 or 3, wherein the second NMOS transistor and the third NMOS transistor work in a sub-threshold region. 6. The voltage source circuit according to claim 5, wherein the second PMOS transistor and the third PMOS transistor work in a sub-threshold region.

Images