CN102662427A - Voltage source circuit - Google Patents

Voltage source circuit Download PDF

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CN102662427A
CN102662427A CN 201210167250 CN201210167250A CN102662427A CN 102662427 A CN102662427 A CN 102662427A CN 201210167250 CN201210167250 CN 201210167250 CN 201210167250 A CN201210167250 A CN 201210167250A CN 102662427 A CN102662427 A CN 102662427A
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tube
source
circuit
voltage
connected
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CN 201210167250
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Chinese (zh)
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赵喆
陈岚
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中国科学院微电子研究所
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Abstract

An embodiment of the invention provides a voltage source circuit which comprises a current source circuit and a reference voltage output level. The reference voltage output level comprises a first NMOS (N-channel metal oxide semiconductor) tube and a first PMOS (P-channel metal oxide semiconductor) tube. A source electrode of the first NMOS tube is earthed, and a grid and a drain thereof are connected. A source electrode of the first PMOS tube is connected with a power supply, a grid of the first PMOS tube is connected with the current source circuit, and a drain of the first PMOS tube is connected with the drain of the first NMOS tube. The current source circuit consists of an MOS (metal oxide semiconductor) tube and a resistor. Bi-polar transistors and other types of transistors are omitted due to the MOS tube and the resistor. Besides, the voltage source circuit is simple in structure, small in chip occupation space, low in manufacturing cost and applicable to the standard CMOS (complementary metal oxide semiconductor) process compatible with digital circuits, and compatibility of a simulation circuit and a digital circuit is improved.

Description

一种电压源电路 A voltage source circuit

技术领域 FIELD

[0001 ] 本发明涉及集成电路技术领域,具体涉及ー种电压源电路。 [0001] The present invention relates to the field of integrated circuit technology, particularly relates to a voltage source circuit ー seed.

背景技术 Background technique

[0002] 电压源电路是集成电路系统中非常重要的基本电路之一,它为芯片中其他模块的正常工作提供了必要的偏置电压,因此电压源电路的性能很大程度上影响了芯片的整体性能。 [0002] The voltage source circuit of an integrated circuit is one of the very important basic circuit system, which provides the necessary bias to the chip normal operation of other modules, so the performance largely affects the voltage source circuit chip overall performance. 随着微电子制造エ艺技术的发展以及个人便携设备、无线接收机等消费市场的急剧增カロ,对电压源电路提出的设计挑战也越来越高。 With Ester microelectronics manufacturing process technology development and personal portable devices, radio receivers and other consumer markets increased sharply ka ro, the voltage source circuit design challenges raised higher and higher.

[0003] 但目前广泛应用的电压源电路大多来源于双极型带隙基准,这类电压源电路需要较高性能的双极型晶体管,占用面积大,制造成本高,有些甚至需要在BiCMOS或双极型エ艺下实现,不能与标准CMOSエ艺兼容,不能满足深亚微米エ艺下的集成电路设计要求。 [0003] However, the voltage source circuit from the widely used mostly bipolar bandgap reference voltage source circuit requires such high performance bipolar transistor, a large occupied area, high manufacturing costs, and some or even necessary BiCMOS achieved under Arts bipolar Ester, Ester is not compatible with standard CMOS Arts, integrated circuit design can not meet the requirements under deep submicron Ester Arts.

发明内容 SUMMARY

[0004] 有鉴于此,本发明g在提供一种能够与CMOSエ艺兼容的电压源电路,以解决现有技术中电压源电路与CMOSエ艺不兼容的缺陷。 [0004] Accordingly, the present invention is to provide a capable g Ester CMOS compatible voltage source circuit arts, the prior art to solve the voltage source circuit is not compatible with CMOS Ester arts defects.

[0005] 为此,本发明技术方案提供ー种与CMOSエ艺兼容的电压源电路,包括电流源电路和參考电压输出级,所述电流源电路由MOS管和电阻组成,所述电流源电路与电源相连并接地,用于提供与温度成正比的输出电流; [0005] To this end, the present invention provides a technical solution with kinds ー CMOS compatible arts Ester voltage source circuit comprising a current source circuit and the reference voltage output stage, the current source circuit composed of a MOS transistor and a resistor, said current source circuit and is connected to a ground power supply, for providing an output current proportional to the temperature;

[0006] 所述參考电压输出级包括第一PMOS管和第一NMOS管, [0006] The reference voltage output stage includes a first PMOS transistor and a first NMOS transistor,

[0007] 所述第一PMOS管的源极与所述电源相连,栅极与电流源电路的输出端相连,漏极与所述第一NMOS管的漏极相连,用于将所述电流源电路输出的所述输出电流镜像; Source [0007] electrode of the first PMOS transistor is connected to the power supply, a gate connected to the output terminal of the current source circuit, a drain connected to the drain of said first NMOS transistor, a current source for the an output of said current mirror circuit output;

[0008] 所述第一NMOS管的源极接地,栅极与漏极相连,用于将镜像后的所述输出电流转换成输出电压。 Source [0008] The first NMOS transistor is grounded, and a drain connected to the gate, for converting the output current into an output voltage the mirror.

[0009] 优选地,所述电流源电路包括第二NMOS管、第三NMOS管、第二PMOS管、第三PMOS管以及补偿电阻,其中, [0009] Preferably, the current source circuit comprises a second NMOS transistor, the third NMOS transistor, a second PMOS transistor, the third PMOS transistor and a compensation resistor, wherein

[0010] 所述第二NMOS管的源极接地,栅极与漏极相连; Source [0010] of the second NMOS transistor is grounded, a gate connected to a drain;

[0011] 所述第三NMOS管的源极通过所述补偿电阻接地,栅极与所述第二NMOS管的栅极相连; Source [0011] electrode of the third NMOS transistor is grounded through a compensating resistor, a gate connected to the gate of the second NMOS transistor;

[0012] 所述第二PMOS管的源极接所述电源,漏极与所述第二NMOS管的漏极相连; [0012] The source of the second PMOS transistor is connected to the power supply, a drain connected to the drain of said second NMOS transistor;

[0013] 所述第三PMOS管的源极接所述电源,栅极与所述第二PMOS管的栅极相连,并构成所述电流源电路的输出端,漏极与所述第三匪OS管的漏极相连,且栅极与漏极相连。 Source [0013] The third PMOS transistor is connected to said power source connected to the gate, a gate of said second PMOS transistor, and the current source circuit constituting an output terminal, a drain connected to said third bandit OS drain pipe is connected, and is connected to the gate and drain.

[0014] 优选地,所述电压源电路还包括启动电路,所述启动电路包括: [0014] Preferably, the circuit further comprises a starting voltage source circuit, said starting circuit comprising:

[0015] 第四PMOS管,源极与所述电源相连,栅极与所述第二PMOS管的漏极相连; [0015] the fourth PMOS transistor, a source connected to the power supply, a gate connected to the drain of the second PMOS transistor;

[0016] 第四NMOS管,源极接地,栅极与所述第四PMOS管的栅极相连,漏极与所述第四PMOS管的漏极相连; [0016] The fourth NMOS transistor, a source grounded, a gate connected to the gate of the fourth PMOS transistor, a drain connected to the drain of the fourth PMOS transistor;

[0017] 第五NMOS管,源极接地,栅极与所述第四PMOS管的漏极相连,漏极与所述第二、PMOS管的栅极相连。 [0017] The fifth NMOS transistor, a source grounded, a gate connected to the drain of the fourth PMOS transistor, a drain connected to said second gate, PMOS transistor.

[0018] 优选地,所述第二PMOS管的沟道宽长比与所述第三PMOS管的沟道宽长比不相同。 A channel width to length [0018] Preferably, the second PMOS transistor are not the same as the ratio of the third PMOS transistor channel width to length ratio.

[0019] 优选地,所述第二NMOS管和第三NMOS管工作在亚阈值区。 [0019] Preferably, the second NMOS transistor and the third NMOS transistor subthreshold operation value in the region.

[0020] 优选地,所述第二PMOS管和第三PMOS管工作在亚阈值区。 [0020] Preferably, the second PMOS transistor and the third PMOS transistor subthreshold operation value in the region.

[0021] 本发明实施例中的电压源电路,仅使用MOS管和电阻,不需要双极型晶体管以及其他类型的晶体管,结构简单,占用芯片的面积小,制造成本低,能够用于与数字电路兼容的标准CMOSエ艺中,提高了模拟电路与数字电路的兼容性。 [0021] The voltage source circuit in the embodiment of the present invention, only the MOS transistor and a resistor, and a bipolar transistor does not need other types of transistors, simple structure, small area occupied by the chip, the manufacturing cost is low, can be used with the digital Ester compatible with standard CMOS circuits in the arts, improve compatibility analog circuits and digital circuits.

附图说明 BRIEF DESCRIPTION

[0022] 为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。 [0022] In order to more clearly illustrate the technical solutions in the embodiments or the prior art embodiment of the present invention, briefly introduced hereinafter, embodiments are described below in the accompanying drawings or described in the prior art needed to be used in describing the embodiments figures some embodiments of the present invention, those of ordinary skill in the art is concerned, without creative efforts, can derive from these drawings other drawings.

[0023] 图I是本发明实施例一的电压源电路的电路结构图; [0023] Figure I is a circuit configuration diagram of a voltage source circuit according to an embodiment of the present invention;

[0024] 图2是本发明实施例ニ的电压源电路的电路结构图; [0024] FIG. 2 is a circuit configuration diagram of a voltage source circuit according to embodiments of the present invention, ni;

[0025] 图3是本发明实施例ニ的电压源电路的參考电压随温度的变化曲线示意图; [0025] FIG. 3 is a schematic diagram of the temperature curve of the reference voltage with a voltage source circuit ni embodiment of the present invention;

[0026] 图4是本发明实施例三的电压源电路的电路结构图。 [0026] FIG. 4 is a circuit configuration diagram of a voltage source circuit according to a third embodiment of the present invention.

具体实施方式 detailed description

[0027] 为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。 [0027] In order that the invention object, technical solutions, and advantages of the embodiments more clearly, the following the present invention in the accompanying drawings, technical solutions of embodiments of the present invention are clearly and completely described, obviously, the described the embodiment is an embodiment of the present invention is a part, but not all embodiments. 基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。 Based on the embodiments of the present invention, all other embodiments of ordinary skill in the art without any creative effort shall fall within the scope of the present invention.

[0028] 现有技术中,传统的电压源电路由MOS管、运放及三极管等部分构成,电路结构复杂,占用芯片面积较大,制造成本较高;并且,传统电压源电路无法与CMOS标准エ艺相兼容,在深亚微米エ艺不断发展的过程中,需要提高模拟电路与数字电路的兼容性。 [0028] In the prior art, the conventional voltage source circuit of the MOS tube, transistor amplifier and other parts, a complicated circuit structure, occupies a large chip area, high manufacturing cost; and, the conventional source voltage of the CMOS circuit can not standard Ester compatible arts, in the process of deep submicron Ester growing arts, it is necessary to improve the compatibility of the analog and digital circuits. 本发明实施例g在提供一种能够与CMOS标准エ艺兼容的电压源电路,以提高模拟电路与数字电路的兼容性,以满足深亚微米エ艺技术的要求。 G Example embodiments of the present invention to provide a standard CMOS capable Ester arts compliant voltage source circuit, to improve the compatibility of the analog and digital circuits in order to meet the requirements of deep sub-micron technology Ester arts.

[0029] 实施例一 [0029] Example a

[0030] 本发明实施例一提供一种电压源电路,如图I所示,为本发明实施例一的电压源电路的电路结构图。 Example [0030] The present invention provides a voltage source of a circuit shown in FIG. I, the circuit configuration diagram of a voltage source circuit according to one embodiment of the present invention. 该电压源电路包括电流源电路101和參考电压输出级102,其中,电流源电路101由MOS管和电阻组成,且电流源电路101与电源Vdd相连并接地,电流源电路101用于提供与温度成正比的输出电流; The voltage source circuit comprises a current source circuit 101 and the reference voltage output stage 102, wherein the current source circuit 101 is composed of a MOS transistor and a resistor, and a current source circuit 101 is connected to the power supply Vdd and ground, a current source circuit 101 for providing temperature proportional to the output current;

[0031] 參考电压输出级102包括: [0031] The reference voltage output stage 102 comprises:

[0032] 第一PMOS管M2,其源极与电源Vdd相连,栅极与电流源电路的输出端相连,漏极与第一NMOS管Ml的漏极相连,用于将电流源电路101输出的输出电流镜像; [0032] The first PMOS transistor M2, which is connected to a power source Vdd, a gate connected to the output terminal of the current source circuit is connected to the drain of the first NMOS transistor Ml for the current source circuit 101 outputs an output current mirror;

[0033] 第一NMOS管Ml,其源极接地,栅极与漏极相连,用于将第一PMOS管M2镜像后的输出电流转换成输出电压。 [0033] First of Ml NMOS transistor, whose source is grounded, and a drain connected to the gate, for converting the output current of the first PMOS transistor M2 mirror into an output voltage.

[0034] 由图I可见,第一NMOS管Ml和第一PMOS管M2连接成ニ极管的形式,參考电压Vref可以由节点103输出。 [0034] seen in Figure I, a first NMOS transistor Ml and the PMOS transistor M2 is connected to a first form of Ni diode, the reference voltage Vref can be output by the node 103.

[0035] 需要说明的是,本发明实施例一中的电流源电路可以是现有技术中任何仅由MOS管和电阻组成并且其输出电流与温度成正比的电流源电路;电流源电路101中可以包括连接成共源共栅电流镜形式的MOS管,共源共栅的MOS管起到电流镜的作用,保证电流源电路的各支路的电流相等或成一定比例。 [0035] Incidentally, the current source circuit according to an embodiment of the present invention may be any of the prior art current source circuit of the MOS transistor and resistors only and is proportional to the output current and temperature; the current source circuit 101 may include a connection to the cascode current mirror in the form of MOS transistors, the cascode MOS transistor functions as a current mirror, the current in each branch to ensure that the current source circuit is equal or proportional. 其中,第一PMOS管M2的栅极可以与该电流镜的共用栅极连接。 Wherein the gate of the first PMOS transistor M2 may be connected to the common gate of the current mirror.

[0036] 如果电流源电路中使用运放,会造成电压源电路结构复杂,同时会消耗较大的功耗,无法满足集成电路结构简单的要求;另外,一些电流源电路中使用三极管,但在与数字电路兼容的标准CMOSエ艺中,无法制作出高性能的三极管,所以,很多高性能电流源需要在BiCMOSエ艺下实现,这就大大提高了芯片的制造成本,降低了模拟电路与数字电路的兼容性。 [0036] If the current source circuit used in the amplifier will cause a voltage source circuit configuration complex, and it will consume more power, simply can not meet the requirements of the integrated circuit structure; Further, some of the transistors used in the current source circuit, but in the compatible with standard CMOS digital circuits Ester arts, you can not produce high-performance transistors, so many high-performance current sources need to achieve in BiCMOS Ester Arts, which greatly increases the manufacturing cost of the chip, reducing the analog and digital circuits compatibility circuits. 然而,本发明实施例一的电压源电路仅使用MOS管和电阻,使得电压源电路的结构简単,占用芯片面积小;同时,降低了芯片的制造成本,提高了模拟电路与数字电路的兼容性。 Small simple structure radiolabeling occupied chip area voltage source circuit according to a However, the embodiment of the present invention uses only MOS transistor and a resistor, the voltage source circuit; while reducing the manufacturing cost of the chip, to improve the compatibility analog circuits and digital circuits sex. [0037] 实施例ニ [0037] Example ni

[0038] 本发明实施例ニ提供一种电压源电路,如图2所示,为本发明实施例ニ的电压源电路的电路结构图。 Example ni embodiment [0038] The present invention provides a voltage source circuit, shown in Figure 2, is a circuit configuration diagram of a voltage source circuit ni embodiment of the invention. 该电压源电路包括电流源电路201和參考电压输出级202,其中,參考电压输出级202包括: The voltage source circuit comprises a current source circuit 201 and the reference voltage output stage 202, wherein the reference voltage output stage 202 comprises:

[0039] 第一NMOS管Ml,源极接地,栅极与漏极相连; [0039] First of Ml NMOS transistor, a source grounded, a gate connected to a drain;

[0040] 第一PMOS管M2,源极与电源Vdd相连,栅极与电流源电路的输出端(节点203)相连,漏极与第一NMOS管Ml的漏极相连; [0040] The first PMOS transistor M2, a source connected to power supply Vdd, (node ​​203) connected to the output terminal of the current source circuit of the gate, and a drain connected to the drain of the first NMOS transistor Ml;

[0041] 本发明实施例ニ的电压源电路中的电流源电路201包括: [0041] The current source circuit 201 a voltage source circuit according to the present embodiment ni invention include:

[0042] 第二NMOS管M3、第三NMOS管M4、第二PMOS管M5、第三PMOS管M6以及补偿电阻R,其中, [0042] The second NMOS transistor M3, the third NMOS transistor M4, a second PMOS transistor M5, M6 third PMOS transistor and a compensation resistor R, wherein

[0043] 第二NMOS管M3的源极接地,栅极与漏极相连; [0043] The source of the second NMOS transistor M3 is grounded, a gate connected to a drain;

[0044] 第三NMOS管M4的源极通过补偿电阻R接地,栅极与第二NMOS管M3的栅极相连; [0044] The source of the third NMOS transistor M4 is connected to the compensating resistor R is grounded through a gate, the gate of the second NMOS transistor M3;

[0045] 第二PMOS管M5的源极接电源Vdd,漏极与第二NMOS管M3的漏极相连; [0045] The source of the second PMOS transistor M5 is connected to the power supply Vdd, the drain connected to the drain of the second NMOS transistor M3;

[0046] 第三PMOS管M6的源极接电源Vdd,栅极与第二PMOS管M5的栅极相连,并构成电流源电路201的输出端203,漏极与第三NMOS管M4的漏极相连,且其栅极与漏极相连。 [0046] The source of the third PMOS transistor M6 is connected to power supply Vdd, a gate connected to the gate of the second PMOS transistor M5, and the current source circuit 201 constitutes the output terminal 203, the drain of the third NMOS transistor M4 It is connected, and having a gate connected to the drain.

[0047] 具体地,补偿电阻R可以为可变电阻,如滑线变阻器,也可以为固定电阻。 [0047] In particular, compensation resistor R may be a variable resistor, such as a slide rheostat, it may be a fixed resistor.

[0048] 具体地,第二NMOS管M3和第三NMOS管M4可以工作在饱和区,也可以工作在亚阈值区。 [0048] Specifically, the second NMOS transistor M3 and a third NMOS transistor M4 may operate in the saturation region, can also work in sub-threshold region. 第二NMOS管M3和第三NMOS管M4工作在饱和区时可以构成电压源电路,并且该电压源电路可以与CMOSエ艺兼容;第二NMOS管M3和第三NMOS管M4工作在亚阈值区时,该电压源电路不但可以与CMOSエ艺兼容,还可以工作在IV以下的电源电压,并且该电压源电路还可以具有低温度系数以及低功耗的特点。 A second NMOS transistor M3 and a third NMOS transistor M4 operates in a saturation region can constitute a voltage source circuit, and the voltage source circuit may be compatible with the CMOS Ester arts; second NMOS transistor M3 and M4 operate in a third NMOS transistor subthreshold region when the voltage source circuit can not only compatible with CMOS Ester arts, can also work in the power source voltage IV below, and the voltage source circuit may also have a low temperature coefficient and low power consumption.

[0049] 需要说明的是,本发明实施例ニ中的第二PMOS管M5和第三PMOS管M6可以工作在相同的工作区域,如均可以工作在饱和区或者亚阈值区,以保证第二PMOS管M5和第三PMOS管M6的源漏电流之比与沟道尺寸之比相同,以构成饱和区或者亚阈值区电流镜的关系。 [0049] Incidentally, the second PMOS transistor and the third PMOS transistor M5 M6 ni embodiment of the present invention can operate in the same work area, such as can be in the saturation region or sub-threshold region, to ensure that a second source-drain current of the PMOS transistors M5 and M6 of the third PMOS transistor and the ratio of the channel dimensions, in order to constitute a saturated region or relation subthreshold current mirror ratio of the same.

[0050] 需要说明的是,对于本发明实施例ニ的电压源电路结构,可以通过调节MOS管的宽长比以及补偿电阻的阻值来得到ー个温度系数极低甚至接近于零的输出參考电压vMf。 [0050] Incidentally, the voltage source circuit structure of the embodiment of the present invention, Ni may be obtained by adjusting the width to length ratio ー resistance of compensation resistor and MOS transistor low coefficient temperatures even close to zero the output of the reference voltage vMf. 下面通过具体公式推导,来详细说明该电压源电路的温度系数值。 Derived by the following specific formula, the value of the temperature coefficient of the voltage source circuit will be described in detail. [0051] 当第二NMOS管M3和第三NMOS管M4工作在亚阈值区时,第二NMOS管M3的源漏 [0051] When the second NMOS transistor M3 and a third NMOS transistor M4 is operating in sub-threshold region, the source and drain of the second NMOS transistor M3

电流Ids可以表示为: Current Ids can be expressed as:

[0052] [0052]

Figure CN102662427AD00061

[0053] 其中,μ n为第二NMOS管M3的迁移率,Cox是第二NMOS管M3的単位面积栅氧化层电容,(W/L)为第二NMOS管M3的沟道宽长比,Vt为第二NMOS管(M3)的热电势kT/q,k为波尔兹曼常数,即k=l. 3806505X 10-23J/K, T为绝对温度,q为元电荷电量,即q=l. 6X10-19库伦,Vgs为第二NMOS管M3的栅源电压差,Vth为第二NMOS管M3的阈值电压。 [0053] where, μ n is the mobility of the second NMOS transistor M3, Cox is the gate oxide layer. Unit area capacitance of the second NMOS transistor M3, (W / L) of the second NMOS transistor M3 is longer than the channel width, Vt is a second NMOS transistor (M3) thermopower kT / q, k is Boltzmann's constant, i.e., k = l. 3806505X 10-23J / K, T is the absolute temperature, q is an elementary charge quantity, i.e., q = l. 6X10-19 Coulomb, Vgs is the gate-source voltage difference of the second NMOS transistor M3, Vth is the threshold voltage of the second NMOS transistor M3.

[0054] 依据基尔霍夫电压定律,对于节点205可以列出如下等式: [0054] According KVL for node 205 can list the following equation:

[0055] VGS3-VGS4+IDSR..................................................................... (2) [0055] VGS3-VGS4 + IDSR .......................................... ........................... (2)

[0056] 其中,Ves3为第二NMOS管M3的栅源电压差,Ves4为第三NMOS管M4的栅源电压差,R为补偿电阻的阻值。 [0056] wherein, Ves3 is the gate-source voltage difference of the second NMOS transistor M3, Ves4 gate-source voltage for the NMOS transistor M4, the third difference, R is the resistance of compensation resistor.

[0057] 将(I)式代入(2)式中,并假设第二NMOS管M3和第三NMOS管M4的阈值电压相 [0057] The formula (I) into (2) In the formula, and assuming the threshold voltage of the second NMOS transistor M3 and NMOS transistor M4, the third phase

等,可以得到: And so on, you can get:

[0058] [0058]

Figure CN102662427AD00062

[0059] 其中,令第二PMOS管M5、第三PMOS管M6以及第一PMOS管M2的宽长比之比是I :M:N,则流过它们的电流分别为Ids,MIds, NIds。 [0059] wherein, to enable the second PMOS transistor M5, M6 width to length third PMOS transistor and a first PMOS transistor M2 ratio is the ratio of I: M: N, the current flowing through them are Ids, MIds, NIds.

[0060] 由等式(3)可以看出,第二NMOS管M3和第三NMOS管M4工作在亚阈值区,可以保证由第二NMOS管M3和第三NMOS管M4以及补偿电阻R所确定的偏置电流是ー个与温度严格成正比的电流,并且,使得电流源电路201可以工作在很低的电源电压下,如几百毫伏。 [0060] As can be seen from equation (3), a second NMOS transistor M3 and NMOS transistor M4 operate in the third sub-threshold region, it may ensure that determined by the second and the third NMOS transistor M3 and NMOS transistor M4 compensation resistor Rー a bias current is strictly proportional to the current temperature, and that the current source circuit 201 can operate at low supply voltage, such as a few hundred millivolts.

[0061] 图2中參考电压输出级202中的第一NMOS管Ml的工作区域由输出參考电压Vref決定。 The working region of the first NMOS transistor Ml in reference 202. [0061] FIG 2 is determined by the voltage of the output stage output reference voltage Vref. 如果输出參考电压VMf低于NMOS管的阈值电压,则第一NMOS管Ml工作在亚阈值区;如果输出參考电压Vref高于NMOS管的阈值电压,则第一NMOS管Ml可以工作在邻近亚阈值区甚至饱和区。 If the output reference voltage VMf lower than the threshold voltage of the NMOS transistor, the first NMOS transistor Ml to work in sub-threshold region; if the output reference voltage Vref is higher than the threshold voltage of the NMOS transistor, the first NMOS transistor Ml can work values ​​adjacent subthreshold District even saturation region.

[0062] 如果第二NMOS管M3的源漏电流是 [0062] If the source of the second NMOS transistor M3 is the drain current

Figure CN102662427AD00063

,则第二PMOS管 , The second PMOS transistor

Μ5的源漏电流也是 The source-drain current is Μ5

Figure CN102662427AD00064

;进ー步可以得到第一PMOS管M2的源漏电 ; Get further into ー source drain of the first PMOS transistor M2

Figure CN102662427AD00065

则第一NMOS管Ml的源漏电流也是 A first NMOS transistor Ml to the source-drain current is

Figure CN102662427AD00066

根据(I)式可以得到: According to formula (I) can be obtained:

[0063] [0063]

Figure CN102662427AD00067

[0064] 其中 [0064] in which

Figure CN102662427AD00068

是ー个与温度无关的比例系数,热电势Vt的值与温度成正比,第一NMOS管Ml的阈值电压Vthi及迁移率μ n都具有负的温度系数,它们分别可以表示为: It is independent of temperature ー a scaling factor proportional to the value of the temperature of the thermoelectric potential Vt, the first NMOS transistor Ml threshold voltage Vthi and the mobility μ n has a negative temperature coefficient, respectively, can be expressed as:

[0065] [0065]

Figure CN102662427AD00071

[0066] [0066]

[0067] 其中,Tci为室温参考温度,-α为第一NMOS管Ml的_值电压的温度系数,在大多数エ艺中为负值。 [0067] where, the reference temperature Tci is the temperature, the temperature coefficient [alpha _ value of the voltage of the first NMOS transistor Ml in most Ester arts as negative. Vthi⑴为温度为T时第一NMOS管Ml的阈值电压;-Y为第一NMOS管Ml迀移率的温度系数,一般在-1. 5左右,μη(Τ)为温度为T时NMOS管的迀移率。 Vthi⑴ threshold voltage when the temperature T of the first NMOS transistor Ml; -Y is the temperature coefficient of a first NMOS Ml tube Gan shift rate, generally about -1 5, μη (Τ) as temperature T of the NMOS transistor. Gan shift rate.

[0068] 将等式(4)的两端对温度求导,可以得到参考电压Vm的ー阶温度系数: [0068] The two ends of the equation (4) to a temperature of derivation, the reference voltage Vm can be obtained ー order temperature coefficient of:

[0069] [0069]

Figure CN102662427AD00072

[0070] 令等式(7)等于零,则可以得到: [0070] so equation (7) is equal to zero, it can be obtained:

[0071] [0071]

Figure CN102662427AD00073

[0072] 因为 [0072] because

Figure CN102662427AD00074

所以β的值与MOS管的沟道宽长比,第二PMOS管Μ5、第三 Therefore, the channel width to length ratio β value and the MOS transistor, a second PMOS transistor Μ5, third

PMOS管M6以及第一PMOS管M2的宽长比之比,补偿电阻R的阻值,MOS管的单位面积栅氧化层电容等有夫。 PMOS transistor M6 and the width to length of the first PMOS transistor M2 than the ratio of the resistance of the compensation resistor R, the unit area of ​​the MOS transistor gate oxide capacitance married. 因此,可以通过调节MOS管的宽长比以及补偿电阻的阻值来设计β的值来得到ー个温度系数极低甚至接近于零的输出參考电压VMf。 Thus, the value of β can be designed by adjusting the aspect ratio of the resistance of compensation resistor and MOS transistors to obtain a low coefficient ー temperatures even close to zero output reference voltage VMf.

[0073] 可见,可以利用第一NMOS管Ml的迁移率的负温度系数、第一NMOS管Ml的阈值电压的负温度系数以及第一NMOS管Ml的热电势kT/q的正温度系数,使得第一NMOS管Ml的的栅源电压差即输出參考电压具有零温度系数。 [0073] visible, can utilize the mobility of the negative temperature coefficient of the first NMOS transistor Ml, the positive temperature coefficient negative temperature coefficient of the threshold voltage of the first NMOS transistor and a first NMOS transistor Ml Ml thermopower kT / q, so that gate-source voltage difference between the first NMOS transistor Ml, i.e., the output of the reference voltage has a zero temperature coefficient.

[0074] 需要说明的是,本发明实施例ニ中的第二PMOS管M5和第三PMOS管M6可以工作在饱和区,也可以工作在亚阈值区。 [0074] Incidentally, in the second embodiment of Ni, and the third PMOS transistor M5 M6 may be PMOS transistors operate in the saturation region of the present invention may also operate in sub-threshold region. 第二PMOS管M5和第三PMOS管M6可以工作在饱和区时,第二PMOS管M5和第三PMOS管M6连接成饱和电流镜的形式,本发明实施例ニ的电压源电路仍然可以工作在较低的电源电压下;第二PMOS管M5和第三PMOS管M6可以工作在亚阈值区时,第二PMOS管M5和第三PMOS管M6连接成亚阈值电流镜的形式,可以进ー步降低本发明实施例ニ的电压源电路工作所需的电源电压,并且可以进一歩降低电压源电路的功耗。 The second and third PMOS transistors M5 M6 may be PMOS transistors operate in the saturation region, the second PMOS transistor M5 and the third PMOS transistor M6 is connected to saturating current mirror embodiment of the present invention embodiment ni voltage source circuit can still operate in lower power supply voltage; a second PMOS transistor M5 and the third PMOS transistor M6 may be operating in sub-threshold region, the second PMOS transistor M5 and M6 is connected to the third PMOS transistor subthreshold form a current mirror, you can enter further ーembodiment of the present invention to reduce the required voltage source circuit ni supply voltage embodiment, and may be lowered into a ho voltage power source circuit.

[0075] 当电源电压Vdd为O. 8V吋,输出參考电压V,ef随温度的变化曲线如图3所示,该曲线是在第二NMOS管M3和第三匪OS管M4以及第二PMOS管M5和第三PMOS管M6均工作在亚阈值区时得到的,可见,在-40°C〜80°C温度范围内,输出參考电压Vref的变化率极小,仅为31. 5ppm/°C ο [0075] When the power supply voltage Vdd is O. 8V inch, output the reference voltage V, ef with the temperature curve shown in Figure 3, this curve in the second and third NMOS transistor M3 bandit OS and a second PMOS transistor M4 a third PMOS transistor M5 and the transistor M6 are obtained when working subthreshold region, seen in a -40 ° C~80 ° C temperature range, the rate of change of the output reference voltage Vref is extremely small, only 31. 5ppm / ° C ο

[0076] 需要说明的是,本发明实施例ニ的电压源电路中的第二PMOS管M5的沟道宽长比和第三PMOS管M6的沟道宽长比可以相同,也可以不相同,如果第二PMOS管M5的沟道宽长比和第三PMOS管M6的沟道宽长比相同,则第二PMOS管M5的源漏电流和第三PMOS管M6的源漏电流相同,为保证等式(2)成立,需要保证第二NMOS管M3的沟道宽长比和第三NMOS管M4的沟道宽长比不相同;如果第二PMOS管M5的沟道宽长比和第三PMOS管M6的沟道宽长比不相同,则第二PMOS管M5的源漏电流和第三PMOS管M6的源漏电流不相同,等式(2)必然成立,此时对第二NMOS管M3的沟道宽长比和第三NMOS管M4的沟道宽长比没有限制,可见,当第二PMOS管M5的沟道宽长比和第三PMOS管M6的沟道宽长比不相同时,第二NMOS管M3和第三NMOS管M4的沟道宽长比不受限制。 [0076] Incidentally, the same can be longer than the channel width of the second PMOS transistor M5 ni voltage source circuit embodiment of a channel width to length ratio, and the third PMOS transistor M6, and may not be the same embodiment of the present invention, If the channel width to length ratio of the third PMOS transistor and a second PMOS transistor M5 M6 channel width to length ratio of the same, the second PMOS transistor M5 and the source-drain current of the third PMOS transistor M6 is the same as source-drain current, in order to ensure equation (2) holds, it is necessary to ensure that the channel width to length ratio of the second NMOS transistor M3 and NMOS transistor M4, the third channel are not the same width to length ratio; if the second PMOS transistor M5 and the third channel width to length ratio PMOS transistor M6 channel width to length, the source-drain current of the second PMOS transistor M5 and a PMOS transistor M6 of the third source-drain current ratio is not the same as different, equation (2) inevitably established, this time of the second NMOS transistor longer than the channel width of M3 and NMOS transistor M4, the third channel width to length ratio is not limited, and can be seen, when the channel width to length ratio of the channel width to length of the third PMOS transistor and a second PMOS transistor M5 M6 ratio not in Meanwhile, the second NMOS transistor M3 and NMOS transistor M4, the third channel width to length ratio is not limited.

[0077] 与现有技术中温度系数通常高于几百ppm/°C的电压源电路相比,本发明实施例ニ的电压源电路的温度系数可以达到很低的水平,可以满足高精度电路对參考电压源电路的要求。 [0077] The prior art generally higher than the temperature coefficient of the voltage source circuit of several hundred ppm / ° C compared to the temperature coefficient of the voltage source circuit according to embodiments of the present invention, ni can reach a very low level, high-precision circuit can meet required reference voltage source circuit.

[0078] 需要说明的是,与传统的带隙基准电压源电路相比,本发明实施例ニ所提供的输出參考电压Vref并不固定在某一特定值,而是与MOS管的宽长比、阈值电压及补偿电阻的阻值有夫,可以通过合理的电路设计满足不同的输出參考电压要求。 [0078] Note that, as compared with the conventional bandgap voltage reference circuit, the output of the reference voltage Vref provided ni embodiment of the present invention is not fixed to a specific value, but longer than the width of the MOS transistor , resistance and threshold voltage compensation resistor married, the circuit design can be reasonable to meet different requirements of the output voltage reference.

[0079] 当第二NMOS管M3和第三NMOS管M4以及第二PMOS管M5和第三PMOS管M6均エ作在亚阈值区时,本发明实施例ニ的电压源电路可以达到深亚微米エ艺下电路工作的电源电压低于IV的要求,其整体电路功耗可以达到nW级,本发明实施例ニ的电压源电路能够为深亚微米エ艺下的电路提供工作的电源电压,克服了传统带隙基准电压源输出电压高无法为深亚微米エ艺下的电路提供工作的电源电压的缺陷。 Voltage source circuit [0079] When the second and third NMOS transistor M3 and NMOS transistor M4 second PMOS transistor M5 and the third PMOS transistor M6 are made in Ester subthreshold region, ni embodiment of the present invention embodiment can achieve deep sub-micron supply voltage circuit operating at less than the required IV Ester arts, the entire power consumption of the circuit can be achieved nW level, the voltage source circuit according to embodiments of the present invention, Ni is possible to provide the supply voltage for the circuit under deep submicron Ester arts to overcome traditional bandgap reference voltage source the output voltage of the high supply voltage is not available for the circuit at deep submicron defects Ester arts.

[0080] 本发明实施例ニ的电压源电路,仅由MOS管和补偿电阻组成,结构简単,占用芯片的面积小,可以与标准CMOSエ艺兼容,降低了芯片的制造成本;本发明实施例中的第二NMOS管和第三NMOS管可以工作在亚阈值区,能够提供满足深亚微米エ艺下电路工作的低于IV的输出參考电压,与工作在饱和区相比,能够降低电压源电路的整体功耗;此外,通过可以调节MOS管的宽长比以及补偿电阻的阻值来设计β的值来得到ー个温度系数极低甚至接近于零的输出參考电压。 [0080] Example ni voltage source circuit according to the present invention, only the MOS transistor and the compensating resistors, small area simple structure radiolabeling, occupied chip may Ester arts is compatible with the standard the CMOS, reduces the manufacturing cost of the chip; embodiment of the present invention in a second embodiment of the third NMOS transistor and the NMOS transistor can operate in the subthreshold region can be provided to meet the deep submicron Ester arts circuit output voltage is lower than the reference IV compared with in the saturation region, the voltage can be reduced overall power supply circuit; in addition, may be adjusted by the ratio of width to length compensation resistor and the resistance of the MOS transistor is designed to obtain the value of β ー a low temperature coefficient of the reference voltage output even close to zero. 本发明实施例ニ能够提供一种输出參考电压小于IV的低功耗低温度系数电压源电路,此电压源电路满足集成电路设计领域的要求。 Ni embodiment of the present invention can provide a low-power low temperature coefficient of the reference voltage supply circuit for the output voltage is less than the IV, this voltage source circuit to meet the requirements in the field of integrated circuit design.

[0081] 实施例三 [0081] Example three

[0082] 本发明实施例三提供一种电压源电路,如图4所示,为该电压源电路的电路结构示意图。 Embodiment [0082] The three embodiments of the present invention to provide a voltage source circuit, shown in Scheme 4, the voltage source circuit for the circuit configuration of FIG. 该电压源电路包括电流源电路401、參考电压输出级402以及启动电路403,其中,參考电压输出级402包括: The voltage source circuit comprises a current source circuit 401, the reference voltage output stage 402 and a starting circuit 403, wherein the reference voltage output stage 402 comprises:

[0083] 第一NMOS管Ml,源极接地,栅极与漏极相连,节点406构成參考电压输出端; [0083] First of Ml NMOS transistor, a source grounded, a gate connected to a drain, the reference voltage node 406 constituting an output terminal;

[0084] 第一PMOS管M2,源极与电源Vdd相连,栅极与电流源电路的输出端(节点404)相连,漏极与第一NMOS管Ml的漏极相连; [0084] The first PMOS transistor M2, a source connected to power supply Vdd, (node ​​404) connected to the output terminal of the current source circuit of the gate, and a drain connected to the drain of the first NMOS transistor Ml;

[0085] 本发明实施例三的电压源电路中的电流源电路401包括: [0085] The embodiment of the present invention, a current source circuit according to a third voltage source circuit 401 comprises:

[0086] 第二NMOS管M3、第三NMOS管Μ4、第二PMOS管Μ5、第三PMOS管Μ6以及补偿电阻R,其中, [0086] The second NMOS transistor M3, the third NMOS transistor Μ4, a second PMOS transistor Μ5, Μ6 third PMOS transistor and a compensation resistor R, wherein

[0087] 第二NMOS管M3的源极接地,栅极与漏极相连; [0087] The source of the second NMOS transistor M3 is grounded, a gate connected to a drain;

[0088] 第三NMOS管Μ4的源极通过补偿电阻R接地,栅极与第二NMOS管M3的栅极相连; Μ4 source of [0088] the third NMOS transistor is grounded pole compensation resistor R, a gate connected to the gate of the second NMOS transistor M3 through;

[0089] 第二PMOS管Μ5的源极接电源Vdd,漏极与第二NMOS管M3的漏极相连;[0090] 第三PMOS管M6的源极接电源Vdd,栅极与第二PMOS管M5的栅极相连,并构成电流源电路401的输出端404,漏极与第三NMOS管M4的漏极相连,且其栅极与漏极相连; [0089] The source of the second PMOS transistor to the power Μ5 pole Vdd, the drain connected to the drain of the second NMOS transistor M3; [0090] The source of the third PMOS transistor M6 is connected to power supply Vdd, and the gate of the second PMOS transistor the gate of M5 is connected to the current source circuit 401 and constitute the output terminal 404, a drain connected to the drain of the third NMOS transistor M4, and a gate connected to the drain;

[0091] 本发明实施例三的启动电路403包括: [0091] Example embodiments of the present invention, three start-up circuit 403 comprises:

[0092] 第四PMOS管M7,源极与电源Vdd相连,栅极与第二PMOS管M5的漏极相连; [0092] The fourth PMOS transistor M7, a source connected to power supply Vdd, a gate connected to the drain of the second PMOS transistor M5;

[0093] 第四NMOS管M8,源极接地,栅极与第四PMOS管M7的栅极相连,漏极与第四PMOS管M7的漏极相连; [0093] The fourth NMOS transistor M8, a source grounded, and a gate of the fourth PMOS transistor M7 is connected to a gate, a drain connected to the drain of the fourth PMOS transistor M7 is connected;

[0094] 第五NMOS管M9,源极接地,栅极与第四PMOS管M7的漏极相连,漏极与第二PMOS管M5的栅极相连。 [0094] The fifth NMOS transistor M9, a source grounded, a gate connected to the drain of the fourth PMOS transistor M7 and a drain connected to the gate of the second PMOS transistor M5.

[0095] 具体地,第四PMOS管M7和第四NMOS管M8连接成反相器的模式,反相器的输入端连接至第二NMOS管M3的漏扱,反相器的输出端连接至第五NMOS管M9的栅极。 [0095] Specifically, the fourth PMOS transistor M7 and the fourth NMOS transistor M8 is connected to the inverter mode, the input terminal of the inverter is connected to the drain of the second NMOS transistor M3 Qi, the output terminal of the inverter is connected to the gate of the fifth NMOS transistor M9.

[0096] 具体地,当电源电压接通后,若电压源电路工作在电流为零的静态工作点,则该启动电路403工作。 [0096] Specifically, when the supply voltage is turned on, if the voltage source circuit in the quiescent operating point of the current is zero, the circuit 403 starts working. 如图4所示,电压源电路工作在电流为零的静态工作点时,第二PMOS管M5和第三PMOS管M6的集电结均处于反向偏置,发射结没有导通,M5和M6工作在截止区;第二NMOS管M3和第三NMOS管M4的集电结也处于反向偏置,发射结没有导通,也工作在截止区,所以节点404的电平为电源电压,节点405的电平为零,则第四PMOS管M7工作在线性区,即M7的发射结加正向偏压,集电结加反向偏压,M7导通;第四NMOS管M8工作在截止区,即M8的集电结处于反向偏置,发射结没有导通。 4, the voltage supply circuit when the current is zero quiescent operating point, a second PMOS transistor M5 and M6 of the third PMOS transistor are the collector junction is reverse-biased, the emitter junction is not turned on, and M5 M6 operate in cut-off region; a second NMOS transistor M3 and NMOS transistor M4, the third collector junction is reverse-biased also, the emitter junction is not turned on, also work in cut-off region, the level of the node 404 is the supply voltage, level of the node 405 is zero, the fourth PMOS transistor M7 operating in the linear region, i.e., the emitter junction is forward biased M7, the collector junction is reverse biased, M7 is turned on; the fourth NMOS transistor M8 work cutoff region, i.e., the collector junction is reverse-biased M8, the emitter junction is not turned on. 此时,节点407的输出电平为电源电压,从而使第四NMOS-MS导通,并工作在线性区,故而节点404的电平被拉低,然后,电压源电路401恢复至电流非零的稳定工作点。 At this time, the output level of the node 407 to the supply voltage so that the fourth NMOS-MS is turned on, and the linear region, and therefore the level of the node 404 is pulled low, then the voltage source circuit 401 the current returns to zero the stable operating point.

[0097] 需要说明的是,电压源电路401工作在电流非零的稳定工作点后,第四PMOS管M7、第四NMOS管M8和第五NMOS管M9均工作在截止区。 [0097] Incidentally, the voltage source circuit 401 operate in the stable operating point of the current non-zero, the fourth PMOS transistor M7, the fourth NMOS transistor M8 and a fifth NMOS transistor M9 are turned off in the work area. 即:在完成对电压源电路的启动操作后,启动电路403转到截止状态,此时,启动电路403不消耗任何直流功耗;另外,在电源接通以后,如果电压源电路工作在电流非零的静态工作点,则启动电路403不工作。 That is: After completing the start-up operation of the voltage supply circuit, starting circuit 403 to the OFF state, this time, start-up circuit 403 does not consume any DC power consumption; Further, after the power is turned on, if the voltage of the current source circuit in the non- quiescent point zero, the start-up circuit 403 does not work.

[0098] 在这种工作模式下,启动电路403除了在启动电压源电路的过程中消耗一定功耗夕卜,其他过程中不消耗任何直流功耗,因此,该电压源电路整体的直流功耗较低。 [0098] In this mode, the startup circuit 403 in addition to a certain power consumption during the start-Bu Xi voltage source circuit, the other process does not consume any DC power consumption, and therefore, the voltage of the DC power source circuit overall low.

[0099] 需要说明的是,根据设计要求的需要,第四PMOS管M7与第四NMOS管M8的尺寸可以设计为一定的范围,以使节点408的电平高于反相器的阈值电压,从而使节点407输出低电平。 [0099] Incidentally, according to design requirements, the size of the fourth PMOS transistor M7 and the fourth NMOS transistor M8 may be designed in a specific range, so that the level of the node 408 is higher than the threshold voltage of the inverter, so that the node 407 outputs a low level.

[0100] 另外,本发明实施例中的启动电路403还可以采用其他本领域常用的启动电路。 [0100] Further, the present invention, starting circuit 403 in the embodiment may also be other common in the art using starting circuit. [0101 ] 本发明实施例在电压源电路工作在电流为零的静态工作点时采用启动电路启动电压源电路,保证了电压源电路的正常工作;在完成对电压源电路的启动操作后,启动电路转到截止状态,此时,启动电路不消耗任何直流功耗;另外,在电源接通以后,如果电压源电路工作在电流非零的静态工作点,则启动电路不工作。 [0101] Example embodiments of the present invention, the voltage source circuit employed when the current is zero quiescent operating point starting circuit starting voltage source circuit, to ensure the normal operation voltage source circuit; after completion of start-up operation of the voltage source circuit, starting circuit to the oFF state, this time, start-up circuit does not consume any DC power consumption; Further, after the power is turned on, the voltage source circuit if the current non-zero quiescent operating point, the starter circuit does not operate. 可见,启动电路除了在启动电压源电路的过程中消耗一定功耗外,其他过程中不消耗任何直流功耗,可以大大降低电压源电路的整体直流功耗。 Seen, in addition to the starting circuit consumes a certain power source voltage during the starting circuit, the other process does not consume any DC power consumption, can significantly reduce the overall power consumption of the DC voltage source circuit.

[0102] 以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。 [0102] The above are only preferred embodiments of the present invention, it should be noted that those of ordinary skill in the art, in the present invention without departing from the principles of the premise, can make various improvements and modifications, such modifications and modifications should also be regarded as the protection scope of the present invention.

Claims (6)

  1. 1. 一种电压源电路,包括电流源电路和参考电压输出级,其特征在于, 所述电流源电路由MOS管和电阻组成,所述电流源电路与电源相连并接地,用于提供与温度成正比的输出电流; 所述参考电压输出级包括第一PMOS管和第一NMOS管, 所述第一PMOS管的源极与所述电源相连,栅极与电流源电路的输出端相连,漏极与所述第一NMOS管的漏极相连,用于将所述电流源电路输出的所述输出电流镜像; 所述第一NMOS管的源极接地,栅极与漏极相连,用于将所述镜像后的所述输出电流转换成输出电压。 A voltage source circuit comprising a current source circuit and a reference voltage output stages, characterized in that the current source circuit is composed of a MOS transistor and a resistor, said current source circuit is connected to a power supply and a ground, for providing a temperature proportional to the output current; the reference voltage output stage includes a first PMOS transistor and a first NMOS transistor, the source of the first PMOS transistor is connected to the power supply, a gate connected to the output terminal of the current source circuit, a drain and the drain electrode of said first NMOS transistor is connected to the output of said current mirror circuit output current source; source of the first NMOS transistor is grounded, a gate connected to the drain, for the output of the current mirror is converted into the output voltage.
  2. 2.根据权利要求I所述的电压源电路,其特征在于,所述电流源电路包括第二NMOS管、第三NMOS管、第二PMOS管、第三PMOS管以及补偿电阻,其中, 所述第二NMOS管的源极接地,栅极与漏极相连; 所述第三NMOS管的源极通过所述补偿电阻接地,栅极与所述第二NMOS管的栅极相连; 所述第二PMOS管的源极接所述电源,漏极与所述第二匪OS管的漏极相连; 所述第三PMOS管的源极接所述电源,栅极与所述第二PMOS管的栅极相连,并构成所述电流源电路的输出端,漏极与所述第三NMOS管的漏极相连,且栅极与漏极相连。 The voltage source circuit according to claim I, wherein said current source circuit includes a second NMOS transistor, the third NMOS transistor, a second PMOS transistor, the third PMOS transistor and a compensation resistor, wherein said source of the second NMOS transistor is grounded, a gate connected to the drain electrode; a source electrode of said third NMOS transistor is grounded through a compensating resistor, a gate connected to the gate of the second NMOS transistor; the second source of the PMOS transistor is connected to the power supply, a drain connected to the drain of the second OS bandit tube; the source of the third PMOS transistor is connected to the power source, a gate and a gate of the second PMOS transistor pole is connected, and constitutes the output terminal of the current source circuit, the drain of the third NMOS transistor is connected to the drain and gate connected.
  3. 3.根据权利要求2所述的电压源电路,其特征在于,所述电压源电路还包括启动电路,所述启动电路包括: 第四PMOS管,源极与所述电源相连,栅极与所述第二PMOS管的漏极相连; 第四NMOS管,源极接地,栅极与所述第四PMOS管的栅极相连,漏极与所述第四PMOS管的漏极相连; 第五NMOS管,源极接地,栅极与所述第四PMOS管的漏极相连,漏极与所述第二PMOS管的栅极相连。 The voltage source circuit according to claim 2, wherein said circuit further comprises a starting voltage source circuit, said starting circuit comprises: a fourth PMOS transistor is connected, the power source, and the gate said drain of the second PMOS transistor is connected; a fourth NMOS transistor, a source grounded, a gate connected to the gate of the fourth PMOS transistor, a drain connected to the drain of the fourth PMOS transistor; the fifth NMOS tube, a source grounded, a gate connected to the drain of the fourth PMOS transistor, a drain connected to a gate of the second PMOS transistor.
  4. 4.根据权利要求2或3所述的电压源电路,其特征在于,所述第二 PMOS管的沟道宽长比与所述第三PMOS管的沟道宽长比不相同。 The voltage source circuit of claim 2 or claim 3, wherein channel width to length of the second PMOS transistor are not the same as the ratio of the third PMOS transistor channel width to length ratio.
  5. 5.根据权利要求2或3所述的电压源电路,其特征在于,所述第二 NMOS管和第三NMOS管工作在亚阈值区。 The voltage source circuit of claim 2 or claim 3, wherein said second NMOS transistor and the third NMOS transistor working in the subthreshold region.
  6. 6.根据权利要求5所述的电压源电路,其特征在于,所述第二 PMOS管和第三PMOS管工作在亚阈值区。 The voltage source circuit according to claim 5, characterized in that said second PMOS transistor and the third PMOS transistor working in the subthreshold region.
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