CN102662427A - Voltage source circuit - Google Patents
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- CN102662427A CN102662427A CN2012101672505A CN201210167250A CN102662427A CN 102662427 A CN102662427 A CN 102662427A CN 2012101672505 A CN2012101672505 A CN 2012101672505A CN 201210167250 A CN201210167250 A CN 201210167250A CN 102662427 A CN102662427 A CN 102662427A
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Abstract
The embodiment of the invention provides a voltage source circuit, which comprises a current source circuit and a reference voltage output stage, wherein the reference voltage output stage comprises: the source electrode of the first NMOS tube is grounded, and the grid electrode of the first NMOS tube is connected with the drain electrode; the source electrode of the first PMOS tube is connected with a power supply, the grid electrode of the first PMOS tube is connected with the output end of the current source circuit, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube; the current source circuit is composed of an MOS tube and a resistor. The voltage source circuit in the embodiment of the invention only uses the MOS tube and the resistor, does not need a bipolar transistor and other transistors, has simple structure, small occupied area of a chip and low manufacturing cost, can be used in a standard CMOS process compatible with a digital circuit, and improves the compatibility of an analog circuit and the digital circuit.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a voltage source circuit.
Background
The voltage source circuit is one of the most important basic circuits in the integrated circuit system, and provides necessary bias voltage for the normal operation of other modules in the chip, so that the performance of the voltage source circuit greatly influences the overall performance of the chip. With the development of microelectronic manufacturing technology and the dramatic increase in consumer markets such as personal portable devices, wireless receivers, etc., the design challenges posed to voltage source circuits are also increasing.
However, most of the voltage source circuits widely applied at present are derived from bipolar band gap references, such voltage source circuits need bipolar transistors with higher performance, have large occupied area and high manufacturing cost, some of the voltage source circuits even need to be realized under a BiCMOS or bipolar process, cannot be compatible with a standard CMOS process, and cannot meet the design requirements of integrated circuits under a deep submicron process.
Disclosure of Invention
In view of the above, the present invention is directed to a voltage source circuit compatible with a CMOS process, so as to solve the problem of incompatibility between the voltage source circuit and the CMOS process in the prior art.
Therefore, the technical scheme of the invention provides a voltage source circuit compatible with a CMOS (complementary metal oxide semiconductor) process, which comprises a current source circuit and a reference voltage output stage, wherein the current source circuit consists of an MOS (metal oxide semiconductor) tube and a resistor, is connected with a power supply and is grounded and is used for providing an output current in direct proportion to the temperature;
the reference voltage output stage comprises a first PMOS tube and a first NMOS tube,
the source electrode of the first PMOS tube is connected with the power supply, the grid electrode of the first PMOS tube is connected with the output end of the current source circuit, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and is used for mirroring the output current output by the current source circuit;
and the source electrode of the first NMOS tube is grounded, and the grid electrode of the first NMOS tube is connected with the drain electrode of the first NMOS tube and is used for converting the output current after mirroring into output voltage.
Preferably, the current source circuit includes a second NMOS transistor, a third NMOS transistor, a second PMOS transistor, a third PMOS transistor, and a compensation resistor, wherein,
the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is connected with the drain electrode;
the source electrode of the third NMOS tube is grounded through the compensation resistor, and the grid electrode of the third NMOS tube is connected with the grid electrode of the second NMOS tube;
the source electrode of the second PMOS tube is connected with the power supply, and the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube;
and the source electrode of the third PMOS tube is connected with the power supply, the grid electrode of the third PMOS tube is connected with the grid electrode of the second PMOS tube and forms the output end of the current source circuit, the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube, and the grid electrode of the third PMOS tube is connected with the drain electrode of the second PMOS tube.
Preferably, the voltage source circuit further comprises a start-up circuit comprising:
a source electrode of the fourth PMOS tube is connected with the power supply, and a grid electrode of the fourth PMOS tube is connected with a drain electrode of the second PMOS tube;
a source electrode of the fourth NMOS tube is grounded, a grid electrode of the fourth NMOS tube is connected with a grid electrode of the fourth PMOS tube, and a drain electrode of the fourth NMOS tube is connected with a drain electrode of the fourth PMOS tube;
and the source electrode of the fifth NMOS tube is grounded, the grid electrode of the fifth NMOS tube is connected with the drain electrode of the fourth PMOS tube, and the drain electrode of the fifth NMOS tube is connected with the grid electrode of the second PMOS tube.
Preferably, the channel width-length ratio of the second PMOS transistor is different from the channel width-length ratio of the third PMOS transistor.
Preferably, the second NMOS transistor and the third NMOS transistor operate in the sub-threshold region.
Preferably, the second PMOS tube and the third PMOS tube work in a subthreshold region.
The voltage source circuit in the embodiment of the invention only uses the MOS tube and the resistor, does not need a bipolar transistor and other transistors, has simple structure, small occupied area of a chip and low manufacturing cost, can be used in a standard CMOS process compatible with a digital circuit, and improves the compatibility of an analog circuit and the digital circuit.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a circuit configuration diagram of a voltage source circuit according to a first embodiment of the invention;
FIG. 2 is a circuit diagram of a voltage source circuit according to a second embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a variation curve of a reference voltage of a voltage source circuit with temperature according to a second embodiment of the present invention;
fig. 4 is a circuit configuration diagram of a voltage source circuit according to a third embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the prior art, a traditional voltage source circuit consists of an MOS (metal oxide semiconductor) tube, an operational amplifier, a triode and the like, and has a complex circuit structure, large occupied chip area and high manufacturing cost; moreover, the conventional voltage source circuit cannot be compatible with the CMOS standard process, and in the process of continuous development of the deep submicron process, it is necessary to improve the compatibility between the analog circuit and the digital circuit. The embodiment of the invention aims to provide a voltage source circuit which can be compatible with a CMOS standard process so as to improve the compatibility of an analog circuit and a digital circuit and meet the requirements of deep submicron process technology.
Example one
Fig. 1 is a circuit structure diagram of a voltage source circuit according to a first embodiment of the present invention. The voltage source circuit comprises a current source circuit 101 and a reference voltage output stage 102, wherein the current source circuit 101 consists of an MOS (metal oxide semiconductor) transistor and a resistor, the current source circuit 101 is connected with a power supply Vdd and grounded, and the current source circuit 101 is used for providing an output current which is in direct proportion to the temperature;
the reference voltage output stage 102 includes:
a first PMOS transistor M2, having a source connected to a power supply Vdd, a gate connected to the output terminal of the current source circuit, and a drain connected to the drain of the first NMOS transistor M1, for mirroring the output current outputted by the current source circuit 101;
the source of the first NMOS transistor M1 is grounded, and the gate is connected to the drain, for converting the mirrored output current of the first PMOS transistor M2 into an output voltage.
As can be seen from FIG. 1, the first NMOS transistor M1 and the first PMOS transistor M2 are connected in the form of a diode with a reference voltage VrefMay be output by node 103.
It should be noted that the current source circuit in the first embodiment of the present invention may be any current source circuit in the prior art, which is only composed of a MOS transistor and a resistor, and whose output current is proportional to temperature; the current source circuit 101 may include MOS transistors connected in a cascode current mirror form, where the cascode MOS transistors function as a current mirror to ensure that currents of the branches of the current source circuit are equal or in a certain proportion. Wherein, the gate of the first PMOS transistor M2 may be connected to the common gate of the current mirror.
If the operational amplifier is used in the current source circuit, the structure of the voltage source circuit is complex, and simultaneously, the large power consumption is consumed, so that the requirement of simple structure of an integrated circuit cannot be met; in addition, some current source circuits use triodes, but high-performance triodes cannot be manufactured in a standard CMOS (complementary metal oxide semiconductor) process compatible with a digital circuit, so that a plurality of high-performance current sources need to be realized in a BiCMOS (bipolar complementary metal oxide semiconductor) process, the manufacturing cost of a chip is greatly improved, and the compatibility of an analog circuit and the digital circuit is reduced. However, the voltage source circuit of the first embodiment of the invention only uses the MOS transistor and the resistor, so that the voltage source circuit has a simple structure and occupies a small chip area; meanwhile, the manufacturing cost of the chip is reduced, and the compatibility of the analog circuit and the digital circuit is improved.
Example two
A second embodiment of the invention provides a voltage source circuit, as shown in fig. 2, which is a circuit structure diagram of the voltage source circuit according to the second embodiment of the invention. The voltage source circuit comprises a current source circuit 201 and a reference voltage output stage 202, wherein the reference voltage output stage 202 comprises:
the source electrode of the first NMOS tube M1 is grounded, and the grid electrode of the first NMOS tube M1 is connected with the drain electrode;
a first PMOS transistor M2, having a source connected to a power supply Vdd, a gate connected to the output terminal (node 203) of the current source circuit, and a drain connected to the drain of the first NMOS transistor M1;
the current source circuit 201 in the voltage source circuit according to the second embodiment of the present invention includes:
a second NMOS transistor M3, a third NMOS transistor M4, a second PMOS transistor M5, a third PMOS transistor M6, and a compensation resistor R, wherein,
the source electrode of the second NMOS tube M3 is grounded, and the grid electrode is connected with the drain electrode;
the source electrode of the third NMOS tube M4 is grounded through a compensation resistor R, and the grid electrode of the third NMOS tube M4 is connected with the grid electrode of the second NMOS tube M3;
the source electrode of the second PMOS tube M5 is connected with a power supply Vdd, and the drain electrode of the second PMOS tube M3 is connected with the drain electrode of the second NMOS tube M3;
the source of the third PMOS transistor M6 is connected to the power supply Vdd, the gate is connected to the gate of the second PMOS transistor M5 and constitutes the output terminal 203 of the current source circuit 201, the drain is connected to the drain of the third NMOS transistor M4, and the gate is connected to the drain.
In particular, the compensation resistor R may be a variable resistor, such as a varistor, or a fixed resistor.
Specifically, the second NMOS transistor M3 and the third NMOS transistor M4 may operate in a saturation region and may also operate in a sub-threshold region. The second NMOS transistor M3 and the third NMOS transistor M4 may form a voltage source circuit when operating in a saturation region, and the voltage source circuit may be compatible with a CMOS process; when the second NMOS transistor M3 and the third NMOS transistor M4 work in the sub-threshold region, the voltage source circuit can be compatible with a CMOS (complementary metal oxide semiconductor) process, can also work at a power supply voltage below 1V, and has the characteristics of low temperature coefficient and low power consumption.
It should be noted that the second PMOS transistor M5 and the third PMOS transistor M6 in the second embodiment of the present invention may work in the same working region, for example, both may work in a saturation region or a sub-threshold region, so as to ensure that the ratio of the source-drain current of the second PMOS transistor M5 to the source-drain current of the third PMOS transistor M6 is the same as the ratio of the channel size, so as to form a relationship of a current mirror in the saturation region or the sub-threshold region.
It should be noted that, for the voltage source circuit structure of the second embodiment of the present invention, an output reference voltage V with an extremely low temperature coefficient or even close to zero can be obtained by adjusting the width-to-length ratio of the MOS transistor and the resistance of the compensation resistorref. The temperature coefficient value of the voltage source circuit is detailed by specific formula derivation.
When the second NMOS transistor M3 and the third NMOS transistor M4 work in the subthreshold region, the source-drain current I of the second NMOS transistor M3DSCan be expressed as:
wherein, munIs the mobility, C, of the second NMOS transistor M3oxIs the gate oxide capacitance per unit area of the second NMOS transistor M3, (W/L) is the channel width-to-length ratio of the second NMOS transistor M3, VTIs the thermoelectric potential kT/q of the second NMOS tube (M3), K is Boltzmann constant, i.e. K =1.3806505 x 10-23J/K, T is absolute temperature, q is the elementary charge capacity, i.e. q =1.6 x 10-19 coulomb, VGSIs the gate-source voltage difference, V, of the second NMOS transistor M3THIs the threshold voltage of the second NMOS transistor M3.
In accordance with kirchhoff's voltage law, the following equation may be listed for node 205:
VGS3=VGS4+IDSR……………………………………………………………（2）
wherein, VGS3Is the gate-source voltage difference, V, of the second NMOS transistor M3GS4The voltage difference between the gate and the source of the third NMOS transistor M4, and R is the resistance of the compensation resistor.
Substituting equation (1) into equation (2) and assuming that the threshold voltages of the second NMOS transistor M3 and the third NMOS transistor M4 are equal, we can obtain:
wherein, the ratio of width to length of the second PMOS transistor M5, the third PMOS transistor M6 and the first PMOS transistor M2 is 1: M: N, and the currents flowing through them are IDS，MIDS，NIDS。
As can be seen from equation (3), the second NMOS transistor M3 and the third NMOS transistor M4 operate in the subthreshold region, so that the bias current determined by the second NMOS transistor M3 and the third NMOS transistor M4 and the compensation resistor R is a current strictly proportional to the temperature, and the current source circuit 201 can operate at a very low power voltage, such as several hundred millivolts.
The working region of the first NMOS transistor M1 in the reference voltage output stage 202 in FIG. 2 is defined by the output reference voltage VrefAnd (6) determining. If the reference voltage V is outputrefIf the voltage is lower than the threshold voltage of the NMOS transistor, the first NMOS transistor M1 works in a sub-threshold region; if the reference voltage V is outputrefAbove the threshold voltage of the NMOS transistor, the first NMOS transistor M1 can operate in the adjacent sub-threshold region or even the saturation region.
If the source-drain current of the second NMOS transistor M3 is
The source-drain current of the second PMOS transistor M5 is also
Further, the source-drain current of the first PMOS tube M2 can be obtainedThe source-drain current of the first NMOS transistor M1 is also
According to the formula (1), the following can be obtained:
wherein,
is a temperature-independent proportionality coefficient, thermoelectric potential VTIs proportional to the temperature, and the threshold voltage V of the first NMOS transistor M1TH1And mobility munHave negative temperature coefficients, which can be expressed as:
VTH1(T)=VTH1(T0)-α×(T-T0)………………………………………………（5）
wherein, T0Is a room temperature reference temperature, - α is a temperature coefficient of the threshold voltage of the first NMOS transistor M1, which is negative in most processes. VTH1(T) is the threshold voltage of the first NMOS transistor M1 at the temperature T; gamma is the temperature coefficient of the mobility of the first NMOS transistor M1, and is generally about-1.5, munAnd (T) is the mobility of the NMOS tube at the temperature T.
By differentiating the temperature at both ends of equation (4), the reference voltage V can be obtainedrefFirst order temperature coefficient of (1):
let equation (7) equal zero, then one can get:
because of the fact that
Therefore, the value of β is related to the channel width-length ratio of the MOS transistor, the width-length ratio of the second PMOS transistor M5, the third PMOS transistor M6, and the first PMOS transistor M2, the resistance of the compensation resistor R, the gate oxide capacitance per unit area of the MOS transistor, and the like.Therefore, the value of beta can be designed by adjusting the width-length ratio of the MOS tube and the resistance value of the compensation resistor to obtain an output reference voltage V with extremely low temperature coefficient and even close to zeroref。
It can be seen that the negative temperature coefficient of the mobility of the first NMOS transistor M1, the negative temperature coefficient of the threshold voltage of the first NMOS transistor M1, and the positive temperature coefficient of the thermoelectric voltage kT/q of the first NMOS transistor M1 can be utilized to make the gate-source voltage difference of the first NMOS transistor M1, i.e. the output reference voltage VrefHas a zero temperature coefficient.
It should be noted that the second PMOS transistor M5 and the third PMOS transistor M6 in the second embodiment of the present invention may operate in a saturation region or a sub-threshold region. When the second PMOS transistor M5 and the third PMOS transistor M6 can work in a saturation region, the second PMOS transistor M5 and the third PMOS transistor M6 are connected to form a saturation current mirror, and the voltage source circuit of the second embodiment of the invention can still work at a lower power voltage; the second PMOS transistor M5 and the third PMOS transistor M6 can operate in the sub-threshold region, and the second PMOS transistor M5 and the third PMOS transistor M6 are connected to form a sub-threshold current mirror, so that the supply voltage required by the operation of the voltage source circuit according to the second embodiment of the present invention can be further reduced, and the power consumption of the voltage source circuit can be further reduced.
When the power supply voltage Vdd is 0.8V, the reference voltage V is outputrefThe curve of the variation with temperature is shown in fig. 3, which is obtained when the second NMOS transistor M3 and the third NMOS transistor M4 and the second PMOS transistor M5 and the third PMOS transistor M6 all work in the subthreshold region, and it can be seen that the reference voltage V is output within the temperature range of-40 ℃ to 80 ℃refThe rate of change of (A) was extremely small, only 31.5 ppm/DEG C.
It should be noted that, in the voltage source circuit of the second embodiment of the present invention, the channel width-length ratio of the second PMOS transistor M5 and the channel width-length ratio of the third PMOS transistor M6 may be the same or different, and if the channel width-length ratio of the second PMOS transistor M5 and the channel width-length ratio of the third PMOS transistor M6 are the same, the source-drain current of the second PMOS transistor M5 and the source-drain current of the third PMOS transistor M6 are the same, and in order to ensure that equation (2) is satisfied, it is necessary to ensure that the channel width-length ratio of the second NMOS transistor M3 is different from the channel width-length ratio of the third NMOS transistor M4; if the channel width-length ratio of the second PMOS transistor M5 is different from the channel width-length ratio of the third PMOS transistor M6, the source-drain current of the second PMOS transistor M5 is different from the source-drain current of the third PMOS transistor M6, and equation (2) is necessarily satisfied, at this time, there is no limitation on the channel width-length ratio of the second NMOS transistor M3 and the channel width-length ratio of the third NMOS transistor M4, and it can be seen that, when the channel width-length ratio of the second PMOS transistor M5 is different from the channel width-length ratio of the third PMOS transistor M6, the channel width-length ratios of the second NMOS transistor M3 and the third NMOS transistor M4 are not limited.
Compared with the voltage source circuit in the prior art, the temperature coefficient of which is usually higher than hundreds of ppm/DEG C, the temperature coefficient of the voltage source circuit in the second embodiment of the invention can reach a very low level, and the requirement of a high-precision circuit on a reference voltage source circuit can be met.
It should be noted that, compared with the conventional bandgap reference voltage source circuit, the output reference voltage V provided by the second embodiment of the present inventionrefThe output reference voltage is not fixed at a certain specific value, but is related to the width-length ratio of the MOS tube, the threshold voltage and the resistance value of the compensation resistor, and different output reference voltage requirements can be met through reasonable circuit design.
When the second NMOS transistor M3 and the third NMOS transistor M4, and the second PMOS transistor M5 and the third PMOS transistor M6 all operate in the sub-threshold region, the voltage source circuit of the second embodiment of the present invention can meet the requirement that the power voltage of the circuit operating in the deep sub-micron process is lower than 1V, and the power consumption of the whole circuit can reach nW level.
The voltage source circuit of the second embodiment of the invention only consists of the MOS tube and the compensation resistor, has simple structure and small occupied area of the chip, can be compatible with a standard CMOS process, and reduces the manufacturing cost of the chip; the second NMOS tube and the third NMOS tube in the embodiment of the invention can work in a sub-threshold region, can provide output reference voltage lower than 1V which meets the circuit work in a deep submicron process, and can reduce the whole power consumption of a voltage source circuit compared with the power consumption when the second NMOS tube and the third NMOS tube work in a saturation region; in addition, the value of beta can be designed by adjusting the width-length ratio of the MOS tube and the resistance value of the compensation resistor, so that an output reference voltage with extremely low temperature coefficient and even close to zero can be obtained. The second embodiment of the invention can provide a low-power-consumption low-temperature coefficient voltage source circuit with an output reference voltage smaller than 1V, and the voltage source circuit meets the requirements of the field of integrated circuit design.
EXAMPLE III
A third embodiment of the invention provides a voltage source circuit, as shown in fig. 4, which is a schematic circuit structure diagram of the voltage source circuit. The voltage source circuit comprises a current source circuit 401, a reference voltage output stage 402 and a start-up circuit 403, wherein the reference voltage output stage 402 comprises:
a first NMOS transistor M1, the source is grounded, the gate is connected to the drain, and the node 406 forms a reference voltage output terminal;
a first PMOS transistor M2, having a source connected to a power supply Vdd, a gate connected to the output terminal (node 404) of the current source circuit, and a drain connected to the drain of the first NMOS transistor M1;
the current source circuit 401 in the voltage source circuit according to the third embodiment of the present invention includes:
a second NMOS transistor M3, a third NMOS transistor M4, a second PMOS transistor M5, a third PMOS transistor M6, and a compensation resistor R, wherein,
the source electrode of the second NMOS tube M3 is grounded, and the grid electrode is connected with the drain electrode;
the source electrode of the third NMOS tube M4 is grounded through a compensation resistor R, and the grid electrode of the third NMOS tube M4 is connected with the grid electrode of the second NMOS tube M3;
the source electrode of the second PMOS tube M5 is connected with a power supply Vdd, and the drain electrode of the second PMOS tube M3 is connected with the drain electrode of the second NMOS tube M3;
the source electrode of the third PMOS transistor M6 is connected to the power supply Vdd, the gate electrode is connected to the gate electrode of the second PMOS transistor M5 and constitutes the output terminal 404 of the current source circuit 401, the drain electrode is connected to the drain electrode of the third NMOS transistor M4, and the gate electrode is connected to the drain electrode;
the start circuit 403 of the third embodiment of the present invention includes:
a fourth PMOS transistor M7, the source is connected with the power supply Vdd, and the grid is connected with the drain of the second PMOS transistor M5;
a source electrode of the fourth NMOS transistor M8 is grounded, a grid electrode of the fourth NMOS transistor M7 is connected with the grid electrode of the fourth PMOS transistor M7, and a drain electrode of the fourth NMOS transistor M7 is connected with the drain electrode of the fourth PMOS transistor M7;
and the source electrode of the fifth NMOS transistor M9 is grounded, the grid electrode of the fifth NMOS transistor M9 is connected with the drain electrode of the fourth PMOS transistor M7, and the drain electrode of the fifth NMOS transistor M9 is connected with the grid electrode of the second PMOS transistor M5.
Specifically, the fourth PMOS transistor M7 and the fourth NMOS transistor M8 are connected in an inverter mode, an input terminal of the inverter is connected to the drain of the second NMOS transistor M3, and an output terminal of the inverter is connected to the gate of the fifth NMOS transistor M9.
Specifically, when the power supply voltage is turned on, the start-up circuit 403 operates if the voltage source circuit operates at a static operating point where the current is zero. As shown in fig. 4, when the voltage source circuit operates at a static operating point where the current is zero, the collector junctions of the second PMOS transistor M5 and the third PMOS transistor M6 are both under reverse bias, the emitter junction is not turned on, and M5 and M6 operate in the cut-off region; the collector junctions of the second NMOS transistor M3 and the third NMOS transistor M4 are also under reverse bias, the emitter junction is not turned on, and also operates in the cut-off region, so the level of the node 404 is the power voltage, the level of the node 405 is zero, the fourth PMOS transistor M7 operates in the linear region, that is, the emitter junction of the transistor M7 is applied with forward bias, the collector junction is applied with reverse bias, and the transistor M7 is turned on; the fourth NMOS transistor M8 operates in the off region, i.e., the collector junction of M8 is in reverse bias and the emitter junction is not turned on. At this time, the output level of the node 407 is the power supply voltage, so that the fourth NMOS transistor M8 is turned on and operates in the linear region, and therefore the level of the node 404 is pulled low, and then the voltage source circuit 401 returns to the stable operating point where the current is non-zero.
It should be noted that, after the voltage source circuit 401 operates at a stable operating point where the current is non-zero, the fourth PMOS transistor M7, the fourth NMOS transistor M8, and the fifth NMOS transistor M9 all operate in the cut-off region. Namely: after the start-up operation of the voltage source circuit is completed, the start-up circuit 403 turns to a cut-off state, at which time, the start-up circuit 403 does not consume any dc power consumption; in addition, after the power is turned on, if the voltage source circuit operates at a quiescent operating point where the current is non-zero, the start-up circuit 403 does not operate.
In this operation mode, the start-up circuit 403 consumes no dc power consumption in other processes except for a certain power consumption in the process of starting up the voltage source circuit, and therefore, the dc power consumption of the entire voltage source circuit is low.
It should be noted that, according to the design requirement, the sizes of the fourth PMOS transistor M7 and the fourth NMOS transistor M8 may be designed to be in a certain range, so that the level of the node 408 is higher than the threshold voltage of the inverter, and the node 407 outputs a low level.
In addition, the start-up circuit 403 in the embodiment of the present invention may also adopt other start-up circuits commonly used in the art.
According to the embodiment of the invention, when the voltage source circuit works at the static working point with zero current, the starting circuit is adopted to start the voltage source circuit, so that the normal work of the voltage source circuit is ensured; after the starting operation of the voltage source circuit is finished, the starting circuit is switched to a cut-off state, and at the moment, the starting circuit does not consume any direct current power consumption; in addition, after the power is switched on, if the voltage source circuit operates at a static operating point where the current is non-zero, the start-up circuit does not operate. Therefore, the starting circuit consumes certain power consumption in the process of starting the voltage source circuit, and does not consume any direct current power consumption in other processes, so that the overall direct current power consumption of the voltage source circuit can be greatly reduced.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (6)
1. A voltage source circuit comprising a current source circuit and a reference voltage output stage,
the current source circuit is connected with the power supply and is grounded and used for providing an output current in direct proportion to the temperature;
the reference voltage output stage comprises a first PMOS tube and a first NMOS tube,
the source electrode of the first PMOS tube is connected with the power supply, the grid electrode of the first PMOS tube is connected with the output end of the current source circuit, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and is used for mirroring the output current output by the current source circuit;
and the source electrode of the first NMOS tube is grounded, and the grid electrode of the first NMOS tube is connected with the drain electrode of the first NMOS tube and is used for converting the output current after the mirror image into output voltage.
2. The voltage source circuit of claim 1, wherein the current source circuit comprises a second NMOS transistor, a third NMOS transistor, a second PMOS transistor, a third PMOS transistor, and a compensation resistor, wherein,
the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is connected with the drain electrode;
the source electrode of the third NMOS tube is grounded through the compensation resistor, and the grid electrode of the third NMOS tube is connected with the grid electrode of the second NMOS tube;
the source electrode of the second PMOS tube is connected with the power supply, and the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube;
and the source electrode of the third PMOS tube is connected with the power supply, the grid electrode of the third PMOS tube is connected with the grid electrode of the second PMOS tube and forms the output end of the current source circuit, the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube, and the grid electrode of the third PMOS tube is connected with the drain electrode of the second PMOS tube.
3. The voltage source circuit of claim 2, further comprising a startup circuit comprising:
a source electrode of the fourth PMOS tube is connected with the power supply, and a grid electrode of the fourth PMOS tube is connected with a drain electrode of the second PMOS tube;
a source electrode of the fourth NMOS tube is grounded, a grid electrode of the fourth NMOS tube is connected with a grid electrode of the fourth PMOS tube, and a drain electrode of the fourth NMOS tube is connected with a drain electrode of the fourth PMOS tube;
and the source electrode of the fifth NMOS tube is grounded, the grid electrode of the fifth NMOS tube is connected with the drain electrode of the fourth PMOS tube, and the drain electrode of the fifth NMOS tube is connected with the grid electrode of the second PMOS tube.
4. The voltage source circuit of claim 2 or 3, wherein the channel width-to-length ratio of the second PMOS transistor is different from the channel width-to-length ratio of the third PMOS transistor.
5. The voltage source circuit of claim 2 or 3, wherein the second NMOS transistor and the third NMOS transistor operate in a sub-threshold region.
6. The voltage source circuit of claim 5, wherein the second and third PMOS transistors operate in a sub-threshold region.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102981550A (en) * | 2012-11-27 | 2013-03-20 | 中国科学院微电子研究所 | Low-voltage low-power-consumption CMOS voltage source |
| CN103001493A (en) * | 2012-11-02 | 2013-03-27 | 长沙景嘉微电子股份有限公司 | Simple linear power source circuit |
| CN105786081A (en) * | 2016-03-30 | 2016-07-20 | 上海华虹宏力半导体制造有限公司 | Reference voltage source circuit |
| CN110308757A (en) * | 2019-05-22 | 2019-10-08 | 长沙景美集成电路设计有限公司 | A kind of low-power consumption low supply voltage reference circuit |
| CN111506143A (en) * | 2020-04-02 | 2020-08-07 | 上海华虹宏力半导体制造有限公司 | Current source circuit |
| CN113885639A (en) * | 2021-09-28 | 2022-01-04 | 深圳市爱协生科技有限公司 | Reference circuit, integrated circuit, and electronic device |
| CN115112941A (en) * | 2022-08-24 | 2022-09-27 | 芯昇科技有限公司 | Voltage detection circuit |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2788843B2 (en) * | 1992-09-03 | 1998-08-20 | 日鉄セミコンダクター株式会社 | Reference voltage generator |
| CN101149628A (en) * | 2007-10-30 | 2008-03-26 | 东南大学 | Reference voltage source circuit |
| CN101169671A (en) * | 2006-10-24 | 2008-04-30 | 松下电器产业株式会社 | Reference voltage generation circuit |
| CN101216717A (en) * | 2007-12-28 | 2008-07-09 | 络达科技股份有限公司 | Reference voltage circuit |
| CN101763137A (en) * | 2009-12-31 | 2010-06-30 | 华亚微电子（上海）有限公司 | Current generating circuit |
| US20110127989A1 (en) * | 2009-12-01 | 2011-06-02 | Tomoki Hikichi | Constant current circuit |
| CN102176185A (en) * | 2011-01-24 | 2011-09-07 | 浙江大学 | Sub-threshold CMOS (complementary metal-oxide-semiconductor transistor) reference source |
-
2012
- 2012-05-25 CN CN2012101672505A patent/CN102662427A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2788843B2 (en) * | 1992-09-03 | 1998-08-20 | 日鉄セミコンダクター株式会社 | Reference voltage generator |
| CN101169671A (en) * | 2006-10-24 | 2008-04-30 | 松下电器产业株式会社 | Reference voltage generation circuit |
| CN101149628A (en) * | 2007-10-30 | 2008-03-26 | 东南大学 | Reference voltage source circuit |
| CN101216717A (en) * | 2007-12-28 | 2008-07-09 | 络达科技股份有限公司 | Reference voltage circuit |
| US20110127989A1 (en) * | 2009-12-01 | 2011-06-02 | Tomoki Hikichi | Constant current circuit |
| CN101763137A (en) * | 2009-12-31 | 2010-06-30 | 华亚微电子（上海）有限公司 | Current generating circuit |
| CN102176185A (en) * | 2011-01-24 | 2011-09-07 | 浙江大学 | Sub-threshold CMOS (complementary metal-oxide-semiconductor transistor) reference source |
Non-Patent Citations (1)
| Title |
|---|
| 汪宁等: "一种具有高电源抑制比的低功耗CMOS带隙基准电压源", 《微电子学》 * |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103001493A (en) * | 2012-11-02 | 2013-03-27 | 长沙景嘉微电子股份有限公司 | Simple linear power source circuit |
| CN103001493B (en) * | 2012-11-02 | 2014-08-13 | 长沙景嘉微电子股份有限公司 | Simple linear power source circuit |
| CN102981550A (en) * | 2012-11-27 | 2013-03-20 | 中国科学院微电子研究所 | Low-voltage low-power-consumption CMOS voltage source |
| CN105786081A (en) * | 2016-03-30 | 2016-07-20 | 上海华虹宏力半导体制造有限公司 | Reference voltage source circuit |
| CN105786081B (en) * | 2016-03-30 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | Reference voltage source circuit |
| CN110308757A (en) * | 2019-05-22 | 2019-10-08 | 长沙景美集成电路设计有限公司 | A kind of low-power consumption low supply voltage reference circuit |
| CN111506143A (en) * | 2020-04-02 | 2020-08-07 | 上海华虹宏力半导体制造有限公司 | Current source circuit |
| CN111506143B (en) * | 2020-04-02 | 2022-03-08 | 上海华虹宏力半导体制造有限公司 | Current source circuit |
| CN113885639A (en) * | 2021-09-28 | 2022-01-04 | 深圳市爱协生科技有限公司 | Reference circuit, integrated circuit, and electronic device |
| CN115112941A (en) * | 2022-08-24 | 2022-09-27 | 芯昇科技有限公司 | Voltage detection circuit |
| CN115112941B (en) * | 2022-08-24 | 2023-01-03 | 芯昇科技有限公司 | Voltage detection circuit |
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Application publication date: 20120912 |