CN105786081B - Reference voltage source circuit - Google Patents

Reference voltage source circuit Download PDF

Info

Publication number
CN105786081B
CN105786081B CN201610191832.5A CN201610191832A CN105786081B CN 105786081 B CN105786081 B CN 105786081B CN 201610191832 A CN201610191832 A CN 201610191832A CN 105786081 B CN105786081 B CN 105786081B
Authority
CN
China
Prior art keywords
nmos tube
source voltage
gate source
current path
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201610191832.5A
Other languages
Chinese (zh)
Other versions
CN105786081A (en
Inventor
邵博闻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN201610191832.5A priority Critical patent/CN105786081B/en
Publication of CN105786081A publication Critical patent/CN105786081A/en
Application granted granted Critical
Publication of CN105786081B publication Critical patent/CN105786081B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

The invention discloses a kind of reference voltage source circuit, including：Biasing circuit, its first and two NMOS tube all work in subthreshold region and gate source voltage between the two subtracts each other to form the gate source voltage difference of positive temperature coefficient to the two ends of first resistor；Gate source voltage difference produces circuit poor including working in the 3rd and four NMOS tubes of subthreshold region, the gate source voltage that the series connection of the 3rd and four NMOS tubes and the source-drain electrode in the 3rd NMOS tube form the 3rd and four NMOS tubes；Biasing circuit and each gate source voltage difference produce circuit formed gate source voltage difference be added to reference voltage output circuit the 5th NMOS tube source electrode, the grid leak of the 5th NMOS tube is extremely connected and output reference voltage, 5th NMOS tube works in subthreshold region, is superimposed to form the reference voltage unrelated with temperature using each gate source voltage difference and with the Positive and Negative Coefficient Temperature of the gate source voltage of the 5th NMOS tube.The present invention can reduce area and reduce power consumption.

Description

Reference voltage source circuit
Technical field
The present invention relates to a kind of semiconductor integrated circuit, more particularly to a kind of reference voltage source circuit.
Background technology
Reference voltage source circuit is widely used in integrated circuits, as shown in figure 1, being existing reference voltage source circuit Circuit structure diagram；The grid of NMOS tube MN101 and MN102 links together and is all connected to the drain electrode of NMOS tube MN101, NMOS The source ground of pipe MN101, the source electrode of NMOS tube MN102 is grounded by resistance R101；The drain electrode of NMOS tube MN101 be connected to by The current path of PMOS MP101 compositions, the drain electrode of NMOS tube MN102 is connected to the current path being made up of PMOS MP102, PMOS MP101 and MP102 mirror image each other.The channel width-over-length ratio raceway groove of the requirement more than NMOS tube MN101 of NMOS tube MN102 is wide Ratio long, in addition, the ratio of the channel width-over-length ratio of the channel width-over-length ratio of NMOS tube MN102 and NMOS tube MN101 is N.During work, NMOS tube MN101 and MN102 work in subthreshold region, and the source-drain current of the subthreshold region of NMOS tube has following spy Property：
Because NMOS tube MN101 and MN102 are operated in sub-threshold region, MOS transistor is the subthreshold of NMOS tube or PMOS The formula of the conducting electric current in value area is：
Wherein, IDIt is the leakage current of corresponding MOS transistor；ID0It is the characteristic current of corresponding MOS transistor, ID0With The characteristic current of the nmos pass transistor that the breadth length ratio of the raceway groove of MOS transistor is directly proportional and uses same process to be formed is a constant And it is identical；VGSIt is the gate source voltage of MOS transistor；M is the thermodynamic voltage of the subthreshold conduction electric current of metal-oxide-semiconductor transistor；VT It is thermal voltage, andWith positive temperature coefficient, T represents absolute temperature, and k is Boltzmann constant, and q is electron charge.
As shown in Figure 1, the voltage difference at resistance R101 two ends is, the gate source voltage V of NMOS tube MN101GS101And NMOS tube The gate source voltage V of MN102GS102Difference, i.e.,：
VR101=VGS101-VGS102----------------------(2)；
Make PMOS MP101 and 102 be of the same size, the breadth length ratio of NMOS tube MN101 and MN102 is updated to public affairs Formula (1) is simultaneously updated to formula (2) and can obtain：
The electric current flowed through on R101 is：
Understand,That is VTWith positive temperature coefficient, therefore VR101And IR101All there is positive temperature coefficient.
Include NMOS tube MN103, resistance R102 and PMOS MP103, PMOS MP103 in reference voltage outgoing route Mirror image circuit is constituted with MP101 and both sizes of order are identical.
As shown in Figure 1, the drain electrode connection end output reference voltage VREF of resistance R102 and PMOS MP103, NMOS tube MN103 works in subthreshold region, and the gate source voltage of NMOS tube MN103 can be more than threshold voltage if resistance R102 is not provided with And work in saturation region；NMOS tube MN103 can work in subthreshold region after being provided with resistance R102, using working in pressure threshold value The source-drain current and gate source voltage of the MOS transistor in region such as NMOS tube or PMOS all characteristics with negative temperature coefficient, Make the reference voltage of output Positive and Negative Coefficient Temperature offset so as to and temperature it is unrelated, i.e.,：Flow through the source-drain current of NMOS tube MN103 With negative temperature characterisitic, and the electric current for flowing through PMOS MP103 is IR101Image current so as to have positive temperature characterisitic, Both can cancel out each other so as to realize at Positive and Negative Coefficient Temperature.
Needed in outgoing route in Fig. 1 using resistance R102, in semiconductor integrated circuit resistance can take chip compared with Big area, this can reduce the integrated level of chip and improve cost so as to relative, and some cost sensitivity applications to area requirements compared with Height, thus should phase method reduce circuit area.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of reference voltage source circuit, can reduce area.
In order to solve the above technical problems, the reference voltage source circuit that the present invention is provided includes：
Biasing circuit, including the first NMOS tube, the second NMOS tube and first resistor, the raceway groove length wide of second NMOS tube Than the channel width-over-length ratio more than first NMOS tube, the source ground of first NMOS tube, the source of second NMOS tube Pole is grounded by the first resistor, and the grid of the drain and gate of first NMOS tube and second NMOS tube all connects The first bias voltage is connect, the drain electrode of first NMOS tube connects the first current path, the drain electrode connection of second NMOS tube Second current path, first current path and second current path mirror image each other；First NMOS tube and described Second NMOS tube works in subthreshold region, and tool is provided in the connection end of the first resistor and the source electrode of second NMOS tube There is the first order gate source voltage of positive temperature coefficient poor, the first order gate source voltage difference is first NMOS tube and described second Gate source voltage between NMOS tube is poor.
Gate source voltage difference more than one-level produces circuit, each gate source voltage difference produce circuit include the 3rd NMOS tube, 4th NMOS tube and the 3rd current path, the source electrode of the 4th NMOS tube connect the drain electrode of the 3rd NMOS tube, and described the The grid of the drain and gate of four NMOS tubes and the 3rd NMOS tube links together and is all connected to the 3rd electric current road Footpath, the 3rd current path and first current path mirror image each other；The channel width-over-length ratio of the 4th NMOS tube is more than The channel width-over-length ratio of the 3rd NMOS tube, the source electrode connection previous stage gate source voltage of the 3rd NMOS tube is poor, the first order The gate source voltage difference produces the previous stage gate source voltage difference of circuit for the first order gate source voltage is poor, the 3rd NMOS tube With the 4th NMOS tube be all operated in subthreshold region and the 3rd NMOS tube drain electrode output have positive temperature coefficient When prime gate source voltage it is poor.
Reference voltage output circuit, including the 5th NMOS tube and the 4th current path；4th current path and described First current path mirror image each other；The grid of the 5th NMOS tube and drain electrode all connect the 4th current path, and described the The drain electrode of five NMOS tubes as reference voltage output end, the 5th NMOS tube source electrode connection afterbody described in grid source electricity Pressure difference produces the gate source voltage that circuit is exported poor；5th NMOS tube is operated in sub-threshold region makes the 5th NMOS tube Gate source voltage has negative temperature coefficient；The reference voltage is the gate source voltage and the grid source electricity at different levels of the 5th NMOS tube The sum of pressure difference, has negative temperature coefficient and the gate source voltage difference at different levels with just using the gate source voltage of the 5th NMOS tube The characteristic of temperature coefficient realizes the counteracting of temperature coefficient, makes the reference voltage and temperature unrelated.
Further improvement is that first current path, second current path, the gate source voltage difference at different levels are produced 3rd current path and the 4th current path of raw circuit are all made up of a PMOS, and the grid of each PMOS is connected to Mirror is realized together.
Further improvement is that first current path, second current path, the gate source voltage difference at different levels are produced 3rd current path of raw circuit and the size of current of the 4th current path are equal.
Further improvement is that it is two-stage that the gate source voltage difference produces the series of circuit.
The present invention produces circuit to improve reference voltage by using the gate source voltage difference being made up of NMOS tube and PMOS The source voltage of the output NMOS tube of output circuit, makes the output NMOS tube of reference voltage output circuit work in sub-threshold region Domain, has negative temperature coefficient and at different levels works in subthreshold region using the gate source voltage of the NMOS tube for working in pressure threshold region The gate source voltage mutual coefficient of the difference with positive temperature coefficient of NMOS tube realize and the unrelated reference voltage of temperature, relative to existing There is technology, the present invention need not use resistance in outgoing route, so as to save the usage amount of resistance, reduce circuit area.
In addition, the present invention can also reduce the power consumption of circuit, reason is：The electric current of reference voltage output circuit of the invention with And the electric current of gate source voltage difference generation circuits at different levels can all flow to first resistor, and the voltage at first resistor two ends keeps constant, Namely compared to the prior art the electric current of first resistor of the invention is dispersed on each bar branch road, reference voltage output circuit with And gate source voltage difference generation circuits at different levels will not bring extra power consumption, therefore the present invention can also reduce the power consumption of circuit.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is the circuit structure diagram of existing reference voltage source circuit；
Fig. 2 is the circuit structure diagram of embodiment of the present invention reference voltage source circuit.
Specific embodiment
As shown in Fig. 2 being the circuit structure diagram of embodiment of the present invention reference voltage V REF source circuits, embodiment of the present invention base Quasi- voltage VREF source circuits include：
Biasing circuit 1, including the first NMOS tube MN1, the second NMOS tube MN2 and first resistor R1, second NMOS tube Channel width-over-length ratio of the channel width-over-length ratio of MN2 more than the first NMOS tube MN1, the source ground of the first NMOS tube MN1 The source electrode of GNDA, the second NMOS tube MN2 is grounded GNDA, the leakage of the first NMOS tube MN1 by the first resistor R1 The grid of pole and grid and the second NMOS tube MN2 all connects the first bias voltage NBIAS, the first NMOS tube MN1 Drain electrode connect the first current path, the drain electrode of the second NMOS tube MN2 connects the second current path, the first electric current road Footpath and second current path mirror image each other；The first current path is made up of PMOS MP1 described in the embodiment of the present invention, institute The second current path is stated to be made up of PMOS MP2.
The first NMOS tube MN1 and the second NMOS tube MN2 work in subthreshold region, in the first resistor R1 It is poor the first order gate source voltage with positive temperature coefficient to be provided with the connection end of the source electrode of the second NMOS tube MN2, described the One-level gate source voltage difference is poor for the gate source voltage between the first NMOS tube MN1 and the second NMOS tube MN2.
Gate source voltage difference more than one-level produces circuit, each gate source voltage difference produce circuit include the 3rd NMOS tube, 4th NMOS tube and the 3rd current path, the source electrode of the 4th NMOS tube connect the drain electrode of the 3rd NMOS tube, and described the The grid of the drain and gate of four NMOS tubes and the 3rd NMOS tube links together and is all connected to the 3rd electric current road Footpath, the 3rd current path and first current path mirror image each other；The channel width-over-length ratio of the 4th NMOS tube is more than The channel width-over-length ratio of the 3rd NMOS tube, the source electrode connection previous stage gate source voltage of the 3rd NMOS tube is poor, the first order The gate source voltage difference produces the previous stage gate source voltage difference of circuit for the first order gate source voltage is poor, the 3rd NMOS tube With the 4th NMOS tube be all operated in subthreshold region and the 3rd NMOS tube drain electrode output have positive temperature coefficient When prime gate source voltage it is poor.It is two-stage that the difference of gate source voltage described in the embodiment of the present invention produces the series of circuit, respectively such as void Shown in wire frame 2a and 2b, the gate source voltage difference produces the 3rd NMOS tube of circuit 2a to be marked with MN3a, and the 4th NMOS tube is used MN4a is marked, and the 3rd current path is made up of PMOS MP3a；The gate source voltage difference produces the 3rd NMOS tube of circuit 2b to use MN3b is marked, and the 4th NMOS tube is marked with MN4b, and the 3rd current path is made up of PMOS MP3b.
Reference voltage output circuit 3, including the 5th NMOS tube MN5 and the 4th current path；4th current path and First current path mirror image each other, the 4th current path is made up of PMOS MP4 in the embodiment of the present invention；Described 5th The grid of NMOS tube MN5 and drain electrode all connect the 4th current path, and the drain electrode of the 5th NMOS tube MN5 is used as benchmark electricity The output end of VREF, gate source voltage difference described in the source electrode connection afterbody of the 5th NMOS tube MN5 is pressed to produce circuit institute defeated The gate source voltage for going out is poor；The 5th NMOS tube MN5 is operated in sub-threshold region has the gate source voltage of the 5th NMOS tube MN5 There is negative temperature coefficient；The reference voltage V REF is the gate source voltage and the gate source voltage at different levels of the 5th NMOS tube MN5 Poor sum, using the gate source voltage of the 5th NMOS tube MN5 there is negative temperature coefficient and the gate source voltage difference at different levels to have The characteristic of positive temperature coefficient realizes the counteracting of temperature coefficient, makes the reference voltage V REF and temperature unrelated.
Operation principle is described as follows in the embodiment of the present invention：
The present invention is electric by first current path, second current path, the grid source at different levels for convenience of description It is equal that pressure difference produces the 3rd current path of circuit and the size of current of the 4th current path to be set to, PMOS MP1, The source electrode of MP2, MP3a, MP3b and MP4 is all supply voltage VDDA, and grid all links together and connects PBIAS, and it is electric current to drain The output end in path, PMOS MP1, MP2, MP3a, MP3b and the setting of MP4 are set to identical then may be such that first electric current Path, second current path, the 3rd current path and the 4th electric current of the gate source voltage difference generation circuit at different levels The size of current in path is equal.
First, compare and understood shown in Fig. 1 and Fig. 2, the biasing circuit 1 of the embodiment of the present invention is identical with available circuit, so Equally have：The voltage difference at resistance R1 two ends is, the gate source voltage V of NMOS tube MN1GS1With the gate source voltage V of NMOS tube MN2GS2's Difference, i.e.,：
VR1=VGS1-VGS2----------------------(2a)；
The ratio of the channel width-over-length ratio of NMOS tube MN2 and the channel width-over-length ratio of NMOS tube MN1 is equally made for N, will by this The breadth length ratio and ratio N of NMOS tube MN1 and NM2 are updated to formula (1) and are updated to formula (2a) and can obtain：
Understand, therefore VR1With positive temperature coefficient, V in the embodiment of the present inventionR1First order gate source voltage is poor.
Secondly, gate source voltage difference produces circuit 2a and 2b poor, the respectively V that each provides other two-stage gate source voltageDS3a And VDS3b, wherein VDS3aIt is the source-drain voltage and V of NMOS tube MN3aDS3bIt is the source-drain voltage of NMOS tube MN3b.Assuming that NMOS tube The breadth length ratio of MN4a is N1 times of NMOS tube MN3a, and the breadth length ratio of NMOS tube MN4b is N2 times of NMOS tube MN3b, then have：
VDS3aFormula be：
VDS3a=VGS3a-VGS4a----------------------(2b)；
Wherein VGS3aIt is the gate source voltage of NMOS tube MN3a, VGS4aIt is the gate source voltage of NMOS tube MN4a；
As seen from Figure 2, the source-drain current of NMOS tube MN3a is 3 times of the source-drain current of NMOS tube NM4a, will by this The breadth length ratio and ratio N1 and current ratio 3 of NMOS tube MN4a and NM3a are accordingly updated to formula (1) and are updated to formula (2b) Can obtain：
VDS3bFormula be：
VDS3b=VGS3b-VGS4b----------------------(2c)；
Wherein VGS3bIt is the gate source voltage of NMOS tube MN3b, VGS4bIt is the gate source voltage of NMOS tube MN4b；
As seen from Figure 2, the source-drain current of NMOS tube MN3b is 2 times of the source-drain current of NMOS tube NM4b, will by this The breadth length ratio and ratio N1 and current ratio 2 of NMOS tube MN4b and NM3b are accordingly updated to formula (1) and are updated to formula (2c) Can obtain：
As shown in Figure 2, the formula of the reference voltage V REF for finally exporting is：
VREF=VR1+VDS3a+VDS3b+VGS5--------------------(4)。
Wherein VGS5It is the gate source voltage of NMOS tube MN5.
From formula (4), VR1, VDS3a, VDS3bAll it is operate on two gate source voltages of NMOS tube of subthreshold region Difference, with positive temperature coefficient；And VGS5The gate source voltage of the NMOS tube of subthreshold region is operate on, with negative temperature Degree coefficient, both can cancel out each other so that the reference voltage V REF and temperature that export are unrelated.Relative to existing shown in Fig. 1 Structure is that the embodiment of the present invention passes through multistage gate source voltage difference and raise the source voltage of NMOS tube MN5 and make NMOS tube MN5 Pressure threshold region is worked in, so the embodiment of the present invention can save the resistance R102 shown in the output circuit in a Fig. 1, Therefore the embodiment of the present invention can save resistance, so as to reduce circuit area.
Emulation experiment shows that resistance needed for embodiment of the present invention circuit is 231.5K Europe, and the existing structure shown in Fig. 1 is 1012.9K Europe, so can greatly reduce area.
In addition, the embodiment of the present invention can also reduce the power consumption of circuit, reason is：Compare and understood shown in Fig. 1 and Fig. 2, this hair Bright first resistor R1 and the voltage at the resistance R101 two ends of existing structure are identicals, namely both electric currents are also identical, this Gate source voltage difference generation circuit 2a, 2b and reference voltage output circuit 3 of inventive embodiments can be input in first resistor R1, Namely the electric current of first resistor R1 is dispersed on each bar branch road, reference voltage output circuit and gate source voltage at different levels difference are produced Circuit will not bring extra power consumption, and outgoing route where PMOS MP102, resistance R102 and NMOS tube MN103 in Fig. 1 Extra power consumption is needed, therefore the present invention can also reduce the power consumption of circuit.Emulation shows that the power consumption of the embodiment of the present invention is： 346.7nA, and the existing structure shown in Fig. 1 is 819.1nA, therefore the power consumption of the embodiment of the present invention is reduced really.
The present invention has been described in detail above by specific embodiment, but these are not constituted to limit of the invention System.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and improvement, and these also should It is considered as protection scope of the present invention.

Claims (4)

1. a kind of reference voltage source circuit, it is characterised in that including：
Biasing circuit, including the first NMOS tube, the second NMOS tube and first resistor, the channel width-over-length ratio of second NMOS tube are big In the channel width-over-length ratio of first NMOS tube, the source ground of first NMOS tube, the source electrode of second NMOS tube leads to Cross first resistor ground connection, the grid of the drain and gate of first NMOS tube and second NMOS tube all connects the One bias voltage, the drain electrode of first NMOS tube connects the first current path, the drain electrode connection second of second NMOS tube Current path, first current path and second current path mirror image each other；First NMOS tube and described second NMOS tube works in subthreshold region, and being provided in the connection end of the first resistor and the source electrode of second NMOS tube has just The first order gate source voltage of temperature coefficient is poor, and the first order gate source voltage difference is first NMOS tube and the 2nd NMOS Gate source voltage between pipe is poor；
Gate source voltage difference generation circuit more than one-level, each gate source voltage difference generation circuit includes the 3rd NMOS tube, the 4th NMOS tube and the 3rd current path, the source electrode of the 4th NMOS tube connect the drain electrode of the 3rd NMOS tube, the described 4th The grid of the drain and gate of NMOS tube and the 3rd NMOS tube links together and is all connected to the 3rd current path, 3rd current path and first current path mirror image each other；The channel width-over-length ratio of the 4th NMOS tube is more than described The channel width-over-length ratio of the 3rd NMOS tube, the 3rd NMOS tube source electrode connection previous stage gate source voltage it is poor, the first order it is described Gate source voltage difference produces the previous stage gate source voltage difference of circuit for the first order gate source voltage is poor, the 3rd NMOS tube and institute State the 4th NMOS tube and be all operated in subthreshold region and in drain electrode output the working as with positive temperature coefficient of the 3rd NMOS tube Prime gate source voltage is poor；
Reference voltage output circuit, including the 5th NMOS tube and the 4th current path；4th current path and described first Current path mirror image each other；The grid of the 5th NMOS tube and drain electrode all connect the 4th current path, the described 5th The drain electrode of NMOS tube as reference voltage output end, the 5th NMOS tube source electrode connection afterbody described in gate source voltage Difference produces the gate source voltage that circuit is exported poor；5th NMOS tube is operated in sub-threshold region makes the grid of the 5th NMOS tube Source voltage has negative temperature coefficient；The reference voltage is the gate source voltage and the gate source voltage at different levels of the 5th NMOS tube Poor sum, using the gate source voltage of the 5th NMOS tube there is negative temperature coefficient and the gate source voltage difference at different levels to have positive warm The characteristic for spending coefficient realizes the counteracting of temperature coefficient, makes the reference voltage and temperature unrelated.
2. reference voltage source circuit as claimed in claim 1, it is characterised in that：First current path, second electricity Flow path, the gate source voltage difference at different levels produce the 3rd current path and the 4th current path of circuit all by a PMOS Pipe is constituted, and the grid of each PMOS links together and realizes mirror.
3. reference voltage source circuit as claimed in claim 1 or 2, it is characterised in that：First current path, described second Current path, the gate source voltage difference at different levels produce the 3rd current path of circuit and the size of current of the 4th current path It is equal.
4. reference voltage source circuit as claimed in claim 1, it is characterised in that：The gate source voltage difference produces the series of circuit It is two-stage.
CN201610191832.5A 2016-03-30 2016-03-30 Reference voltage source circuit Active CN105786081B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610191832.5A CN105786081B (en) 2016-03-30 2016-03-30 Reference voltage source circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610191832.5A CN105786081B (en) 2016-03-30 2016-03-30 Reference voltage source circuit

Publications (2)

Publication Number Publication Date
CN105786081A CN105786081A (en) 2016-07-20
CN105786081B true CN105786081B (en) 2017-06-06

Family

ID=56392050

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610191832.5A Active CN105786081B (en) 2016-03-30 2016-03-30 Reference voltage source circuit

Country Status (1)

Country Link
CN (1) CN105786081B (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102124241B1 (en) * 2016-08-16 2020-06-18 선전 구딕스 테크놀로지 컴퍼니, 리미티드 Linear regulator
CN106484018A (en) * 2016-09-29 2017-03-08 广州智慧城市发展研究院 A kind of reference voltage source circuit system and supply unit
CN108007594B (en) * 2016-10-31 2020-05-19 深圳市中兴微电子技术有限公司 Temperature detection circuit and method
CN107015595A (en) * 2017-05-03 2017-08-04 苏州大学 It is operated in subthreshold region high-precision low-power consumption low-voltage bandgap reference source
CN107272811B (en) * 2017-08-04 2018-11-30 佛山科学技术学院 A kind of low-temperature coefficient reference voltage source circuit
CN107783586B (en) * 2017-11-10 2022-12-20 佛山科学技术学院 Voltage reference source circuit without bipolar transistor
CN107992145A (en) * 2017-12-06 2018-05-04 电子科技大学 A kind of voltage reference circuit with super low-power consumption characteristic
CN107943183A (en) * 2017-12-06 2018-04-20 电子科技大学 A kind of voltage reference circuit of super low-power consumption
CN109062305B (en) * 2018-07-26 2020-06-09 上海华虹宏力半导体制造有限公司 Reference voltage source circuit
CN109947165A (en) * 2019-01-31 2019-06-28 敦泰电子有限公司 Voltage reference source circuit and low-power dissipation power supply system
CN111381625B (en) * 2020-03-12 2022-05-20 上海华虹宏力半导体制造有限公司 Reference source circuit
CN112198921B (en) * 2020-10-20 2022-06-21 上海华虹宏力半导体制造有限公司 Reference voltage source circuit
CN115220515A (en) * 2021-04-16 2022-10-21 中国科学院微电子研究所 Voltage reference circuit, component and equipment
CN113296571B (en) * 2021-07-27 2021-10-22 上海南麟集成电路有限公司 Reference voltage source circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102662427A (en) * 2012-05-25 2012-09-12 中国科学院微电子研究所 Voltage source circuit
CN103440013A (en) * 2013-08-30 2013-12-11 江苏物联网研究发展中心 Band-gap reference voltage source structure without passive elements based on standard CMOS technology
CN104156026A (en) * 2014-08-26 2014-11-19 电子科技大学 Non-resistance and total temperature compensation non-band-gap reference source
CN105404351A (en) * 2015-12-14 2016-03-16 上海华虹宏力半导体制造有限公司 Current bias circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009093483A (en) * 2007-10-10 2009-04-30 Kobe Univ Temperature compensation bias circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102662427A (en) * 2012-05-25 2012-09-12 中国科学院微电子研究所 Voltage source circuit
CN103440013A (en) * 2013-08-30 2013-12-11 江苏物联网研究发展中心 Band-gap reference voltage source structure without passive elements based on standard CMOS technology
CN104156026A (en) * 2014-08-26 2014-11-19 电子科技大学 Non-resistance and total temperature compensation non-band-gap reference source
CN105404351A (en) * 2015-12-14 2016-03-16 上海华虹宏力半导体制造有限公司 Current bias circuit

Also Published As

Publication number Publication date
CN105786081A (en) 2016-07-20

Similar Documents

Publication Publication Date Title
CN105786081B (en) Reference voltage source circuit
CN106527572A (en) CMOS subthreshold reference circuit with low power dissipation and low temperature drift
CN102541149B (en) Reference power circuit
CN107992156B (en) A kind of subthreshold value low-power consumption non-resistance formula reference circuit
CN103389766B (en) Sub-threshold non-bandgap reference voltage source
CN106200732A (en) Generate the circuit of output voltage and the method to set up of the output voltage of low dropout voltage regulator
CN105955391A (en) Band-gap reference voltage generation method and circuit
CN103092253A (en) Reference voltage generation circuit
CN104156025B (en) A kind of high-order temperature compensated reference source
CN104156026B (en) Non-bandgap reference source is repaid in the full temperature compensation of a kind of non-resistance
CN102385411A (en) Reference current generating circuit
CN105468076B (en) Full cmos reference current source
TW201525647A (en) Bandgap reference generating circuit
CN104571251A (en) Reference voltage generator
CN104076856B (en) A kind of super low-power consumption non-resistance non-bandgap reference source
CN105094207A (en) Band gap reference source eliminating bulk effect
CN101149628B (en) Reference voltage source circuit
CN104615184A (en) CMOS reference current and reference voltage generating circuit
CN108055014A (en) Differential operational amplifier and bandgap reference voltage generating circuit
CN102662427A (en) Voltage source circuit
CN108363447A (en) A kind of full MOS type current source circuit of low-temperature coefficient with technological compensa tion
CN104881071A (en) Low-power reference voltage source
CN107066006A (en) Novel band gap reference circuit structure
CN204576336U (en) Reference voltage source circuit
CN103123512A (en) Band-gap reference circuit

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant