CN112198921B - Reference voltage source circuit - Google Patents

Reference voltage source circuit Download PDF

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Publication number
CN112198921B
CN112198921B CN202011121202.3A CN202011121202A CN112198921B CN 112198921 B CN112198921 B CN 112198921B CN 202011121202 A CN202011121202 A CN 202011121202A CN 112198921 B CN112198921 B CN 112198921B
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temperature coefficient
circuit
voltage
current
positive temperature
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CN112198921A (en
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邵博闻
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

The application relates to the technical field of semiconductor integrated circuits, in particular to a reference voltage source circuit. The method comprises the following steps: a current mirror circuit including a first current path and a second current path; the first current path is used for generating a bias current according to the second current path; the mirror image circuit is used for copying the bias current to generate a mirror image current; the negative temperature coefficient generating circuit generates a negative temperature coefficient current on a resistor R1 through a current mirror circuit and generates a negative temperature coefficient voltage on a negative temperature coefficient node NB 1; the positive temperature coefficient generating circuit can form positive temperature coefficient voltage; the positive temperature coefficient generating circuit enables the negative temperature coefficient voltage on the negative temperature coefficient node NB1 to be superposed with the positive temperature coefficient voltage weight formed by the positive temperature coefficient generating circuit, and a reference prepared voltage irrelevant to temperature is output; the amplifying output circuit is connected with the positive temperature coefficient generating circuit to form a common gate amplifier taking the reference reserve voltage as the input voltage.

Description

Reference voltage source circuit
Technical Field
The application relates to the technical field of semiconductor integrated circuits, in particular to a reference voltage source circuit.
Background
The reference voltage source circuit is widely used in an integrated circuit because it can generate a precise and stable reference voltage.
Fig. 1 shows a reference voltage source circuit provided in the related art, which includes a current mirror circuit 101 composed of a PMOS transistor P1, a PMOS transistor P2, an NMOS transistor N1, an NMOS transistor N2, and a resistor RX, and a reference output circuit 102. The reference output circuit 102 comprises a PMOS transistor P3, a resistor RY and an NMOS transistor N3, wherein a connection node between one end of the resistor RY and the drain of the PMOS transistor P3 is used for outputting a reference voltage Vout.
However, the reference voltage output by the related art has a weak driving capability, and when a resistive load is applied to the reference voltage, the reference voltage output by the reference voltage source circuit of the related art varies with the variation of the resistive load, which affects the accuracy of the reference voltage.
Disclosure of Invention
The application provides a reference voltage source circuit, which can solve the problem that the driving capability of reference voltage in the related art is weaker.
The application provides a reference voltage source circuit, reference voltage source circuit includes:
a current mirror circuit including a first current path and a second current path that are mirror images of each other; the first current path is used for generating bias current independent of a power supply according to the second current path;
the mirror circuit is connected with the current mirror circuit and is used for copying the bias current to generate a mirror current;
a negative temperature coefficient generating circuit including a negative temperature coefficient node NB1, the negative temperature coefficient node NB1 being connected between a resistor R1 and the current mirror circuit, and generating a negative temperature coefficient current at the resistor R1 and a negative temperature coefficient voltage at the negative temperature coefficient node NB1 via the current mirror circuit;
the mirror current flows through the positive temperature coefficient generating circuit, and the positive temperature coefficient generating circuit can form positive temperature coefficient voltage; the positive temperature coefficient generating circuit is also connected with the negative temperature coefficient node NB1, so that the negative temperature coefficient voltage on the negative temperature coefficient node NB1 is superposed with the positive temperature coefficient voltage weight formed by the positive temperature coefficient generating circuit, and a reference preparatory voltage irrelevant to temperature is output;
and the amplification output circuit is connected with the positive temperature coefficient generating circuit to form a common gate amplifier taking the reference reserve voltage as an input voltage.
Optionally, the negative temperature coefficient generating circuit further comprises an NMOS transistor MN1 and an NMOS transistor MN 2;
a bias node NB2 is arranged on the first current path;
the grid electrode of the NMOS tube MN1 is connected with the negative temperature coefficient node NB1, the drain electrode is connected with the bias node NB2, and the source electrode is grounded;
the gate of the NMOS transistor MN2 is connected to the bias node NB2, the drain is connected to the output end of the second current path, and the source is connected to the negative temperature coefficient node NB 1.
Optionally, the positive temperature coefficient generating circuit comprises an NMOS transistor MNX and an NMOS transistor MNY;
the source electrode of the NMOS tube MNX is connected with the negative temperature coefficient node NB1, the grid electrode of the NMOS tube MNX is connected with the grid electrode of the NMOS tube MNY and the drain electrode of the NMOS tube MNY, and the mirror image current flows into the drain electrode of the NMOS tube MNY;
the drain of the NMOS MNX and the source of the NMOS MNY are used to form the reference preliminary voltage.
Optionally, the positive temperature coefficient generating circuit comprises a primary positive temperature coefficient generating circuit and a secondary positive temperature coefficient generating circuit; the mirror circuit comprises a first mirror circuit and a second mirror circuit;
the first mirror image circuit and the second mirror image circuit are respectively connected with the current mirror circuit and are used for respectively copying the bias current to generate a first mirror image current and a second mirror image current;
the first mirror current flows into the primary positive temperature coefficient generating circuit, and the second mirror current flows into the secondary positive temperature coefficient generating circuit;
the primary positive temperature coefficient generating circuit can generate a first positive temperature coefficient voltage, can superpose the negative temperature coefficient voltage on a negative temperature coefficient node NB1 with the first positive temperature coefficient voltage weight, and outputs primary positive and negative temperature quantity weight superposition voltage to the secondary positive temperature coefficient generating circuit at a superposition node NB 3;
the secondary positive temperature coefficient generating circuit can generate a second positive temperature coefficient voltage, and can further weight and overlap the primary positive and negative temperature quantity weight and superposed voltage with the second positive temperature coefficient voltage to generate the reference reserve voltage.
Optionally, the first mirror circuit includes a PMOS transistor MP3, and the second mirror circuit includes a PMOS transistor MP 4;
the source electrode of the PMOS tube MP3 is connected with a power supply, the grid electrode of the PMOS tube MP3 is connected with the output end of the second current path, and the drain electrode of the PMOS tube MP3 is used for generating the first mirror current;
the source of the PMOS transistor MP4 is connected to the power supply, the gate is connected to the output of the second current path, and the drain is used for generating the second mirror current.
Optionally, the primary positive temperature coefficient generating circuit comprises an NMOS transistor MN3 and an NMOS transistor MN 4;
the source of the NMOS transistor MN3 is connected to the negative temperature coefficient node NB1, the gate of the NMOS transistor MN3 is connected to the gate of the NMOS transistor MN4 and to the drain of the NMOS transistor MN4, and the first mirror current flows into the drain of the NMOS transistor MN 4;
the drain electrode of the NMOS transistor MN3 is connected with the source electrode of the NMOS transistor MN4 to form a superposition node NB 3.
Optionally, the secondary positive temperature coefficient generating circuit comprises an NMOS transistor MN5 and an NMOS transistor MN 6;
the source electrode of the NMOS tube MN5 is connected with the superposition node NB3, the gate electrode of the NMOS tube MN5 is connected with the gate electrode of the NMOS tube MN6 and the drain electrode of the NMOS tube MN6, and the second mirror current flows into the drain electrode of the NMOS tube MN 6;
the drain electrode of the NMOS transistor MN5 is connected with the source electrode of the NMOS transistor MN6 and is used for generating the reference preparation voltage.
Optionally, the amplifying output circuit comprises an NMOS transistor MN 7;
the grid electrode of the NMOS transistor MN7 is connected with the drain electrode of the NMOS transistor MN6, and forms a common-gate amplifier with the NMOS transistor MN 6;
the drain electrode of the NMOS transistor MN7 is connected with a power supply, and the source electrode of the NMOS transistor MN7 is used for generating a reference voltage according to the reference standby voltage.
Optionally, the amplified output circuit further comprises:
and a gate of the tail current NMOS tube MN8, a drain of the MN8 is connected with the negative temperature coefficient node NB1, a source of the NMOS tube MN7 is connected, and a source of the NMOS tube is grounded.
Optionally, the first current path comprises a PMOS transistor MP1, and the second current path comprises a PMOS transistor MP 2;
the source electrode of the PMOS tube MP1 is connected with a power supply, the drain electrode is used for outputting the bias current, and the grid electrode is connected with the grid electrode of the PMOS tube MP 2;
the source electrode of the PMOS tube MP2 is connected with a power supply, the drain electrode of the PMOS tube MP2 is connected with the grid electrode of the PMOS tube MP2, and the drain electrode of the PMOS tube MP2 is the output end of the second current path.
The technical scheme at least comprises the following advantages: the positive temperature coefficient generating circuit and the positive temperature coefficient generating circuit are matched to superpose the weights of the positive temperature quantity and the negative temperature quantity, so that a reference voltage irrelevant to temperature can be formed; through the cooperation of the amplifying output circuit and the positive temperature coefficient generating circuit, the reference voltage can be amplified and output according to the reference reserve voltage, so that the driving capability of the reference voltage can be improved, and the precision of the reference voltage output by the circuit can be improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 shows a reference voltage source circuit provided in the related art;
FIG. 2 illustrates a reference voltage source circuit provided by an embodiment of the present application;
fig. 3 shows a reference voltage source circuit according to another embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making creative efforts belong to the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Fig. 2 shows a reference voltage source circuit provided in an embodiment of the present application, and referring to fig. 2, the reference voltage source circuit includes: a current mirror circuit 210, a negative temperature coefficient generation circuit 220, a mirror circuit 230, a positive temperature coefficient generation circuit 240, and an amplification output circuit 250.
The current mirror circuit 210 includes a first current path 211 and a second current path 212 that are mirror images of each other; the first current path 211 is used for generating a power-supply-independent bias current I according to the second current path 212ref。
The negative temperature coefficient generating circuit 220 comprises a negative temperature coefficient node NB1 and a resistor R1, the negative temperature coefficient node NB1 is connected between the resistor R1 and the current mirror circuit 210, and a negative temperature coefficient current I is generated on the resistor R1 by the current mirror circuit 2100A negative temperature coefficient voltage is generated at the negative temperature coefficient node NB 1. Optionally, the negative temperature coefficient node NB1 is connected between the resistor R1 and the output terminal of the second current path 212, and a negative temperature coefficient current I is generated on the resistor R1 through the second current path 2120A negative temperature coefficient voltage is generated at the negative temperature coefficient node NB 1.
The mirror circuit 230 is connected to the current mirror circuit 210 for duplicating the bias current IrefGenerating a mirror current ID. In this embodiment, the mirror circuit 230 includes a first mirror circuit 231 and a second mirror circuit 232 connected in parallel, the first mirror circuit231 and a second mirror circuit 232 are respectively connected to the current mirror circuit 210 for respectively duplicating the bias current IrefGenerating a first mirror current ID1And a second mirror current ID2。
The mirror current IDFlowing through the positive temperature coefficient generating circuit 240, the positive temperature coefficient generating circuit 240 is capable of forming a positive temperature coefficient voltage (+) Δ VGS, and the positive temperature coefficient generating circuit 240 is further connected to the negative temperature coefficient node NB1, such that the negative temperature coefficient voltage (-) VNB1 on the negative temperature coefficient node NB1 is superimposed with the positive temperature coefficient voltage (+) Δ VGS weight formed by the positive temperature coefficient generating circuit 240, and a temperature-independent reference preliminary voltage V is outputref-inI.e. Vref-in(-) VNB1+ (+) Δ VGS. In this embodiment, the ptc generating circuit 240 includes a first-stage ptc generating circuit 241 and a second-stage ptc generating circuit 242; the first mirror current ID1Flows into the primary positive temperature coefficient generating circuit 241, and the second mirror current ID2Flows into the secondary positive temperature coefficient generating circuit 242. The primary positive temperature coefficient generating circuit 241 is capable of generating a first positive temperature coefficient voltage (+) Δ VGS1, and is capable of superposing the negative temperature coefficient voltage (-) VNB1 at the negative temperature coefficient node NB1 with the first positive temperature coefficient voltage (+) Δ VGS1 by weight, and outputting a primary positive/negative temperature quantity weight superposition voltage VNB3 to the secondary positive temperature coefficient generating circuit 242 at a superposition node NB 3; that is, the primary positive/negative temperature weight superimposed voltage VNB3 provided by the primary positive temperature coefficient generating circuit 241 to the secondary positive temperature coefficient generating circuit 242 is: VNB3 ═ VNB1+ (+) Δ VGS 1. It should be explained that the sign (-) in this text represents a quantity with a negative temperature coefficient and the sign (+) represents a quantity with a positive temperature coefficient. It can be seen that the primary positive temperature coefficient generating circuit 241 can perform a preliminary weighted superposition of the positive and negative temperature values.
The secondary positive temperature coefficient generating circuit 242 can generate a second positive temperature coefficient voltage (+) Δ VGS2, weight the primary positive and negative temperature quantities to a superimposed voltage VNB3, and further weight the secondary positive temperature coefficient voltage (+) Δ VGS2Superpositioning to generate the reference preparatory voltage Vref-inI.e. Vref-inV is found from VNB3+ (+) Δ VGS2 and VNB3 ═ VNB1+ (+) Δ VGS1ref-in(-) VNB1+ (+) Δ VGS1+ (+) Δ VGS 2. It can be seen that the positive and negative temperature quantities can be weighted again in the secondary positive temperature coefficient generating circuit 242.
The amplifying output circuit 250 is connected to the PTC generating circuit 240 to form the reference preliminary voltage Vref-inA common-gate amplifier for the input voltage and based on the reference preliminary voltage Vref-inOutput reference voltage Vref。
From the above, it can be determined that the second-level weight superposition of the positive and negative temperature quantities is performed through the cooperation of the positive temperature coefficient generating circuit and the positive temperature coefficient generating circuit, so that the reference voltage irrelevant to the temperature can be formed; through the cooperation of the amplifying output circuit and the positive temperature coefficient generating circuit, the reference voltage can be amplified and output according to the reference reserve voltage, so that the driving capability of the reference voltage can be improved, and the precision of the reference voltage output by the circuit can be improved.
In this embodiment, the first current path 211 includes a PMOS transistor MP1, and the second current path 212 includes a PMOS transistor MP 2; the source electrode of the PMOS tube MP1 is connected with a power supply, and the drain electrode is used for outputting the bias current IrefThe grid electrode of the PMOS tube MP2 is connected; the source of the PMOS transistor MP2 is connected to the power supply VDDA, the drain is connected to the gate of the PMOS transistor MP2, and the drain of the PMOS transistor MP2 is the output end of the second current path 212.
The negative temperature coefficient generating circuit 220 further comprises an NMOS transistor MN1 and an NMOS transistor MN 2; a bias node NB2 is arranged on the first current path 211; the grid electrode of the NMOS transistor MN1 is connected with the negative temperature coefficient node NB1, the drain electrode of the NMOS transistor MN is connected with the bias node NB2, and the source electrode of the NMOS transistor MN is grounded; the gate of the NMOS transistor MN2 is connected to the bias node NB2, the drain is connected to the output end of the second current path 212, and the source is connected to the negative temperature coefficient node NB 1.
The first mirror circuit 231 includes a PMOS transistor MP3, and the second mirror circuit 232 includes a PMThe OS pipe MP 4; the source of the PMOS transistor MP3 is connected to a power supply VDDA, the gate is connected to the output terminal of the second current path 212, and the drain is used for generating the first mirror current ID1(ii) a The source of the PMOS transistor MP4 is connected to a power supply VDDA, the gate is connected to the output terminal of the second current path 212, and the drain is used for generating the second mirror current ID2。
The primary positive temperature coefficient generating circuit 241 comprises an NMOS tube MN3 and an NMOS tube MN 4; the source electrode of the NMOS tube MN3 is connected with the negative temperature coefficient node NB1, the grid electrode of the NMOS tube MN3 is connected with the grid electrode of the NMOS tube MN4 and the drain electrode of the NMOS tube MN4, and the first mirror current ID1Flows into the drain electrode of the NMOS pipe MN 4; the drain electrode of the NMOS transistor MN3 is connected with the source electrode of the NMOS transistor MN4 to form a superposition node NB 3. Wherein, the channel width length ratio (W/L) of the NMOS transistor MN4MN4Is the channel width length ratio (W/L) of the NMOS tube MN3MN3M times of.
The secondary positive temperature coefficient generating circuit 242 comprises an NMOS tube MN5 and an NMOS tube MN 6; the source electrode of the NMOS transistor MN5 is connected with the superposition node NB3, the gate electrode of the NMOS transistor MN5 is connected with the gate electrode of the NMOS transistor MN6 and the drain electrode of the NMOS transistor MN6, and the second mirror current ID2Flows into the drain electrode of the NMOS pipe MN 6; the drain electrode of the NMOS transistor MN5 is connected with the source electrode of the NMOS transistor MN6 and is used for generating the reference preparatory voltage Vref-in. Wherein, the channel width length ratio (W/L) of the NMOS transistor MN6MN6Is the channel width length ratio (W/L) of the NMOS tube MN5MN5M times.
The amplification output circuit 250 comprises an NMOS tube MN 7; the grid electrode of the NMOS transistor MN7 is connected with the drain electrode of the NMOS transistor MN6, and forms a common-gate amplifier with the NMOS transistor MN 6; the drain electrode of the NMOS transistor MN7 is connected with a power supply, and the source electrode of the NMOS transistor MN7 is used for preparing a voltage V according to the referenceref-inGenerating a reference voltage Vref. The amplified output circuit 250 further includes: and a gate of the tail current NMOS tube MN8, a drain of the MN8 is connected with the negative temperature coefficient node NB1, a source of the NMOS tube MN7 is connected, and a source of the NMOS tube is grounded. In this embodiment, the NMOS transistor MN7 and the NMOS transistor MN6 of the secondary ptc generating circuit 242 form a common-gate amplifier according to the reference preliminary voltage Vref-inAmplifying outputOut of reference voltage Vref。
With continued reference to FIG. 2, the present embodiment provides a negative temperature coefficient voltage (-) VNB1 for the negative temperature coefficient node NB1 of FIG. 2 that is equal to the gate-source voltage VGS of the NMOS transistor MN1MN1That is, the negative temperature coefficient voltage (-) VNB1 ═ VGSMN1. For the primary positive temperature coefficient generating circuit 241, the primary positive and negative temperature weight of the superposition node NB3 is superposed with the added voltage VNB3, which is equal to the drain-source voltage VDS of the NMOS transistor MN3MN3The sum of the voltages with the negative temperature coefficient node NB1, VNB3 ═ VDSMN3+ (-) VNB 1. As can be seen from FIG. 2, the drain-source voltage VDS of the NMOS transistor MN3MN3Equal to the gate-source voltage VGS of the NMOS transistor MN3MN3And NMOS transistor MN4 gate-source voltage VGSMN4The difference, i.e. VDSMN3＝VGSMN3-VGSMN4. The current flowing out of the source electrode of the NMOS tube MN4 and the current flowing out of the source electrode of the NMOS tube MN5 converge at the position of a superposition node NB3, and in addition, the first mirror current ID1And a first mirror current ID1Are all to bias current IrefThe channel width-to-length ratio (W/L) of the NMOS transistor MN4MN4Is the channel width length ratio (W/L) of the NMOS tube MN3MN3M times, the current flowing through the NMOS transistor MN3 is twice the current flowing through the NMOS transistor MN 4. Accordingly, the gate-source voltage VGS of the NMOS transistor MN3MN3And NMOS transistor MN4 gate-source voltage VGSMN4The difference is equal to (kT/q) x ln (M/2), i.e. VDSMN3＝VGSMN3-VGSMN4Where k is boltzmann's constant, T is temperature, and q is a charge constant. Therefore, in the embodiment, the gate-source voltage VGS of the NMOS transistor MN3 is shownMN3And NMOS transistor MN4 gate-source voltage VGSMN4The difference is the first positive temperature coefficient voltage (+) Δ VGS1 generated by the primary positive temperature coefficient generating circuit 241. Namely (+) Δ VGS1 ═ VGSMN3-VGSMN4＝VDSMN3。
Further, the primary positive/negative temperature quantity weight superimposed voltage VNB3 of superimposed node NB3 is:
VNB3＝(-)VNB1+(+)ΔVGS1＝VGSMN1+VDSMN3。
with continued reference to FIG. 2, for the secondary PTC generating circuit 242, the reference preliminary voltage Vref-inEqual to the drain-source voltage VDS of the NMOS transistor MN5MN5The sum of the primary positive and negative temperature-weighted overlap voltage VNB3, i.e., V, with overlap node NB3ref-in＝VDSMN5+ VNB 3. As can be seen from FIG. 2, the drain-source voltage VDS of the NMOS transistor MN5MN5Equal to the gate-source voltage VGS of the NMOS transistor MN5MN5And NMOS transistor MN6 gate-source voltage VGSMN6The difference, i.e. VDSMN5＝VGSMN5-VGSMN6. Channel width-length ratio (W/L) of NMOS tube MN6MN6Is the channel width length ratio (W/L) of the NMOS tube MN5MN5M times, therefore the gate-source voltage VGS of the NMOS transistor MN5MN5And NMOS transistor MN6 gate-source voltage VGSMN6The difference is equal to (kT/q) x ln (M), i.e. VDSMN5＝VGSMN5-VGSMN6(kT/q) x ln (m), where k is the boltzmann constant, T is temperature, and q is the charge constant. Therefore, in the embodiment, the gate-source voltage VGS of the NMOS transistor MN5 is shownMN5And NMOS transistor MN6 gate-source voltage VGSMN6The difference is the second positive temperature coefficient voltage (+) Δ VGS2 generated by the secondary positive temperature coefficient generating circuit 242. Namely (+) Δ VGS2 ═ VGSMN5-VGSMN6＝VDSMN5。
Further, the reference standby voltage Vref-inComprises the following steps:
Vref-in＝(-)VNB1+(+)ΔVGS1+(+)ΔVGS2＝VDSMN5+VNB3＝VGSMN1+VDSMN3+VDSMN5。
fig. 3 shows a reference voltage source circuit provided in another embodiment of the present application, and referring to fig. 3, the embodiment is based on fig. 2, and for the mirror circuit 230 shown in fig. 2, the present embodiment includes a PMOS transistor MP, a gate of the PMOS transistor MP is connected to the output terminal of the second current path 212, a source of the PMOS transistor MP is connected to the power supply VDDA, and a drain of the PMOS transistor MP is used for outputting the mirror current ID. For the ptc generating circuit 240 shown in fig. 2, the present embodiment comprises an NMOS transistor MNX and an NMOS transistor MNY connected in series, wherein the drain of the NMOS transistor MNX is connected to the source of the NMOS transistor MNY for generating the temperature-independent reference standby voltage Vref-in. The source of the NMOS transistor MNX is connected with the negative temperature coefficient node NB1 of the negative temperature coefficient generation circuit 220, and the gate is connected with the gate of the NMOS transistor MNY and is connected with the NMOS transistorMNY drain, mirror current I output by PMOS transistor MP drainDInto the drain of the NMOS transistor MNY. Wherein, the channel width length ratio (W/L) of the NMOS tube MNYMNYIs the channel width length ratio (W/L) of the MNX of the NMOS tubeMNXM times. In this embodiment, the NMOS transistor MN7 and the NMOS transistor MNY of the second-stage ptc generating circuit 242 form a common-gate amplifier according to the reference preliminary voltage Vref-inAmplifying output reference voltage Vref。
The principle of the embodiment: the negative temperature coefficient voltage (-) VNB1 of the negative temperature coefficient node NB1 in FIG. 3 is equal to the gate-source voltage VGS of the NMOS transistor MN1MN1That is, the negative temperature coefficient voltage (-) VNB1 ═ VGSMN1. Reference preliminary voltage V for PTC generation circuit 240ref-inEqual to MNX drain-source voltage VDS of NMOS tubeMNXThe sum of the negative temperature coefficient voltage (-) VNB1 of the negative temperature coefficient node NB1, i.e., Vref-in＝VDSMN5+ (-) VNB 1. As can be seen from FIG. 3, the drain-source voltage VDS of the NMOS transistor MNXMNXEqual to the gate-source voltage VGS of the MNX of the NMOS tubeMNXAnd NMOS transistor MNY gate-source voltage VGSMNYThe difference, i.e. VDSMNX＝VGSMNX-VGSMNY. Channel width-length ratio (W/L) of NMOS tube MNYMNYIs the channel width length ratio (W/L) of the NMOS tube MNXMNXM times, so that the MNX gate-source voltage VGS of the NMOS transistorMNXAnd NMOS transistor MNY gate-source voltage VGSMNYThe difference is equal to (kT/q) x ln (M), i.e. VDSMNX＝VGSMNX-VGSMNY(kT/q) x ln (m), where k is the boltzmann constant, T is temperature, and q is the charge constant. Therefore, in the embodiment, the gate-source voltage VGS of the NMOS transistor MNXMNXAnd NMOS transistor MNY gate-source voltage VGSMNYThe difference is the positive temperature coefficient voltage (+) Δ VGS generated by the positive temperature coefficient generating circuit 240. Namely (+) Δ VGS ═ VGSMNX-VGSMNY＝VDSMNX。
Further, the reference standby voltage Vref-inComprises the following steps:
Vref-in＝(-)VNB1+(+)ΔVGS＝VGSMN1+VDSMNX。
in the embodiment, the positive temperature coefficient generating circuit and the positive temperature coefficient generating circuit are matched to superpose the weights of the positive temperature quantity and the negative temperature quantity, so that a reference voltage irrelevant to temperature can be formed; through the cooperation of the amplifying output circuit and the positive temperature coefficient generating circuit, the reference voltage can be amplified and output according to the reference reserve voltage, so that the driving capability of the reference voltage can be improved, and the precision of the reference voltage output by the circuit can be improved.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (9)

1. A reference voltage source circuit, characterized in that the reference voltage source circuit comprises:
a current mirror circuit including a first current path and a second current path that are mirror images of each other; the first current path is used for generating bias current independent of a power supply according to a second current path;
the mirror circuit is connected with the current mirror circuit and is used for copying the bias current to generate a mirror current;
a negative temperature coefficient generating circuit including a negative temperature coefficient node NB1, the negative temperature coefficient node NB1 being connected between a resistor R1 and the current mirror circuit, and generating a negative temperature coefficient current at the resistor R1 and a negative temperature coefficient voltage at the negative temperature coefficient node NB1 via the current mirror circuit;
the mirror current flows through the positive temperature coefficient generating circuit, and the positive temperature coefficient generating circuit can form positive temperature coefficient voltage; the positive temperature coefficient generating circuit is also connected with the negative temperature coefficient node NB1, so that the negative temperature coefficient voltage on the negative temperature coefficient node NB1 is superposed with the positive temperature coefficient voltage weight formed by the positive temperature coefficient generating circuit, and a reference preparatory voltage irrelevant to temperature is output;
the amplifying output circuit is connected with the positive temperature coefficient generating circuit to form a common gate amplifier taking the reference reserve voltage as an input voltage; the amplifying output circuit comprises an NMOS tube MN 7;
the positive temperature coefficient generating circuit comprises a secondary positive temperature coefficient generating circuit;
the secondary positive temperature coefficient generating circuit comprises an NMOS tube MN5 and an NMOS tube MN 6;
the drain electrode of the NMOS tube MN5 is connected with the source electrode of the NMOS tube MN6 and is used for generating a reference preparation voltage irrelevant to temperature;
the grid electrode of the NMOS transistor MN7 is connected with the drain electrode of the NMOS transistor MN6, and forms a common-gate amplifier with the NMOS transistor MN 6;
the drain electrode of the NMOS tube MN7 is connected with a power supply, and the source electrode of the NMOS tube MN7 is used for generating a reference voltage according to the reference preparation voltage.
2. The reference voltage source circuit according to claim 1, wherein said negative temperature coefficient generating circuit further comprises an NMOS transistor MN1 and an NMOS transistor MN 2;
a bias node NB2 is arranged on the first current path;
the grid electrode of the NMOS transistor MN1 is connected with the negative temperature coefficient node NB1, the drain electrode of the NMOS transistor MN is connected with the bias node NB2, and the source electrode of the NMOS transistor MN is grounded;
the gate of the NMOS transistor MN2 is connected to the bias node NB2, the drain is connected to the output end of the second current path, and the source is connected to the negative temperature coefficient node NB 1.
3. The reference voltage source circuit according to claim 1, wherein the positive temperature coefficient generating circuit includes an NMOS transistor MNX and an NMOS transistor MNY;
the source electrode of the NMOS tube MNX is connected with the negative temperature coefficient node NB1, the grid electrode of the NMOS tube MNX is connected with the grid electrode of the NMOS tube MNY and the drain electrode of the NMOS tube MNY, and the mirror image current flows into the drain electrode of the NMOS tube MNY;
the drain of the NMOS MNX and the source of the NMOS MNY are used to form the reference preliminary voltage.
4. The reference voltage source circuit of claim 1, wherein the positive temperature coefficient generating circuit further comprises a primary positive temperature coefficient generating circuit; the mirror image circuit comprises a first mirror image circuit and a second mirror image circuit;
the first mirror image circuit and the second mirror image circuit are respectively connected with the current mirror circuit and are used for respectively copying the bias current to generate a first mirror image current and a second mirror image current;
the first mirror current flows into the primary positive temperature coefficient generating circuit, and the second mirror current flows into the secondary positive temperature coefficient generating circuit;
the primary positive temperature coefficient generating circuit can generate a first positive temperature coefficient voltage, can superpose the negative temperature coefficient voltage on a negative temperature coefficient node NB1 with the first positive temperature coefficient voltage weight, and outputs primary positive and negative temperature quantity weight superposition voltage to the secondary positive temperature coefficient generating circuit at a superposition node NB 3;
the secondary positive temperature coefficient generating circuit can generate a second positive temperature coefficient voltage, and can further weight and overlap the primary positive and negative temperature quantity weight and superposed voltage with the second positive temperature coefficient voltage to generate the reference reserve voltage.
5. The reference voltage source circuit according to claim 4, wherein the first mirror circuit includes a PMOS transistor MP3, and the second mirror circuit includes a PMOS transistor MP 4;
the source of the PMOS transistor MP3 is connected with a power supply, the grid of the PMOS transistor MP3 is connected with the output end of the second current path, and the drain of the PMOS transistor MP3 is used for generating the first mirror current;
the source of the PMOS transistor MP4 is connected to the power supply, the gate is connected to the output of the second current path, and the drain is used to generate the second mirror current.
6. The reference voltage source circuit according to claim 4,
the primary positive temperature coefficient generating circuit comprises an NMOS tube MN3 and an NMOS tube MN 4;
the source of the NMOS transistor MN3 is connected to the negative temperature coefficient node NB1, the gate of the NMOS transistor MN3 is connected to the gate of the NMOS transistor MN4 and to the drain of the NMOS transistor MN4, and the first mirror current flows into the drain of the NMOS transistor MN 4;
the drain electrode of the NMOS transistor MN3 is connected with the source electrode of the NMOS transistor MN4 to form a superposition node NB 3.
7. The reference voltage source circuit according to claim 4,
the source electrode of the NMOS tube MN5 is connected with the superposition node NB3, the gate electrode of the NMOS tube MN5 is connected with the gate electrode of the NMOS tube MN6 and the drain electrode of the NMOS tube MN6, and the second mirror current flows into the drain electrode of the NMOS tube MN 6.
8. The reference voltage source circuit according to claim 1, wherein the amplification output circuit further comprises:
and a gate of the tail current NMOS tube MN8, a drain of the MN8 is connected with the negative temperature coefficient node NB1, a source of the NMOS tube MN7 is connected, and a source of the NMOS tube is grounded.
9. The reference voltage source circuit according to claim 1, wherein the first current path includes a PMOS transistor MP1, the second current path includes a PMOS transistor MP 2;
the source electrode of the PMOS tube MP1 is connected with a power supply, the drain electrode is used for outputting the bias current, and the grid electrode is connected with the grid electrode of the PMOS tube MP 2;
the source electrode of the PMOS tube MP2 is connected with a power supply, the drain electrode of the PMOS tube MP2 is connected with the grid electrode of the PMOS tube MP 3556, and the drain electrode of the PMOS tube MP2 is the output end of the second current path.
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CN115268552B (en) * 2021-04-30 2023-12-19 炬芯科技股份有限公司 Reference voltage and reference current generating circuit, integrated chip and method

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CN102385409A (en) * 2011-10-14 2012-03-21 中国科学院电子学研究所 VGS/R (Voltage Gradient Standard/Reference) type reference source capable of supplying zero-temperature coefficient voltage and current reference at the same time
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CN105786081A (en) * 2016-03-30 2016-07-20 上海华虹宏力半导体制造有限公司 Reference voltage source circuit
CN106997221A (en) * 2016-01-22 2017-08-01 中芯国际集成电路制造(上海)有限公司 Band-gap reference circuit
CN110673685A (en) * 2019-10-23 2020-01-10 广州大学 Ultra-low power consumption voltage reference circuit

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Publication number Priority date Publication date Assignee Title
KR20110081414A (en) * 2010-01-08 2011-07-14 주식회사 파이칩스 Circuit for temperature and process compensation
CN102385409A (en) * 2011-10-14 2012-03-21 中国科学院电子学研究所 VGS/R (Voltage Gradient Standard/Reference) type reference source capable of supplying zero-temperature coefficient voltage and current reference at the same time
CN104699164A (en) * 2013-12-10 2015-06-10 展讯通信（上海）有限公司 Band-gap reference circuit
CN106997221A (en) * 2016-01-22 2017-08-01 中芯国际集成电路制造(上海)有限公司 Band-gap reference circuit
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CN110673685A (en) * 2019-10-23 2020-01-10 广州大学 Ultra-low power consumption voltage reference circuit

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