CN107272811B - A kind of low-temperature coefficient reference voltage source circuit - Google Patents
A kind of low-temperature coefficient reference voltage source circuit Download PDFInfo
- Publication number
- CN107272811B CN107272811B CN201710658669.3A CN201710658669A CN107272811B CN 107272811 B CN107272811 B CN 107272811B CN 201710658669 A CN201710658669 A CN 201710658669A CN 107272811 B CN107272811 B CN 107272811B
- Authority
- CN
- China
- Prior art keywords
- pmos tube
- grid
- tube
- drain electrode
- connect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a kind of low-temperature coefficient reference voltage source circuits, including：Current generating circuit, voltage generation circuit, power supply rejection ratio circuit, the current generating circuit provides electric current to the voltage generation circuit, the power supply rejection ratio circuit provides operating voltage, the voltage generation circuit outputting reference voltage to the current generating circuit and voltage generation circuit.The reference voltage source that the invention obtains is lower than 1V, and has lower temperature coefficient, is able to suppress power supply noise, can provide more stable reference voltage, meets the development trend of current electronic equipment low supply voltage and low-power consumption.
Description
Technical field
The present invention relates to technical field of integrated circuits, in particular to a kind of low-temperature coefficient reference voltage source circuit.
Background technique
Reference voltage source is in many circuits, such as Analogous Integrated Electronic Circuits, digital integrated electronic circuit, modulus hybrid integrated electricity
Road is critically important component part.Its effect in circuit is to generate one not by technique, power supply, temperature change shadow
Loud DC voltage provides voltage for entire circuit, and precision directly influences the performance of entire circuit.Therefore it designs a kind of high
The reference voltage source of performance is necessary, and its performance is mainly affected by temperature.
Band-gap reference technology is a kind of widely used reference voltage source generation technology.Its principle is to utilize bipolar transistor
The base emitter voltage of pipe has negative temperature coefficient, and if two bipolar transistor operations are in unequal current density
Under, the difference of their base emitter voltage has positive temperature coefficient.By selecting suitable parameter to mend the two mutually
It repays, available temperature independent voltage.
The temperature independent electricity of about 1.25V can be generated using the reference voltage source of band-gap reference technology
Pressure.However, actual requirement reference voltage source must with the increase to low-power consumption, low-voltage, the demand of light portable equipment
It must be capable of providing the voltage lower than 1V, traditional reference voltage 1.25V can not receive, low-voltage, low-temperature coefficient, height
Power supply rejection ratio be developing direction in future.
Summary of the invention
The object of the present invention is to provide a kind of low-temperature coefficient reference voltage source circuits, including：Current generating circuit, voltage
Generation circuit, power supply rejection ratio circuit, the current generating circuit provide electric current, the power supply suppression to the voltage generation circuit
System provides operating voltage, the voltage generation circuit outputting reference to the current generating circuit and voltage generation circuit than circuit
Voltage.
Further, the current generating circuit is by the first, second triode, the first, second, third resistance, first, second
PMOS tube composition, under the collector and base stage of first triode, the collector of the second triode and base stage, second resistance
End, 3rd resistor lower end be grounded respectively, the lower end of the first resistor is connect with the emitter of first triode, described
The upper end of first resistor is connect with the drain electrode of the upper end of the 3rd resistor, first PMOS tube respectively, the first PMOS
The source electrode of pipe is connect with the source electrode of second PMOS tube, and the grid of the grid of first PMOS tube and the 2nd PMOS connect
It connects, the drain electrode of second PMOS tube is connect with the emitter of the upper end of the second resistance, second triode respectively.
Further, the voltage generation circuit is made of third, the 4th PMOS tube, the first, second, third NMOS tube, institute
State the source electrode of third PMOS tube respectively with the source electrode of the 4th PMOS tube, the source electrode of first PMOS tube, described second
The source electrode of PMOS tube connects, the grid of the third PMOS tube respectively with the grid of the 4th PMOS tube, the first PMOS
The grid of pipe, second PMOS tube grid connection, the 4th PMOS tube drain electrode respectively with second NMOS tube
Drain electrode, the grid connection of the grid of the second NMOS tube, the first NMOS tube, the grid of second NMOS tube and the first NMOS
The grid of pipe connects, the source electrode of second NMOS tube respectively with the drain electrode of first NMOS tube, the third NMOS tube
Source electrode connection, the source electrode of first NMOS tube connects over the ground, the grid of the third NMOS tube respectively with its drain electrode, described
The drain electrode of third PMOS tube connects, the drain electrode outputting reference voltage of the third NMOS tube.
Further, the power supply rejection ratio circuit is made of the five, the six, the seven, the 8th PMOS tube, bias current sources,
The source electrode of 5th PMOS tube is connect with the source electrode of the 6th PMOS tube, the drain electrode of the 5th PMOS tube respectively with it is described
The first, second, third, fourth, the source electrode of the 8th PMOS tube connects, the drain electrode and the 7th PMOS tube of the 6th PMOS tube
Source electrode connection, the leakage with the grid, the 7th PMOS tube of the 5th PMOS tube respectively of the grid of the 6th PMOS tube
Pole connection, one end of the bias current sources are connect with the drain electrode of the 7th PMOS tube, the other end of the bias current sources,
The drain electrode of 8th PMOS tube connects over the ground respectively.
Further, it is additionally provided with feedback loop, the feedback loop includes operational amplifier, the same phase of the operational amplifier
Input terminal is connect with the drain electrode of described first, the upper end of 3rd resistor, the first PMOS tube respectively, the reverse phase of the operational amplifier
Input terminal is connect with the drain electrode of the upper end of the second resistance, the emitter of the second triode, the second PMOS tube respectively, the fortune
The output end for calculating amplifier is connect with the grid of the 8th PMOS tube.
The beneficial effects of the invention are as follows：The reference voltage source that the invention obtains is lower than 1V, and has lower temperature
Coefficient is able to suppress power supply noise, can provide more stable reference voltage, meet current electronic equipment low supply voltage and
The development trend of low-power consumption.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described.Obviously, described attached drawing is a part of the embodiments of the present invention, rather than is all implemented
Example, those skilled in the art without creative efforts, can also be obtained according to these attached drawings other designs
Scheme and attached drawing.
Fig. 1 is the attachment structure schematic diagram of reference voltage source circuit.
Specific embodiment
It is carried out below with reference to technical effect of the embodiment and attached drawing to design of the invention, specific structure and generation clear
Chu is fully described by, to be completely understood by the purpose of the present invention, feature and effect.Obviously, described embodiment is this hair
Bright a part of the embodiment, rather than whole embodiments, based on the embodiment of the present invention, those skilled in the art are not being paid
Other embodiments obtained, belong to the scope of protection of the invention under the premise of creative work.In addition, be previously mentioned in text
All connection/connection relationships not singly refer to that component directly connects, and referring to can be added deduct according to specific implementation situation by adding
Few couple auxiliary, to form more preferably coupling structure.Each technical characteristic in the invention, in not conflicting conflict
Under the premise of can be with combination of interactions.
Embodiment 1, with reference to Fig. 1, a kind of low-temperature coefficient reference voltage source circuit, including：Current generating circuit a2, voltage
Generation circuit a1, power supply rejection ratio circuit a3, feedback loop a4.
The current generating circuit a2 by first, second triode Q1, Q2, first, second, third resistance R1, R2, R3,
First, second PMOS tube PM1, PM2 composition, the feedback loop a4 are made of operational amplifier OP, the first triode Q1
Collector and base stage, the collector of the second triode Q2 and base stage, the lower end of second resistance R2,3rd resistor R3 lower end point
It is not grounded, the lower end of the first resistor R1 is connect with the emitter of the first triode Q1, and the first resistor R1's is upper
End respectively with the upper end of the 3rd resistor R3, the drain electrode of the first PMOS tube PM1, the operational amplifier OP it is same mutually defeated
Enter end connection, the source electrode of the first PMOS tube PM1 is connect with the source electrode of the second PMOS tube PM2, first PMOS tube
The grid of PM1 is connect with the grid of the second PMOS tube PM2, the drain electrode of the second PMOS tube PM2 respectively with the operation
The emitter connection of the inverting input terminal of amplifier OP, the upper end of the second resistance R2, the second triode Q2.
The voltage generation circuit a1 by third, the 4th PMOS tube PM3, PM4, the first, second, third NMOS tube NM1,
NM2, NM3 composition, the source electrode of the third PMOS tube PM3 respectively with the source electrode of the 4th PMOS tube PM4, the first PMOS
The source electrode connection of the source electrode of pipe PM1, the second PMOS tube PM2, the grid of the third PMOS tube PM3 is respectively with the described 4th
The grid connection of the grid of PMOS tube PM4, the grid of the first PMOS tube PM1, the second PMOS tube PM2, the described 4th
PMOS tube PM4 drain electrode respectively with the drain electrode of the second NMOS tube NM2, the grid of the second NMOS tube NM2, the first NMOS tube
The grid of NM1 connects, and the grid of the second NMOS tube NM2 is connect with the grid of the first NMOS tube NM1, and described second
The source electrode of NMOS tube NM2 is connect with the source electrode of the drain electrode of the first NMOS tube NM1, the third NMOS tube NM3 respectively, described
The source electrode of first NMOS tube NM1 connects over the ground, the grid of the third NMOS tube NM3 respectively with its drain electrode, the third
The drain electrode of PMOS tube PM3 connects, the drain electrode outputting reference voltage Vref of the third NMOS tube NM3.
The power supply rejection ratio circuit a3 is by the five, the six, the seven, the 8th PMOS tube PM5, PM6, PM7, PM8, biased electrical
Stream source Ib composition, the source electrode of the 5th PMOS tube PM5 are connect with the source electrode of the 6th PMOS tube PM6, the 5th PMOS
The source electrode of the source electrode of pipe PM5 and the 6th PMOS tube PM6 are separately connected power vd D, the drain electrode point of the 5th PMOS tube PM5
It is not connect with the source electrode of described first, second, third, fourth, the 8th PMOS tube PM1, PM2, PM3, PM4, PM8, the described 8th
The grid of PMOS tube PM8 is connect with the input terminal of the operational amplifier OP, the drain electrode of the 6th PMOS tube PM6 and described the
The source electrode of seven PMOS tube PM7 connects, the grid of the 6th PMOS tube PM6 respectively with the grid of the 5th PMOS tube PM5, institute
The drain electrode connection of the 7th PMOS tube PM7 is stated, the drain electrode of one end of the bias current sources Ib and the 7th PMOS tube PM7 connect
It connects, the drain electrode of the other end of the bias current sources Ib, the 8th PMOS tube PM8 connects over the ground respectively.
Power supply rejection ratio circuit a3 passes through the current mirror that the five, the 6th PMOS tube PM5, PM6 form, can be in the 5th PMOS
The drain electrode of pipe PM5 provided by current generating circuit a2 and voltage generation circuit a1 replace power vd D operating voltage (i.e. C point
Voltage), the first, second, third, fourth, the 7th PMOS tube PM1, PM2, PM3, PM4, PM7 forms current mirror, bias supply Ib
Electric current is provided for the current mirror, since bias supply Ib is independent current source, unrelated with power vd D, the 8th PMOS tube PM8 passes through
It is cascaded with first, second, third, fourth PMOS tube PM1, PM2, PM3, PM4, so that the leakage of the five, the 6th PMOS tube PM5, PM6
Source voltage is equal, and structure as power supply rejection ratio circuit a3 makes have higher independence between C point voltage and power vd D
Property, reduce influence of the power vd D to C point voltage.
In addition, the feedback loop that operational amplifier OP is constituted also improves the power supply rejection ratio of power supply rejection ratio circuit a3,
When power vd D fluctuation, A, B point voltage generate fine difference, and operational amplifier OP is capable of detecting when between the voltage of A, B two o'clock
Fine difference, and amplified output, so that the 8th PMOS tube PM8 generates the compensation electric current for coping with the fine difference, the benefit
It repays electric current and generates offset voltage in C point, which compensates for the fluctuation of power vd D, until A point voltage keeps stablizing, from
And C point is made to keep stablizing, further reduce the influence of power vd D bring.
In third PMOS tube PM3, the 4th PMOS tube PM4 and the current generating circuit a2 in voltage generation circuit a1
Second PMOS tube PM2 constitutes current mirror, and the current replication for flowing through the second PMOS tube PM2 is divided into voltage generation circuit a1
Not Wei I3, I4, compensated by metal-oxide-semiconductor mobility and threshold voltage temperature effects, the drain electrode from third NMOS tube NM3 is available
Temperature independent reference voltage Vref.
Reference voltage Vref is derived below, term is explained：Vref：Reference voltage；VDS3：It is the leakage of NMOS tube NM3
Source voltage；VDS1：The drain-source voltage of first NMOS tube NM1；VGS1：The gate source voltage of first NMOS tube NM1；VTH：The threshold of NMOS tube
Threshold voltage；μn：The mobility of electronics；μp：The mobility in hole；Cox：Gate capacitance per unit area；W：Conducting channel width；L：It leads
Electric channel length.
Such as Fig. 1 it can be seen that reference voltage is：
Vref=VDS3+VDS1 (1)
The electric current for flowing through the 4th PMOS tube PM4 is：
I4=K2[(VGS1-VTH)VDS1-(VDS1/2)] (2)
Wherein
Ki=μn,pCox(W/L)iI=1,2...
The electric current for flowing through the first NMOS tube NM1 is identical as the electric current of the second NMOS tube NM2, i.e.,：
?
It can be obtained by Fig. 1：
VGS1=VDS1+VGS2 (4)
Above formula (2), (3), (4) formula simultaneous are obtained
It solves
It enables
Then
Again
μn=μn0(T/T0)-2 (6)
Wherein T0It is reference temperature, μ 0 is that temperature is T0The electron mobility for being.μ n reduces as the temperature rises.
(5) formula derivation is obtained
By (6), (7) Shi Ke get
The electric current for flowing through third PMOS tube PM3 is：
?
Again
VOVIt is over-drive voltage, value is that the gate source voltage of metal-oxide-semiconductor subtracts threshold voltage.
It is obtained with (6), (7) formula
9 formula derivations can be obtained
It is a negative value, its size depends on technique.
Finally (1) formula derivation is obtained：
This reference voltage source circuit has 2.7ppm/ within the temperature range of -40~140 DEG C under Hspice emulator
DEG C temperature coefficient, outputting reference voltage is between 550.5mV~550.7mV, supply voltage VDD=1.8V, descends power consumption at room temperature
For 62uW.Meet the future development demand of low-voltage, low-temperature coefficient, high PSRR.
Better embodiment of the invention is illustrated above, but the invention is not limited to the implementation
Example, those skilled in the art can also make various equivalent modifications on the premise of without prejudice to spirit of the invention or replace
It changes, these equivalent variation or replacement are all included in the scope defined by the claims of the present application.
Claims (2)
1. a kind of low-temperature coefficient reference voltage source circuit, which is characterized in that including：Current generating circuit, voltage generation circuit,
Power supply rejection ratio circuit, the current generating circuit provide electric current, the power supply rejection ratio circuit to the voltage generation circuit
Operating voltage, the voltage generation circuit outputting reference voltage are provided to the current generating circuit and voltage generation circuit；
The current generating circuit is made of the first, second triode, the first, second, third resistance, the first, second PMOS tube,
The collector and base stage of first triode, the collector of the second triode and base stage, the lower end of second resistance, 3rd resistor
Lower end be grounded respectively, the lower end of the first resistor is connect with the emitter of first triode, the first resistor
Upper end is connect with the drain electrode of the upper end of the 3rd resistor, first PMOS tube respectively, the source electrode of first PMOS tube with
The source electrode of second PMOS tube connects, and the grid of first PMOS tube is connect with the grid of the 2nd PMOS, and described the
The drain electrode of two PMOS tube is connect with the emitter of the upper end of the second resistance, second triode respectively；
The voltage generation circuit is made of third, the 4th PMOS tube, the first, second, third NMOS tube, the third PMOS tube
Source electrode respectively with the source electrode of the source electrode of the 4th PMOS tube, the source electrode of first PMOS tube, second PMOS tube connect
Connect, the grid of the third PMOS tube respectively with the grid of the 4th PMOS tube, the grid of first PMOS tube, described
The grids of two PMOS tube connects, the drain electrode of the 4th PMOS tube respectively with the drain electrode of second NMOS tube, the second NMOS tube
Grid, the first NMOS tube grid connection, the grid of second NMOS tube connect with the grid of first NMOS tube, institute
The source electrode for stating the second NMOS tube is connect with the source electrode of the drain electrode of first NMOS tube, the third NMOS tube respectively, and described
The source electrode of one NMOS tube connects over the ground, the grid of the third NMOS tube respectively with its drain electrode, the leakage of the third PMOS tube
Pole connection, the drain electrode outputting reference voltage of the third NMOS tube；
The power supply rejection ratio circuit is made of the five, the six, the seven, the 8th PMOS tube, bias current sources, the 5th PMOS
The source electrode of pipe is connect with the source electrode of the 6th PMOS tube, and the drain electrode of the 5th PMOS tube is respectively with described first, second,
Three, the source electrode connection of the four, the 8th PMOS tube, the drain electrode of the 6th PMOS tube are connect with the source electrode of the 7th PMOS tube,
The grid of 6th PMOS tube is connect with the drain electrode of the grid, the 7th PMOS tube of the 5th PMOS tube respectively, described
One end of bias current sources is connect with the drain electrode of the 7th PMOS tube, the other end of the bias current sources, the described 8th
The drain electrode of PMOS tube connects over the ground respectively, the grid of the 7th PMOS tube grid with the first, second, third, fourth PMOS tube respectively
Pole connection.
2. a kind of low-temperature coefficient reference voltage source circuit according to claim 1, it is characterised in that：It is additionally provided with and feeds back to
Road, the feedback loop include operational amplifier, and the non-inverting input terminal of the operational amplifier is electric with described first, third respectively
The upper end of resistance, the first PMOS tube drain electrode connection, the inverting input terminal of the operational amplifier respectively with the second resistance
The drain electrode connection of upper end, the emitter of the second triode, the second PMOS tube, the output end of the operational amplifier and the described 8th
The grid of PMOS tube connects.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710658669.3A CN107272811B (en) | 2017-08-04 | 2017-08-04 | A kind of low-temperature coefficient reference voltage source circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710658669.3A CN107272811B (en) | 2017-08-04 | 2017-08-04 | A kind of low-temperature coefficient reference voltage source circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107272811A CN107272811A (en) | 2017-10-20 |
| CN107272811B true CN107272811B (en) | 2018-11-30 |
Family
ID=60075940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710658669.3A Expired - Fee Related CN107272811B (en) | 2017-08-04 | 2017-08-04 | A kind of low-temperature coefficient reference voltage source circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107272811B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112504494B (en) * | 2020-12-02 | 2023-02-24 | 中国科学院上海高等研究院 | Ultra-low power consumption CMOS temperature sensing circuit |
| CN114578891B (en) * | 2022-05-06 | 2022-07-12 | 苏州贝克微电子股份有限公司 | Circuit capable of reducing temperature influence |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102495659A (en) * | 2011-12-27 | 2012-06-13 | 东南大学 | Exponential temperature compensation low-temperature drift complementary metal oxide semiconductor (CMOS) band-gap reference voltage source |
| CN104035471A (en) * | 2014-06-27 | 2014-09-10 | 东南大学 | Current mode bandgap reference voltage source with subthreshold current compensation function |
| CN105786081A (en) * | 2016-03-30 | 2016-07-20 | 上海华虹宏力半导体制造有限公司 | Reference voltage source circuit |
| CN106125811A (en) * | 2016-06-15 | 2016-11-16 | 北京工业大学 | A kind of ultra-low temperature drift high PSRR bandgap voltage reference |
| CN207037520U (en) * | 2017-08-04 | 2018-02-23 | 佛山科学技术学院 | A kind of low-temperature coefficient reference voltage source circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7233196B2 (en) * | 2003-06-20 | 2007-06-19 | Sires Labs Sdn. Bhd. | Bandgap reference voltage generator |
-
2017
- 2017-08-04 CN CN201710658669.3A patent/CN107272811B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102495659A (en) * | 2011-12-27 | 2012-06-13 | 东南大学 | Exponential temperature compensation low-temperature drift complementary metal oxide semiconductor (CMOS) band-gap reference voltage source |
| CN104035471A (en) * | 2014-06-27 | 2014-09-10 | 东南大学 | Current mode bandgap reference voltage source with subthreshold current compensation function |
| CN105786081A (en) * | 2016-03-30 | 2016-07-20 | 上海华虹宏力半导体制造有限公司 | Reference voltage source circuit |
| CN106125811A (en) * | 2016-06-15 | 2016-11-16 | 北京工业大学 | A kind of ultra-low temperature drift high PSRR bandgap voltage reference |
| CN207037520U (en) * | 2017-08-04 | 2018-02-23 | 佛山科学技术学院 | A kind of low-temperature coefficient reference voltage source circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107272811A (en) | 2017-10-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109450415B (en) | Delay circuit | |
| WO2019104467A1 (en) | Voltage regulator and power supply | |
| US9483069B2 (en) | Circuit for generating bias current | |
| JP2002149252A (en) | Band-gap reference circuit | |
| CN104216455B (en) | For the low-power consumption reference voltage source circuit of 4G communication chip | |
| CN107402594B (en) | Realize the low-power consumption low pressure difference linear voltage regulator of high power supply voltage transformation | |
| CN108874008A (en) | A kind of LDO circuit with double feedbacks | |
| CN110347203A (en) | The band-gap reference circuit of broadband low-power consumption | |
| CN112181036B (en) | Voltage and current reference circuit for anti-radiation scene | |
| CN108055014B (en) | Differential operational amplifier and bandgap reference voltage generating circuit | |
| CN107272811B (en) | A kind of low-temperature coefficient reference voltage source circuit | |
| CN107066006B (en) | A kind of novel band-gap reference circuit structure | |
| CN107783588A (en) | A kind of push-pull type quick response LDO circuit | |
| CN207909011U (en) | Adaptive dynamic bias LDO circuit applied to low-voltage output | |
| RU2461048C1 (en) | Reference voltage source | |
| CN207037520U (en) | A kind of low-temperature coefficient reference voltage source circuit | |
| CN107783586B (en) | Voltage reference source circuit without bipolar transistor | |
| CN207992862U (en) | A kind of push-pull type quick response LDO circuit | |
| CN108829169A (en) | A kind of band gap reference of high PSRR | |
| CN113359942A (en) | Low-power consumption voltage reference circuit | |
| CN103425168A (en) | Voltage-to-current converter | |
| CN207281633U (en) | A kind of current reference circuit | |
| CN109582077B (en) | Low-power-consumption power supply start-reset circuit and reference signal circuit | |
| CN105739586A (en) | Current reference source circuit | |
| CN208621993U (en) | A kind of voltage reference source circuit of no bipolar transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20181130 Termination date: 20210804 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |