CN113359942A - Low-power consumption voltage reference circuit - Google Patents

Abstract

The invention provides a low-power-consumption voltage reference circuit, which is a low-power-consumption voltage reference circuit without a loop, a starting circuit, an operational amplifier and a resistor, and can generate a reference voltage almost irrelevant to temperature. The voltage reference circuit provided by the invention is suitable for being used in a low-power chip.

Description

Low-power consumption voltage reference circuit

Technical Field

The invention relates to the field of integrated circuit design, in particular to a low-power-consumption voltage reference circuit.

Background

In order to ensure that the chip can still maintain normal operation within a specified temperature range, almost all integrated circuits require a temperature-independent reference voltage. The conventional method is realized by adopting a band-gap reference source, and the principle is that two voltages with opposite temperature coefficients are added to obtain a band-gap reference voltage which is approximately zero temperature.

As shown in fig. 1, a bandgap reference circuit with a conventional structure includes PMOS transistors P1, P2, and P3 as current mirrors, wherein the PMOS transistors P1, P2, and P3 have the same size, AMP is an operational amplifier for clamping voltage values of a non-inverting terminal and an inverting terminal, a resistor R1A and a resistor R1B have the same resistance value of R1, and an emitter area of a transistor Q1 is K times of an emitter area of a transistor Q2.

The operational amplifier AMP operates in a deep negative feedback state, so that the voltage VA is VB, the current flowing through the resistor R0 is a current positively correlated with the temperature, and a reference voltage irrelevant to the temperature can be output by adjusting the resistances R0, R1A, R1B and R2, namely R0, R1 and R2. Therefore, the expression of the reference voltage Vref is as shown in equation (S1):

in a low power consumption application environment, the bandgap reference source has many disadvantages: operational amplifier need provide bias current alone, and there is offset voltage between homophase end and the inverting terminal, can make and produce certain deviation when theoretical calculation, secondly, the electric current on each branch road is all very little during the low-power consumption, only nano ampere level, the resistance of the resistance that consequently uses must be very big, make the territory area increase, the resistance mismatch also more obvious moreover, there is the loop in the circuit, there is unstable risk, and finally, this circuit has the degeneracy point, need increase extra starting circuit. Therefore, the conventional bandgap reference structure is no longer suitable for low power consumption application environment, and a new circuit structure needs to be proposed to solve the above existing problems.

Disclosure of Invention

The invention provides a low-power-consumption voltage reference circuit without a loop, a starting circuit, an operational amplifier and a resistor, which can generate a reference voltage almost irrelevant to temperature. The voltage reference circuit provided by the invention is suitable for being used in a low-power chip.

A low power voltage reference circuit comprising: the current reference source is connected with the first current mirror, the first current mirror is connected with the second current mirror and the output voltage reference circuit module, and the second current mirror is connected with the output voltage reference circuit module, and is characterized in that: the current reference source is composed of NMOS tubes NM, NM and NM which are connected in series, the current reference source provides bias current for a first current mirror, a second current mirror and an output voltage reference circuit module, the first current mirror is composed of PMOS tubes PM, PM and PM which are connected in parallel, the second current mirror is composed of NMOS tubes NM, NM and NM which are connected in parallel, the output voltage reference circuit module is composed of NMOS tubes NM and a voltage reference output end Vref, the grids of NM, NM and NM are connected while the grid of NM is grounded, the adjacent sources and drains of NM are connected while the drain of NM is connected, the drain of NM, NM and NM is connected with the grid of PM, the grids of PM, PM and PM are connected with the power source, the drain of PM is connected with the drain of NM, the source of NM is grounded, the drain of PM is connected with the emitter of triode Q, triode Q is connected with the collector of diode, namely the base of triode Q is connected with the collector of triode Q and grounded, the emitter of the triode Q1 is further connected with the gate of NM6, the source of NM6 is connected with the drain of NM7 and the gate of NM8, the source of NM7 is grounded, the source of NM8 is connected with the voltage reference output terminal Vref and the drain of NM9, the source of NM9 is grounded, and the drain of NM6 and the drain of NM8 are connected with the power supply.

Furthermore, the NMOS transistors NM1, NM2, NM3, NM4, NM6, and NM8 are depletion MOS transistors, and the other MOS transistors NM5, NM7, and NM9 are enhancement MOS transistors.

Further, all MOS tubes work in a subthreshold region.

Further, an expression (S2) of a voltage VGS between the gate and the source of the depletion type MOS transistor operating in the sub-threshold region can be derived from a current formula of the MOS transistor, where:

wherein Vth is threshold of depletion type NMOS tubeThe value voltage is negative, n is a subthreshold slope correction factor, VT is a thermal voltage, ID is the current flowing through the depletion type NMOS tube NM1 at the moment, W is the width of the conduction channel of the depletion type NMOS tube, L is the length of the conduction channel of the depletion type NMOS tube, and mu_nFor electron mobility, C_OXIs the gate oxide capacitance per unit area.

Further, the width-to-length ratio of the PMOS transistors PM1, PM2, PM3 is 1: k: 1, the width-length ratio of the NMOS tubes NM5, NM7 and NM9 is 1: n: m

Further, since the threshold voltage of the depletion NMOS transistors NM1, NM2, NM3, NM4, NM6, and NM8 is negative, the gate-source connection of the depletion transistor also turns on the MOS transistor to generate a bias current.

Furthermore, the gate voltage of NM6 is VBE of the emitter-base voltage of transistor Q1, so the formula of the value of voltage reference output terminal Vref is VBE-VGS6-VGS8, VGS6 is the voltage between the gate and the source of NMOS transistor NM6, VGS8 is the voltage between the gate and the source of NMOS transistor NM8, and assuming that the bias currents generated by NM1, NM2, NM3, and NM4 are I, the expression of Vref can be finally found according to the ratio among the current mirrors as shown in (S3):

as can be seen from the equation (S3), the first term VBE is negatively correlated to temperature, the second and third terms | Vth6|, | Vth8| are positively correlated to temperature, and the last term is in a higher-order term relationship to temperature, so that the last term can make a higher-order compensation for the temperature coefficient of VBE by adjusting the value N, M, K and the width-to-length ratio of the NMOS tubes NM6 and NM8, thereby obtaining a reference voltage approximately independent of temperature.

Further, the bias current generated when the number of the NMOS tubes of the current reference source is increased is reduced.

The invention has the beneficial effects that: a low-power-consumption voltage reference circuit is characterized in that NMOS tubes NM1, NM2, NM3 and NM4 are connected in series to provide bias current for other branches, PMOS tubes PM1, PM2 and PM3 are used as current mirrors, PM2 copies the current of PM1 and inputs the current to NM5, NM7 and NM9 copy the current of NM5 and inputs the current to depletion tubes NM6 and NM8 to provide current, PM3 copies the current of PM1 and then flows into a triode Q1, a triode Q1 is connected into a diode structure, a triode 1 and the depletion tubes NM6 and NM8 work together, a reference voltage which is almost independent of temperature is generated at the source of the NMOS tube NM8, the circuit structure is simple, resistors are not used, the layout area of the circuit is greatly reduced, a starting circuit is not needed, no loop exists in the circuit, and the low-power-consumption voltage reference circuit is suitable for low-consumption chips.

Drawings

Fig. 1 is a low power consumption voltage reference circuit of a chip in the prior art.

Fig. 2 is a low power consumption voltage reference circuit according to the present application.

Detailed Description

The following examples are described to aid in the understanding of the present invention. The examples are not intended to, and should not be construed in any way as, limiting the scope of the invention.

In the following description, those skilled in the art will recognize that components may be described throughout this discussion as separate functional units (which may include sub-units), but those skilled in the art will recognize that various components or portions thereof may be divided into separate components or may be integrated together (including being integrated within a single system or component).

Furthermore, connections between components or systems within the figures are not intended to be limited to direct connections. Rather, data between these components may be modified, reformatted, or otherwise changed by the intermediate components. Additionally, additional or fewer connections may be used. It should also be noted that the terms "coupled," "connected," or "input" should be understood to include direct connections, indirect connections through one or more intermediate devices, and wireless connections.

Example 1:

as shown in fig. 1, it is a low power consumption voltage reference circuit of a chip in the prior art; fig. 2 shows a low power consumption voltage reference circuit according to the present application.

A low power voltage reference circuit comprising: the current reference source is connected with the first current mirror, the first current mirror is connected with the second current mirror and the output voltage reference circuit module, and the second current mirror is connected with the output voltage reference circuit module, and is characterized in that: the current reference source is composed of NMOS tubes NM, NM and NM which are connected in series, the current reference source provides bias current for a first current mirror, a second current mirror and an output voltage reference circuit module, the first current mirror is composed of PMOS tubes PM, PM and PM which are connected in parallel, the second current mirror is composed of NMOS tubes NM, NM and NM which are connected in parallel, the output voltage reference circuit module is composed of NMOS tubes NM and a voltage reference output end Vref, the grids of NM, NM and NM are connected while the grid of NM is grounded, the adjacent sources and drains of NM are connected while the drain of NM is connected, the drain of NM, NM and NM is connected with the grid of PM, the grids of PM, PM and PM are connected with the power source, the drain of PM is connected with the drain of NM, the source of NM is grounded, the drain of PM is connected with the emitter of triode Q, triode Q is connected with the collector of diode, namely the base of triode Q is connected with the collector of triode Q and grounded, the emitter of the triode Q1 is further connected with the gate of NM6, the source of NM6 is connected with the drain of NM7 and the gate of NM8, the source of NM7 is grounded, the source of NM8 is connected with the voltage reference output terminal Vref and the drain of NM9, the source of NM9 is grounded, and the drain of NM6 and the drain of NM8 are connected with the power supply.

The NMOS transistors NM1, NM2, NM3, NM4, NM6 and NM8 are depletion type MOS transistors, and the other MOS transistors NM5, NM7 and NM9 are enhancement type MOS transistors.

All MOS tubes work in a subthreshold region.

The current formula of the MOS tube can obtain an expression (S2) of a voltage VGS between the grid electrode and the source electrode of the depletion type MOS tube working in the subthreshold region, wherein the expression is as follows:

wherein, VthIs the threshold voltage of the depletion type NMOS tube and is a negative value, n is a sub-threshold slope correction factor, VT is a thermal voltage, ID is the current flowing through the depletion type NMOS tube NM1 at the moment, W is the width of the conduction channel of the depletion type NMOS tube, L is the length of the conduction channel of the depletion type NMOS tube, mu_nFor electron mobility, C_OXIs the gate oxide capacitance per unit area.

The width-length ratio of the PMOS tubes PM1, PM2 and PM3 is 1: k: 1, the width-length ratio of the NMOS tubes NM5, NM7 and NM9 is 1: n: m

Since the threshold voltage of the depletion type NMOS transistors NM1, NM2, NM3, NM4, NM6 and NM8 is negative, the gate-source connection of the depletion type NMOS transistors to the power ground also enables the MOS transistors to be conducted, and generates bias current.

The gate voltage of NM6 is VBE, which is the voltage between the emitter and the base of transistor Q1, so the formula of the value of voltage reference output terminal Vref is VBE-VGS6-VGS8, VGS6 is the voltage between the gate and the source of NMOS transistor NM6, VGS8 is the voltage between the gate and the source of NMOS transistor NM8, and assuming that the bias current generated by NM1, NM2, NM3, NM4 is I, the expression of Vref can be finally found according to the ratio among the current mirrors as shown in (S3):

as can be seen from the equation (S3), the first term VBE is negatively correlated to temperature, the second and third terms | Vth6|, | Vth8| are positively correlated to temperature, and the last term is in a higher-order term relationship to temperature, so that the last term can make a higher-order compensation for the temperature coefficient of VBE by adjusting the value N, M, K and the width-to-length ratio of the NMOS tubes NM6 and NM8, thereby obtaining a reference voltage approximately independent of temperature.

The invention has the beneficial effects that: a low-power-consumption voltage reference circuit is characterized in that NMOS tubes NM1, NM2, NM3 and NM4 are connected in series to provide bias current for other branches, PMOS tubes PM1, PM2 and PM3 are used as current mirrors, PM2 copies the current of PM1 and inputs the current to NM5, NM7 and NM9 copy the current of NM5 and inputs the current to depletion tubes NM6 and NM8 to provide current, PM3 copies the current of PM1 and then flows into a triode Q1, a triode Q1 is connected into a diode structure, a triode 1 and the depletion tubes NM6 and NM8 work together, a reference voltage which is almost independent of temperature is generated at the source of the NMOS tube NM8, the circuit structure is simple, resistors are not used, the layout area of the circuit is greatly reduced, a starting circuit is not needed, no loop exists in the circuit, and the low-power-consumption voltage reference circuit is suitable for low-consumption chips.

Although a number of aspects and embodiments of the invention have been disclosed, other aspects and embodiments will be apparent to those skilled in the art, and several changes and modifications may be made without departing from the spirit of the invention, which falls within the scope of the invention. The various aspects and embodiments disclosed herein are presented by way of example only and are not intended to limit the present invention, which is in any way subject to the claims.

Claims (8)

1. A low power voltage reference circuit comprising: the current reference source is connected with the first current mirror, the first current mirror is connected with the second current mirror and the output voltage reference circuit module, and the second current mirror is connected with the output voltage reference circuit module, and is characterized in that: the current reference source is composed of NMOS tubes NM, NM and NM which are connected in series, the current reference source provides bias current for a first current mirror, a second current mirror and an output voltage reference circuit module, the first current mirror is composed of PMOS tubes PM, PM and PM which are connected in parallel, the second current mirror is composed of NMOS tubes NM, NM and NM which are connected in parallel, the output voltage reference circuit module is composed of NMOS tubes NM and a voltage reference output end Vref, the grids of NM, NM and NM are connected while the grid of NM is grounded, the adjacent sources and drains of NM are connected while the drain of NM is connected, the drain of NM, NM and NM is connected with the grid of PM, the grids of PM, PM and PM are connected with the power source, the drain of PM is connected with the drain of NM, the source of NM is grounded, the drain of PM is connected with the emitter of triode Q, triode Q is connected with the collector of diode, namely the base of triode Q is connected with the collector of triode Q and grounded, the emitter of the triode Q1 is further connected with the gate of NM6, the source of NM6 is connected with the drain of NM7 and the gate of NM8, the source of NM7 is grounded, the source of NM8 is connected with the voltage reference output terminal Vref and the drain of NM9, the source of NM9 is grounded, and the drain of NM6 and the drain of NM8 are connected with the power supply.

2. The low-power voltage reference circuit of claim 1, wherein: the NMOS transistors NM1, NM2, NM3, NM4, NM6 and NM8 are depletion type MOS transistors, and the other MOS transistors NM5, NM7 and NM9 are enhancement type MOS transistors.

3. The low-power voltage reference circuit of claim 1, wherein: all MOS tubes work in a subthreshold region.

4. The low-power voltage reference circuit of claim 1, wherein: the current formula of the MOS tube can obtain an expression (S2) of a voltage VGS between the grid electrode and the source electrode of the depletion type MOS tube working in the subthreshold region, wherein the expression is as follows:

wherein Vth is the threshold voltage of the depletion type NMOS tube and is a negative value, n is a sub-threshold slope correction factor, VT is a thermal voltage, ID is the current flowing through the depletion type NMOS tube NM1 at the moment, W is the width of the conduction channel of the depletion type NMOS tube, L is the length of the conduction channel of the depletion type NMOS tube, and mu_nFor electron mobility, C_OXIs the gate oxide capacitance per unit area.

5. The low-power voltage reference circuit of claim 1, wherein: the width-length ratio of the PMOS tubes PM1, PM2 and PM3 is 1: k: 1, the width-length ratio of the NMOS tubes NM5, NM7 and NM9 is 1: n: and M.

6. The low-power voltage reference circuit of claim 1, wherein: since the threshold voltage of the depletion type NMOS transistors NM1, NM2, NM3, NM4, NM6 and NM8 is negative, the gate-source connection of the depletion type NMOS transistors to the power ground also enables the MOS transistors to be conducted, and generates bias current.

7. The low-power voltage reference circuit of claim 1, wherein: the gate voltage of NM6 is VBE, which is the voltage between the emitter and the base of transistor Q1, so the formula of the value of voltage reference output terminal Vref is VBE-VGS6-VGS8, VGS6 is the voltage between the gate and the source of NMOS transistor NM6, VGS8 is the voltage between the gate and the source of NMOS transistor NM8, and assuming that the bias current generated by NM1, NM2, NM3, NM4 is I, the expression of Vref can be finally found according to the ratio among the current mirrors as shown in (S3):

as can be seen from the equation (S3), the first term VBE is negatively correlated to temperature, the second and third terms | Vth6|, | Vth8| are positively correlated to temperature, and the last term is in a higher-order term relationship to temperature, so that the last term can make a higher-order compensation for the temperature coefficient of VBE by adjusting the value N, M, K and the width-to-length ratio of the NMOS tubes NM6 and NM8, thereby obtaining a reference voltage approximately independent of temperature.

8. The low-power voltage reference circuit of claim 1, wherein: the bias current is smaller when the number of NMOS tubes of the current reference source is larger.

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