CN106125811A - A kind of ultra-low temperature drift high PSRR bandgap voltage reference - Google Patents

Abstract

A kind of ultra-low temperature drift high PSRR bandgap voltage reference, relates to analogue layout field.Present invention is generally directed to the drift of existing a reference source temperature and PSRR problem, it is proposed that compound settlement.It includes that separate current source circuit, biasing circuit, band gap core circuit and PSRR strengthen branch road；Separate current source circuit is powered for producing the electric current the most unrelated with supply voltage, biasing circuit produces the bias voltage of amplifier in band gap core circuit, band gap core circuit utilizes temperature-compensating to obtain reference voltage, and PSRR strengthens branch road provides the gate bias voltage of band gap core circuit to improve PSRR.The present invention obtains providing the benefit that: greatly reduces the temperature coefficient of band-gap reference, improves PSRR.It is applicable to RF identification power management module.

Description

A kind of ultra-low temperature drift high PSRR bandgap voltage reference

Invention field

The invention belongs to electronic circuit technology field, relate to analogue layout field, ultralow particularly to one Temperature drift high PSRR bandgap voltage reference.

Background technology

Band-gap reference circuit is a very important basic unit module in integrated circuits.This module provides for system DC reference voltage, is widely applied in transducer, phaselocked loop and power management class chip.Its temperature coefficient and anti-power supply Noise immune largely have impact on the performance of other circuit in system, and this just requires to improve the precision of band-gap reference and steady Qualitative, it is the emphasis in the design of Analogous Integrated Electronic Circuits system and difficult point.

Fig. 1 is basic band-gap reference circuit structure, it is provided that the reference voltage insensitive to temperature, supply voltage and PTAT reference current.Its basic ideas are that the temperature characterisitic utilizing audion will have the base-emitter voltage of negative temperature coefficient V_BEΔ V poor with the base-emitter voltage with positive temperature coefficient_BEIt is added with different weights, obtains close to zero-temperature coefficient Reference voltage.PTAT current is Δ V_BEThe bias current with PTAT produced.Its formula is respectively as follows:

Wherein, V_BE1It it is the Base-Emitter of PNP triode Q1 Voltage, k is Boltzmann constant, and T is absolute temperature, and q is unit charge electricity, and N is the ratio of Q2 with Q1 coupled in parallel number, R2, R0 are respectively resistance shown in Fig. 1.

The output voltage that Fig. 1 traditional circuit obtains and temperature relation are opening upwards or downward parabola, only single order Compensating, temperature drift is relatively big, makes the normal work of circuit parameter variations impact additionally, due to the reason such as technique, imbalance.It is thus desirable to it is excellent Change circuit structure, design low-temperature coefficient and the bandgap voltage reference of high PSRR.

Summary of the invention

It is an object of the invention to solve first compensation phase temperature coefficient compared with big and to the poor problem of Power supply rejection, carry Go out a kind of ultra-low temperature drift high PSRR band gap reference voltage source circuit.

For achieving the above object, the technical solution used in the present invention is, a kind of ultra-low temperature drift high PSRR band gap base Reference voltage source, its principle is, utilizes the resistance ratio relevant with temperature, eliminates transistor base by regulation resistance ratio and sends out Emitter voltage V_BETemperature coefficient non-linear, is substantially reduced the temperature coefficient of bandgap voltage reference.For improving PSRR, Increase the i.e. PSRR of PSRR and strengthen branch road, and use feedback control loop to produce the independent current the most unrelated with supply voltage Indirectly providing secondary source voltage, the impact that on insulating power supply, noise brings, to improve PSRR.Integrated circuit includes independence Current source circuit, biasing circuit, band gap core circuit and PSRR strengthen branch road；Wherein,

Separate current source circuit includes: PMOS MP1, MP2, MP3, NMOS tube MN1, operational amplifier A MP, resistance R0； Biasing circuit includes PMOS MB1, MB2, MB3, MB4, NMOS tube MB5, MB6 and resistance RB；Band gap core circuit includes PMOS Pipe MP6, MP7, MP8, MP9, MP13, MP14, MP15, MP16, NMOS tube MN7, MN8, MN9, resistance R1a, R1b, R2a, R2b, R3, PNP triode Q1, Q2, compensate electric capacity Cc and compensate resistance Rc；PSRR strengthens branch road and includes PMOS MP4, MP5, NMOS tube MN2；

Concrete connection is as follows:

PMOS MP1, MP2 source electrode meet supply voltage VDD, and PMOS MP1, MP2 grid are connected and connect operational amplifier A MP Outfan VO1, the drain electrode of NMOS tube MN1 meets the drain electrode of PMOS MP1 and the reverse input end Vin1-of operational amplifier A MP1, NMOS tube MN1 grid meets the drain electrode of PMOS MP2, PMOS MP3 source electrode and operational amplifier A MP positive input Vin1+ i.e. etc. Effect time voltage VDDL, PMOS MP3 grounded drain VSS, PMOS MP3 grid is connected with NMOS tube MN2 grid band gap core The outfan VO2 of operational amplifier in circuit, resistance R0 mono-terminate NMOS tube source electrode, resistance R0 other end ground connection VSS, flow through electricity Stream is separate current；

PMOS MB1, MB2 source electrode are connected VDDL, and the PMOS MB2 grid PMOS MB4 source electrode that is connected produces biasing Voltage Vb1, PMOS MB1 drain electrode connect PMOS MB3 source electrode, PMOS MB3, MB4 grid be connected PMOS MB4 drain electrode, electricity Resistance RB mono-terminates the drain electrode of PMOS MB3 and NMOS tube MB5 grid, resistance RB another termination NMOS tube MB6 grid and NMOS tube MB5 Drain electrode, NMOS tube MB5 source electrode is connected with NMOS tube MB6 source electrode ground connection, and the drain electrode of NMOS tube MB6 connects the drain electrode of PMOS MB4；

PMOS MP6, the source electrode of MP7 are connected VDDL, and PMOS MP6, the grid of MP7 are connected the leakage of PMOS MP6 Pole, the source electrode of PMOS MP8 connects the drain electrode of PMOS MP8, and the source electrode of PMOS MP9 meets the drain electrode of PMOS MP7, resistance R1a One termination PMOS MP8 drain electrode, resistance R1a other end connecting resistance R2a one end, resistance R2a other end connecting resistance R3 one end and PMOS MP14 grid i.e. operational amplifier positive input Vin2+, resistance R1b mono-terminate the drain electrode of PMOS MP9 and i.e. export electricity Pressure V_REF, resistance R1b other end connecting resistance R2b one end, another termination PMOS MP15 grid i.e. operational amplifier of resistance R2b is anti- To input Vin2-and audion Q2 emitter stage, the emitter stage of resistance R3 another termination audion Q1, the collection of audion Q1, Q2 Electrode is connected with base stage and all ground connection, and PMOS MP14, MP15 source electrode are connected the drain electrode of PMOS MP13, PMOS MP13 source electrode Be connected VDDL with PMOS MP16 source electrode, and PMOS MP15, MP16 grid are connected the bias voltage Vb1 of biasing circuit, NMOS tube MN7, MN8 grid be connected NMOS tube MN7 drain electrode and PMOS MP14 drain electrode, NMOS tube MN8, MN7, MN9 source electrode phase Connecting ground, NMOS tube MN9 grid connects the drain electrode of NMOS tube MN8 and is connected with electric capacity Cc one end with the drain electrode of PMOS MP15, and electric capacity Cc is another One terminating resistor Rc one end, another termination NMOS tube MN9 drain electrode of resistance Rc and PMOS MN16 drain, for amplifier output end vo 2；

NMOS tube MN2 grounded drain, PMOS MP5 grid is connected with the drain electrode of drain electrode itself and NMOS tube MN2 and connects The grid that is connected of PMOS MP8 and MP9, the grid of PMOS MP4 is connected with drain electrode itself and connects the source electrode of PMOS MP5, PMOS MP4 source electrode meets VDDL.

Compared with prior art, the present invention PSRR is strengthened branch road combine from time voltage generation circuit and with by different The resistance ratio of temperature coefficient produces the comprehensive of zero-temperature coefficient reference circuit, obtains providing the benefit that: greatly reduce band The temperature coefficient of gap benchmark, improves the PSRR of whole frequency range.

Accompanying drawing explanation

Band-gap reference circuit structure basic for Fig. 1

Fig. 2 circuit theory diagrams of the present invention

The output voltage V of Fig. 3 present invention_REFTemperature characterisitic schematic diagram

The output voltage V of Fig. 4 present invention_REFPower supply rejection ratio characteristics schematic diagram

Detailed description of the invention

With detailed description of the invention, the present invention is further described below in conjunction with the accompanying drawings:

As in figure 2 it is shown, the band-gap reference of the present invention includes: separate current source circuit, PSRR strengthen branch road, biasing circuit and Band gap core circuit；Described separate current source circuit, utilization feedback control loop indirectly provides the current source the most unrelated with voltage, carries For the current source the most unrelated with supply voltage, noise isolation on insulating power supply；Described PSRR strengthens branch road, for band gap core electricity Road provides gate bias voltage；Described biasing circuit, in band gap core circuit operational amplifier provide required for and power supply The bias current that voltage is unrelated；Described band gap core circuit, uses the resistance of different temperature coefficients, by regulating the ratio of resistance Rate, reaches the purpose of high-order compensation, produces reference voltage V_REF；

Physical circuit is as in figure 2 it is shown, wherein, and described separate current source circuit includes NMOS tube MN1, PMOS MP1, MP2, MP3, resistance R0 and amplifier AMP；Described PSRR strengthens branch road and comprises NMOS tube MN2, PMOS MP4, MP5；Described biasing circuit Including NMOS tube MB5, MB6, PMOS MB1, MB2, MB3, MB4 and resistance RB；Described band gap core circuit comprises NMOS tube MN7, MN8, MN9, PMOS MP6, MP7, MP8, MP9, MP13, MP14, MP15, MP16, resistance R1a, R1b, R2a, R2b, R3, Rc, electric capacity Cc and PNP triode Q1, Q2.

Concrete linking relationship is as follows:

Described voltage generation circuit, PMOS MP1 source electrode is connected with PMOS MP2 source electrode supply voltage VDD, PMOS Pipe MP1 drain electrode connects the drain electrode of NMOS tube MN1 and is connected with amplifier AMP inverting input, and NMOS tube MN1 grid connects PMOS MP3 source Pole is connected with amplifier AMP positive input, and resistance R0 mono-terminates NMOS tube MN1 source electrode, and the other end is connected with the drain electrode of PMOS MP3 Ground connection, PMOS MP2 grid is connected with PMOS MP1 grid amplifier AMP output end vo 1, PMOS MP3 grid tape splicing gap core The control voltage Vo2 of electrocardio road output, PMOS MP3 source electrode connects the output time that the drain electrode of PMOS MP2 is time voltage generation circuit Voltage VDDL；

Described PSRR strengthens branch road, and PMOS MP4 source electrode meets time voltage VDDL, and PMOS MP5 source electrode connects PMOS MP4 Grid and drain electrode, the drain electrode of NMOS tube MN2 connects grid and the gate bias voltage of drain electrode generation band gap core circuit of PMOS MP5 Vb2, the control voltage Vo2 of NMOS tube MN2 grid tape splicing gap core circuit output, NMOS tube MN2 source ground；

Described biasing circuit, PMOS MB1, MB2 source electrode are connected and connect time voltage VDDL, PMOS MB1, MB2 grid phase Connect PMOS drain electrode and the amplifier bias voltage Vb1 of PMOS MB4 source electrode generation band gap core circuit, PMOS MB3 source electrode Connect PMOS MB1 drain electrode, PMOS MB3, MB4 grid be connected PMOS MB4 drain electrode with NMOS tube MB6 drain, resistance RB mono- Termination PMOS MB3 drain electrode, another termination NMOS tube MB5 drain and gate is also connected with NMOS tube MB6 grid, NMOS tube MB6 Source electrode is connected with NMOS tube MB5 source electrode ground connection；

Described band gap core circuit, PMOS MP6, MP7 source electrode be connected time voltage VDDL, and PMOS MP7 grid connects PMOS MP6 grid is connected with PMOS MP8 source electrode with drain electrode, and PMOS MP8, the MP9 grid PSRR intensifier circuit that is connected is defeated The grid bias voltage Vb2 gone out, PMOS MP9 source electrode connects the drain electrode of PMOS MP7, and resistance R1a mono-terminates the drain electrode of PMOS MP8, One end of other end connecting resistance R2a, resistance R1b mono-terminates the drain electrode of PMOS MP9 and obtains output voltage V_REF, other end connecting resistance One end of R2b, one end of resistance R2a other end connecting resistance R3 and PMOS MP14 grid, another termination PNP tri-pole of resistance R2b The emitter stage of pipe Q2 and PMOS MP15 grid, the emitter stage of another termination PNP triode Q1 of resistance R3, PNP triode Q1, Q2 Colelctor electrode be connected, base stage be connected and ground connection, PMOS MP14, MP15 source electrode be connected PMOS MP13 drain electrode, PMOS MP13, MP16 grid is connected the bias voltage Vb1 of biasing circuit output, and PMOS MP16, MP13 source electrode are connected time voltage VDDL, NMOS tube MN7, MN8 grid be connected PMOS MP14 drain electrode and NMOS tube MN7 drain electrode, NMOS tube MN8 source electrode and NMOS Pipe MN7 source electrode is connected ground connection, electric capacity Cc mono-terminate PMOS MP15 and NMOS tube MN8 be connected drain electrode and with NMOS tube MN9 grid The most connected, other end connecting resistance Rc one end, another termination NMOS tube MN9 of resistance Rc is controlled with the drain electrode that is connected of PMOS MP16 Voltage Vo2 processed, NMOS tube MN9 source ground.

Below the operation principle of foregoing circuit is illustrated:

Described separate current source circuit, as it is shown on figure 3, amplifier clamper MP1, MP2 drain voltage, make two branch currents with The ratio of its breadth length ratio is proportional, and current source receives the feedback signal that band gap core circuit produces, and has the highest power supply independence, The impact on band gap core circuit of the shielded power supply voltage noise, producing the current source the most unrelated with supply voltage is main body circuit Power supply, improves the PSRR of integrated circuit；

Described biasing circuit analysis: main by NMOS tube MB5, MB6 and resistance R_BObtain electric current I_bias, by its circuit structure :

V_GS5-V_GS6=I_biasR_B (1)

Wherein, V_GS5、V_GS6It is respectively the gate source voltage of MB5, MB6 pipe.

NMOS tube saturation region electric current I again_satFormula is:

$I_{sat}=\frac{1}{2}{\mathrm{\μ}}_n{C}_{ox}\frac{W}{L}{(V_{GS}-V_{TH})}^2---\left(2\right)$

Wherein, μ_nFor NMOS tube channel mobility, C_oxFor the gate oxide capacitance of unit area, W is the width of metal-oxide-semiconductor, and L is The length of metal-oxide-semiconductor, V_GSFor metal-oxide-semiconductor gate source voltage, V_THFor threshold voltage.

By formula (1) and formula (2), obtain bias current I_biasExpression formula be:

$I_{bias}=\frac{2}{{\mathrm{\μ}}_n{C}_{ox}{R_B}^2}\left(\sqrt{{\left(\frac{L}{W}\right)}_5}-\sqrt{{\left(\frac{L}{W}\right)}_6}\right)---\left(3\right)$

Wherein,It is respectively NMOS tube MB5, the length-width ratio of MB6.

By expression formula (3), regulation NMOS tube MB5, the breadth length ratio of MB6 can obtain one unrelated with supply voltage Bias current, PMOS MB1, MB2, MB3, MB4 are common-source common-gate current mirror structures, for the current mirror of 1:1, for band gap core In circuit, amplifier provides mirror image bias current.

Described band gap core circuit analysis: traditional bandgap reference voltage source is first compensation phase, such as Fig. 1, it exports electricity Pressure V_REFExpression formula is:

$V_{REF}=V_{BE1}+\frac{kT}{q}\·\ln N\·\frac{R_2}{R_0}---\left(4\right)$

Wherein transistor V_BEWith temperature relation expression formula it is

$V_{BE}=V_G\left(T_0\right)+\frac{T}{T_0}\[V_{BE}\left(T_0\right)-V_G\left(T_0\right)\]-(\mathrm{\η}-m)\frac{kT}{q}ln\left(\frac{T}{T_0}\right)---\left(5\right)$

Wherein, V_G(T₀) be the band gap voltage of silicon, m is the parameter that silicon migration rate is relevant to temperature, η be relevant with technique with The constant that temperature is unrelated, T₀For reference temperature.

V is obtained by formula (5)_BEThe temperature drift coefficient becoming non-linear relation, first compensation phase to obtain with temperature is higher, for fall Low Drift Temperature Coefficient, the present invention uses the resistance of different temperature coefficients, by regulating the ratio of resistance, reaches the purpose of high-order compensation, such as Fig. 3 Shown in, in figure, PMOS MP6, MP7, MP8, MP9 are current-mirror structure, resistance R_1a、R_1b, R3 be high resistance polysilicon resistance, R_2a、 R_2bConsider to be designed as 8:1 based on domain for p-type diffusion resistance, PNP triode Q1 and Q2 emission area, permissible by circuit theory diagrams Obtain:

V_BE2=V_BE1+IR₃ (6)

$\stackrel{\·}{\·\·}I=\frac{V_{BE2}-V_{BE1}}{R_3}=\frac{V_{T}ln\frac{8I_c}{I_s}{V}_{T}ln\frac{I_c}{I_s}}{R_3}=\frac{V_{T}ln8}{R_3}---\left(7\right)$

Wherein,I_cFor collector current, I_sFor saturation current.

$\stackrel{\·}{\·\·}{V}_{REF}=I\·(R_{1b}+R_{2b})+V_{BE}=V_{T}ln8\frac{R_{1b}}{R_3}+V_{T}ln8\frac{R_{2b}}{R_3}+V_{BE}---\left(8\right)$

Analyzed by formula (8), due to R_1bAnd R₃It is all high resistance polysilicon resistance, so R_1b/R₃Temperature independent, R_2bAnd R₃For Different resistance, diffusion resistance R_2bWith temperature positive correlation, high resistance polysilicon resistance R₃With temperature negative correlation, so R_2b/R₃Can be with temperature Degree changes and changes, and obtains R_2b/R₃Taylor expansion:

$\frac{R_{2b}\left(T\right)}{R_3\left(T\right)}=\frac{R_{2b}\left(T_0\right)}{R_3\left(T_0\right)}\[1+K_{pdiff}(T-T_0)\]\·\[1+K_{poly}(T-T_0)+{K^2}_{poly}{(T-T_0)}^2\]---\left(9\right)$

Wherein, K_polyFor the temperature coefficient of high resistance polysilicon, K_pdiffFor the temperature coefficient of P diffusion resistance, by formula (8) and Formula (9) understands, and changes R_1b/R₃And R_2b/R₃Can significantly optimize the temperature coefficient of band-gap reference；

Described PSRR strengthens branch road analysis: NMOS tube MN2 grid meets amplifier output end vo 2, electric current I_DS2It is and supply voltage Unrelated amount, when supply voltage VDDL changes, the grid voltage of PMOS MP5 can change, i.e. PMOS along with VDDL change The gate voltage of pipe MP9 also changes with VDDL change, thus keeps the electric current I of MP9_P9Constant, i.e. output voltage V_REFKeep steady Fixed, PSRR is greatly improved.

The characteristic of the present invention by simulating, verifying, as shown in Figure 4, in-40～120 DEG C, temperature coefficient is 0.23ppm/℃；PSRR is 91dB when 1KHz, is 32dB when 1MHz, less than 30dB in whole frequency range.

Claims (5)

1. a ultra-low temperature drift high PSRR bandgap voltage reference, it is characterised in that: utilize the resistance relevant with temperature Ratio, eliminates transistor base emitter voltage V by regulation resistance ratio_BETemperature coefficient non-linear, is substantially reduced band gap The temperature coefficient of reference voltage；For improving PSRR, increase the i.e. PSRR of PSRR and strengthen branch road, and use feedback loop Road produces the independent current the most unrelated with supply voltage and indirectly provides secondary source voltage, the shadow that on insulating power supply, noise brings Ring, to improve PSRR；Integrated circuit includes that separate current source circuit, biasing circuit, band gap core circuit and PSRR increase Strong branch road；Wherein,

Separate current source circuit includes: PMOS MP1, MP2, MP3, NMOS tube MN1, operational amplifier A MP, resistance R0；Biasing Circuit includes PMOS MB1, MB2, MB3, MB4, NMOS tube MB5, MB6 and resistance RB；Band gap core circuit includes PMOS MP6, MP7, MP8, MP9, MP13, MP14, MP15, MP16, NMOS tube MN7, MN8, MN9, resistance R1a, R1b, R2a, R2b, R3, PNP triode Q1, Q2, compensate electric capacity Cc and compensate resistance Rc；PSRR strengthens branch road and includes PMOS MP4, MP5, NMOS tube MN2；

Concrete connection is as follows:

PMOS MP1, MP2 source electrode meet supply voltage VDD, and PMOS MP1, MP2 grid are connected and connect the defeated of operational amplifier A MP Going out and hold VO1, the drain electrode of NMOS tube MN1 connects the drain electrode of PMOS MP1 and the reverse input end Vin1-of operational amplifier A MP1, NMOS tube MN1 grid connects the drain electrode of PMOS MP2, PMOS MP3 source electrode and operational amplifier A MP positive input Vin1+ i.e. equivalence time electricity Pressure VDDL, PMOS MP3 grounded drain VSS, PMOS MP3 grid is connected in band gap core circuit with NMOS tube MN2 grid The outfan VO2 of operational amplifier, resistance R0 mono-terminate NMOS tube source electrode, and resistance R0 other end ground connection VSS, it is only for flowing through electric current Vertical electric current；

PMOS MB1, MB2 source electrode are connected VDDL, and the PMOS MB2 grid PMOS MB4 source electrode that is connected produces bias voltage Vb1, PMOS MB1 drain electrode connect PMOS MB3 source electrode, PMOS MB3, MB4 grid be connected PMOS MB4 drain electrode, resistance RB One termination PMOS MB3 drain electrode and NMOS tube MB5 grid, another termination NMOS tube MB6 grid of resistance RB and the leakage of NMOS tube MB5 Pole, NMOS tube MB5 source electrode is connected with NMOS tube MB6 source electrode ground connection, and the drain electrode of NMOS tube MB6 connects the drain electrode of PMOS MB4；

PMOS MP6, the source electrode of MP7 are connected VDDL, and PMOS MP6, the grid of MP7 are connected the drain electrode of PMOS MP6, The source electrode of PMOS MP8 connects the drain electrode of PMOS MP8, and the source electrode of PMOS MP9 connects the drain electrode of PMOS MP7, resistance R1a one end Meet the drain electrode of PMOS MP8, resistance R1a other end connecting resistance R2a one end, resistance R2a other end connecting resistance R3 one end and PMOS Pipe MP14 grid i.e. operational amplifier positive input Vin2+, resistance R1b mono-terminate PMOS MP9 drain electrode i.e. output voltage V_REF, resistance R1b other end connecting resistance R2b one end, another termination PMOS MP15 grid i.e. operational amplifier of resistance R2b is reverse Input Vin2-and audion Q2 emitter stage, the emitter stage of resistance R3 another termination audion Q1, the current collection of audion Q1, Q2 Pole is connected with base stage and all ground connection, and PMOS MP14, MP15 source electrode are connected the drain electrode of PMOS MP13, PMOS MP13 source electrode with PMOS MP16 source electrode is connected VDDL, and PMOS MP15, MP16 grid are connected the bias voltage Vb1, NMOS of biasing circuit Pipe MN7, MN8 grid be connected NMOS tube MN7 drain electrode and PMOS MP14 drain electrode, NMOS tube MN8, MN7, MN9 source electrode are connected Ground, NMOS tube MN9 grid connects the drain electrode of NMOS tube MN8 and is connected with electric capacity Cc one end with the drain electrode of PMOS MP15, the electric capacity Cc other end Connecting resistance Rc one end, another termination NMOS tube MN9 drain electrode of resistance Rc and PMOS MN16 drain, for amplifier output end vo 2；

NMOS tube MN2 grounded drain, PMOS MP5 grid is connected with the drain electrode of drain electrode itself and NMOS tube MN2 and connects PMOS The grid that is connected of MP8 with MP9, the grid of PMOS MP4 is connected with drain electrode itself and connects the source electrode of PMOS MP5, PMOS MP4 Source electrode meets VDDL.

A kind of ultra-low temperature drift high PSRR bandgap voltage reference the most according to claim 1, it is characterised in that: institute State separate current source circuit, amplifier clamper MP1, MP2 drain voltage, make two branch currents proportional to the ratio of its breadth length ratio, Current source receives the feedback signal that band gap core circuit produces, and has the highest power supply independence, shielded power supply voltage noise pair The impact of band gap core circuit, producing the current source the most unrelated with supply voltage is that main body circuit is powered, and improves integrated circuit PSRR.

A kind of ultra-low temperature drift high PSRR bandgap voltage reference the most according to claim 1, it is characterised in that: institute State biasing circuit analysis: main by NMOS tube MB5, MB6 and resistance R_BObtain electric current I_bias, its circuit structure obtain:

V_GS5-V_GS6=I_biasR_B(1) wherein, V_GS5、V_GS6It is respectively the gate source voltage of MB5, MB6 pipe；

NMOS tube saturation region electric current I again_satFormula is:

$I_{sat}=\frac{1}{2}{\mathrm{\μ}}_n{C}_{ox}\frac{W}{L}{(V_{GS}-V_{TH})}^2---\left(2\right)$

Wherein, μ_nFor NMOS tube channel mobility, C_oxFor the gate oxide capacitance of unit area, W is the width of metal-oxide-semiconductor, and L is MOS The length of pipe, V_GSFor metal-oxide-semiconductor gate source voltage, V_THFor threshold voltage；

By formula (1) and formula (2), obtain bias current I_biasExpression formula be:

$I_{bias}=\frac{2}{{\mathrm{\μ}}_n{C}_{ox}{R_B}^2}(\sqrt{{\left(\frac{L}{W}\right)}_5}-\sqrt{{\left(\frac{L}{W}\right)}_6})---\left(3\right)$

Wherein,It is respectively NMOS tube MB5, the length-width ratio of MB6；

By expression formula (3), regulation NMOS tube MB5, the breadth length ratio of MB6 can obtain a biased electrical unrelated with supply voltage Stream, PMOS MB1, MB2, MB3, MB4 are common-source common-gate current mirror structures, for the current mirror of 1:1, in band gap core circuit Amplifier provides mirror image bias current.

A kind of ultra-low temperature drift high PSRR bandgap voltage reference the most according to claim 1, it is characterised in that: institute State the circuit analysis of band gap core: traditional bandgap reference voltage source is first compensation phase, its output voltage V_REFExpression formula is:

$V_{REF}=V_{BE1}+\frac{kT}{q}\·lnN\·\frac{R_2}{R_0}---\left(4\right)$

Wherein transistor V_BEWith temperature relation expression formula it is

$V_{BE}=V_G\left(T_0\right)+\frac{T}{T_0}\[V_{BE}\left(T_0\right)-V_G\left(T_0\right)\]-(\mathrm{\η}-m)\frac{kT}{q}ln\left(\frac{T}{T_0}\right)---\left(5\right)$

Wherein, V_G(T₀) it is the band gap voltage of silicon, m is the parameter that silicon migration rate is relevant to temperature, and η is relevant with technique and temperature Unrelated constant, T₀For reference temperature；

V is obtained by formula (5)_BEThe temperature drift coefficient becoming non-linear relation, first compensation phase to obtain with temperature is higher, for fall Low Drift Temperature system Number, uses the resistance of different temperature coefficients, by regulating the ratio of resistance, reaches the purpose of high-order compensation, PMOS MP6, MP7, MP8, MP9 are current-mirror structure, resistance R_1a、R_1b, R3 be high resistance polysilicon resistance, R_2a、R_2bFor p-type diffusion resistance, PNP Audion Q1 and Q2 emission area consider to be designed as 8:1 based on domain, circuit theory can obtain:

V_BE2=V_BE1+IR₃ (6)

$\stackrel{\·}{\·\·}I=\frac{V_{\mathrm{BE}2}-V_{\mathrm{BE}1}}{R_3}=\frac{V_T\ln \frac{{8I}_c}{I_s}-V_T\ln \frac{I_c}{I_s}}{R_3}=\frac{V_T\ln 8}{R_3}---\left(7\right)$

Wherein,I_cFor collector current, I_sFor saturation current；

$\stackrel{\·}{\·\·}{V}_{\mathrm{REF}}=I\·(R_{1b}+R_{2b})+V_{\mathrm{BE}}=V_T\ln 8\frac{R_{1b}}{R_3}+V_T\ln 8\frac{R_{2B}}{R_3}+V_{\mathrm{BE}}---\left(8\right)$

Analyzed by formula (8), due to R_1bAnd R₃It is all high resistance polysilicon resistance, so R_1b/R₃Temperature independent, R_2bAnd R₃For difference Resistance, diffusion resistance R_2bWith temperature positive correlation, high resistance polysilicon resistance R₃With temperature negative correlation, so R_2b/R₃Can become with temperature Change and change, obtain R_2b/R₃Taylor expansion:

$\frac{R_{2b}\left(T\right)}{R_3\left(T\right)}=\frac{R_{2b}\left(T_0\right)}{R_3\left(T_0\right)}\[1+K_{pdiff}(T-T_0)\]\·\[1+K_{poly}(T-T_0)+{K^2}_{poly}{(T-T_0)}^2\]---\left(9\right)$

Wherein, K_polyFor the temperature coefficient of high resistance polysilicon, K_pdiffFor the temperature coefficient of P diffusion resistance, by formula (8) and formula (9) understand, change R_1b/R₃And R_2b/R₃Can significantly optimize the temperature coefficient of band-gap reference.

A kind of ultra-low temperature drift high PSRR bandgap voltage reference the most according to claim 1, it is characterised in that: institute State PSRR and strengthen branch road analysis: NMOS tube MN2 grid meets amplifier output end vo 2, electric current I_DS2It is the amount unrelated with supply voltage, When supply voltage VDDL changes, the grid voltage of PMOS MP5 can change, i.e. the grid of PMOS MP9 along with VDDL change Voltage also changes with VDDL change, thus keeps the electric current I of MP9_P9Constant, i.e. output voltage V_REFKeeping stable, power supply suppresses Ratio is greatly improved.