CN108646846A - A kind of zero temp shift current biasing circuit - Google Patents
A kind of zero temp shift current biasing circuit Download PDFInfo
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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Abstract
The present invention relates to a kind of zero temp shift current biasing circuits,Including reference voltage generating circuit and bias current generating circuit,Reference voltage generating circuit includes the first metal-oxide-semiconductor,Second metal-oxide-semiconductor,Third metal-oxide-semiconductor,4th metal-oxide-semiconductor,5th metal-oxide-semiconductor,First triode,Second triode,Third transistor,First resistor and second resistance,First metal-oxide-semiconductor,Second metal-oxide-semiconductor,Third metal-oxide-semiconductor uses the structure of cascade,First resistor is connected between the 4th metal-oxide-semiconductor source electrode and the first transistor emitter,The source electrode of 5th metal-oxide-semiconductor connects the emitter of the second triode,Second resistance is connected between the drain electrode of third metal-oxide-semiconductor and third transistor emitter,First triode,Second triode,The base stage and grounded collector of third transistor,Bias current generating circuit includes operational amplifier,6th metal-oxide-semiconductor,7th metal-oxide-semiconductor,8th metal-oxide-semiconductor and 3rd resistor,Reference voltage generating circuit connects the positive input of operational amplifier,3rd resistor is connected between the 6th metal-oxide-semiconductor source electrode and ground.
Description
Technical field
The present invention relates to IC design field more particularly to a kind of current biasing circuits, particularly relate to one
The current biasing circuit of kind zero temp shift.
Background technology
In IC design field, the integrated circuit of various functions nearly all be unable to do without current biasing circuit.At certain
We need to use the current biasing circuit of zero temp shift in a little applications, i.e., the size of current offset not variation with temperature and change
Become.
Common zero temp shift current circuit producing method is as shown in Figure 1, Vref is the reference voltage not being affected by temperature, RA
With the resistance that RB is unlike material, RA is the resistance of positive temperature characterisitic（I.e. the resistance value of RA will become larger when the temperature increases）, RB is
The resistance of negative temperature characteristic（I.e. the resistance value of RB will become smaller when the temperature increases）, the resistance value of RA and RB is properly selected, can be made
Their positive and negative temperature drift is cancelled out each other.Again because Vref is not affected by temperature, so the biasing that we will be affected by temperature
Electric current Io：.However there are a serious problems for the circuit, because RA and RB is the resistance of unlike material, so it
Influenced to be different by technological fluctuation.The resistance value of RA and RB is matched under a certain process conditions makes its temperature drift be 0, works as work
When skill condition changes, the resistance value of RA and RB can may all change, and temperature drift will no longer be zero at this time.
Invention content
The present invention proposes a kind of zero temp shift current biasing circuit for the problems of existing zero temp shift current circuit,
The bias current that the circuit generates is not influenced by temperature, and realizes zero temp shift, while not influenced again by resistance process conditions.
To achieve the goals above, the technical solution adopted by the present invention is a kind of zero temp shift current biasing circuit, including base
Quasi- voltage generation circuit and bias current generating circuit, the reference voltage generating circuit include the first metal-oxide-semiconductor, the second metal-oxide-semiconductor,
Third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the first triode, the second triode, third transistor, first resistor and second
Resistance, first metal-oxide-semiconductor, the second metal-oxide-semiconductor, third metal-oxide-semiconductor use the structure of cascade, and source electrode connects power vd D,
The drain electrode of drain electrode the 4th metal-oxide-semiconductor of connection of first metal-oxide-semiconductor, the grid of the first metal-oxide-semiconductor are connected with drain electrode, the drain electrode of the second metal-oxide-semiconductor
Connect the drain electrode of the 5th metal-oxide-semiconductor, one end of the drain electrode connection second resistance of third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor and the 5th metal-oxide-semiconductor
Grid is connected, and the grid of the 5th metal-oxide-semiconductor is connected with drain electrode, one end of the source electrode connection first resistor of the 4th metal-oxide-semiconductor, first resistor
The other end connect the emitter of the first triode, the source electrode of the 5th metal-oxide-semiconductor connects the emitter of the second triode, second resistance
The other end connection third transistor emitter, the first triode, the second triode, the base stage of third transistor and collector
It is grounded GND, a branch is drawn between the drain electrode and second resistance of third metal-oxide-semiconductor as the defeated of reference voltage generating circuit
Outlet；The bias current generating circuit includes operational amplifier, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor and third electricity
Resistance, the reference voltage generating circuit output end connection operational amplifier positive input, operational amplifier it is reversed defeated
Enter the source electrode of the 6th metal-oxide-semiconductor of end connection, the output end of operational amplifier connects the grid of the 6th metal-oxide-semiconductor, the drain electrode of the 6th metal-oxide-semiconductor
Connect the drain electrode of the 7th metal-oxide-semiconductor, the source electrode of the 7th metal-oxide-semiconductor and the 8th metal-oxide-semiconductor is all connected with power vd D, the 7th metal-oxide-semiconductor and the 8th
The grid of metal-oxide-semiconductor is connected, and the grid of the 7th metal-oxide-semiconductor is connected with drain electrode, and one end of 3rd resistor connects the source electrode of the 6th metal-oxide-semiconductor,
The other end is grounded GND, and the drain electrode of the 8th metal-oxide-semiconductor is drawn to the output end as bias current generating circuit.
As an improvement of the present invention, first metal-oxide-semiconductor, the second metal-oxide-semiconductor, third metal-oxide-semiconductor, the 7th metal-oxide-semiconductor and
Eight metal-oxide-semiconductors are all made of PMOS tube, and the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor are all made of NMOS tube.
As an improvement of the present invention, first metal-oxide-semiconductor, the second metal-oxide-semiconductor, third metal-oxide-semiconductor use breadth length ratio W/L values
Identical PMOS tube, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor use the identical NMOS tube of breadth length ratio W/L values, the 7th metal-oxide-semiconductor
The identical PMOS tube of breadth length ratio W/L values is used with the 8th metal-oxide-semiconductor.
As an improvement of the present invention, first triode, the second triode, third transistor are all made of positive-negative-positive
Triode.
As an improvement of the present invention, the first triode, the second triode, third transistor emitter area ratio be
M：1：1.
As an improvement of the present invention, the first resistor, second resistance and 3rd resistor use identical material system
It forms, first resistor, second resistance are identical with the rate of temperature change of 3rd resistor.
As an improvement of the present invention, the first resistor, second resistance and 3rd resistor are with negative temperature characteristic
Resistance.
As an improvement of the present invention, the rate of temperature change of the 3rd resistor is being less than third transistor emitter junction just
To the rate of temperature change of pressure drop.
As an improvement of the present invention, the value of the 3rd resistor at room temperature is defeated by reference voltage generating circuit
The bias current size of outlet output determines.
Compared with the existing technology, the overall construction design of zero temp shift current biasing circuit proposed by the invention is ingenious, knot
Structure advantages of simple, it is easy to accomplish, performance parameter is reliable and stable, and the bias current generated by this circuit is no longer by production technology
Fluctuation and influence, and bias current is influenced small by temperature change, and variable quantity is only 2% within the temperature range of -20 DEG C ~ 120 DEG C
Left and right.
Description of the drawings
Fig. 1 is existing zero temp shift current circuit.
Fig. 2 is the reference voltage generating circuit structure of the present invention.
Fig. 3 is zero temp shift current biasing circuit proposed by the invention.
Fig. 4 is the Simulation results figure of zero temp shift current biasing circuit proposed by the invention.
Specific implementation mode
In order to deepen the understanding of the present invention and recognize, the invention will be further described below in conjunction with the accompanying drawings and introduces.
As Figure 2-3, a kind of zero temp shift current biasing circuit, including reference voltage generating circuit and bias current generate
Circuit, the reference voltage generating circuit include the first metal-oxide-semiconductor PM0, the second metal-oxide-semiconductor PM1, third metal-oxide-semiconductor PM2, the 4th metal-oxide-semiconductor
NM0, the 5th metal-oxide-semiconductor NM1, the first triode Q0, the second triode Q1, third transistor Q2, first resistor R0 and second resistance
R1, the first metal-oxide-semiconductor PM0, the second metal-oxide-semiconductor PM1, third metal-oxide-semiconductor PM2 use cascade structure, and source electrode connect
The drain electrode of the 4th metal-oxide-semiconductor NM0 of drain electrode connection of power vd D, the first metal-oxide-semiconductor PM0, grid and the drain electrode phase of the first metal-oxide-semiconductor PM0
Even, the drain electrode of the 5th metal-oxide-semiconductor NM1 of drain electrode connection of the second metal-oxide-semiconductor PM1, the drain electrode connection second resistance R1 of third metal-oxide-semiconductor PM2
One end, the grid of the 4th metal-oxide-semiconductor NM0 and the 5th metal-oxide-semiconductor NM1 is connected, and the grid of the 5th metal-oxide-semiconductor NM1 is connected with draining, the 4th
One end of the source electrode connection first resistor R0 of metal-oxide-semiconductor NM0, the other end of first resistor R0 connect the transmitting of the first triode Q0
Pole, the source electrode of the 5th metal-oxide-semiconductor NM1 connect the emitter of the second triode Q1, and the other end of second resistance R1 connects the three or three pole
The emitter of pipe Q2, the first triode Q0, the second triode Q1, the base stage of third transistor Q2 and collector are grounded GND,
Output end of the branch as reference voltage generating circuit is drawn between the drain electrode and second resistance R1 of third metal-oxide-semiconductor PM2；Institute
It includes operational amplifier, the 6th metal-oxide-semiconductor NM2, the 7th metal-oxide-semiconductor PM3, the 8th metal-oxide-semiconductor PM4 and third to state bias current generating circuit
Resistance R2, the reference voltage generating circuit output end connection operational amplifier positive input, operational amplifier it is anti-
Connecting the source electrode of the 6th metal-oxide-semiconductor NM2 to input terminal, the output end of operational amplifier connects the grid of the 6th metal-oxide-semiconductor NM2, and the 6th
The source electrode of the drain electrode of the 7th metal-oxide-semiconductor PM3 of drain electrode connection of metal-oxide-semiconductor NM2, the 7th metal-oxide-semiconductor PM3 and the 8th metal-oxide-semiconductor PM4 are all connected with electricity
The grid of source VDD, the 7th metal-oxide-semiconductor PM3 and the 8th metal-oxide-semiconductor PM4 are connected, and the grid of the 7th metal-oxide-semiconductor PM3 is connected with drain electrode, third
One end of resistance R2 connects the source electrode of the 6th metal-oxide-semiconductor NM2, and the other end is grounded GND, and conduct is drawn in the drain electrode of the 8th metal-oxide-semiconductor PM4
The output end of bias current generating circuit.
Wherein, the first metal-oxide-semiconductor PM0, the second metal-oxide-semiconductor PM1, third metal-oxide-semiconductor PM2, the 7th metal-oxide-semiconductor PM3 and the 8th MOS
Pipe PM4 is all made of PMOS tube, and the 4th metal-oxide-semiconductor NM0, the 5th metal-oxide-semiconductor NM1 and the 6th metal-oxide-semiconductor NM2 are all made of NMOS tube.Into
One step, the first metal-oxide-semiconductor PM0, the second metal-oxide-semiconductor PM1, third metal-oxide-semiconductor PM2 use the identical PMOS tube of breadth length ratio W/L values,
The 4th metal-oxide-semiconductor NM0, the 5th metal-oxide-semiconductor NM1 use the identical NMOS tube of breadth length ratio W/L values, the 7th metal-oxide-semiconductor PM3 and the
Eight metal-oxide-semiconductor PM4 use the identical PMOS tube of breadth length ratio W/L values.
The first triode Q0, the second triode Q1, third transistor Q2 are all made of PNP type triode, and first
Triode Q0, the second triode Q1, third transistor Q2 emitter area ratio be M：1：1.
The first resistor R0, second resistance R1 and 3rd resistor R2 are made using identical material, and first
Resistance R0, second resistance R1 are identical with the rate of temperature change of 3rd resistor R2.In addition, the first resistor R0, second resistance R1
It is the resistance with negative temperature characteristic with 3rd resistor R2.
For reference voltage generating circuit, since the breadth length ratio W/L values of the first metal-oxide-semiconductor PM0, the second metal-oxide-semiconductor PM1 are identical,
Therefore flow through that the 4th metal-oxide-semiconductor NM0, the current value of the 5th metal-oxide-semiconductor NM1 are equal, then the 4th metal-oxide-semiconductor NM0, the 5th metal-oxide-semiconductor NM1
Vgs voltage values are also equal, and then the voltage difference at the both ends first resistor R0 is
VR0=ΔVbe=VT*lnM （1）
Wherein, the emitter voltage that Δ Vbe is Q0 and Q1 is poor.
Again because the breadth length ratio W/L values of the first metal-oxide-semiconductor PM0, third metal-oxide-semiconductor PM2 are identical, so flowing through the electric current also phase of the two
Deng
I2=I0= VR0/R0=lnM*VT/R0 （2）
It can thus be concluded that the reference voltage of reference voltage generating circuit output end output is
Vref=Vbe+I2*R1=Vbe+lnM*VT*R1/R0 （3）
For reference voltage generating circuit, due to 3rd resistor R2 and the electricity that first resistor R0, second resistance R1 are same material
The breadth length ratio W/L values of resistance, the 7th metal-oxide-semiconductor PM3 and the 8th metal-oxide-semiconductor PM4 are identical, therefore, by reference voltage generating circuit output end
The bias current of output is
Io=Vref/R2=(Vbe+lnM*VT*R1/R0)/R2 （4）
Assuming that 3rd resistor R2 is in room temperature（T0）When value be R20, the rate of temperature change of 3rd resistor R2 is m2；Third transistor
Vbe is in room temperature for Q2 emitter junction forward voltage drops（T0）When value be Vbe0, the rate of temperature change of Vbe is m1,3rd resistor R2 and Vbe
All it is negative temperature characteristic.Then：
R2=R20[1-（T-T0）*m2] （5）
R1=R10[1-（T-T0）*m2] （6）
R0=R00[1-（T-T0）*m2] （7）
Vbe=Vbe0[1-（T-T0）*m1] （8）
In addition, according to VT=kT/q, VT=VT0=k/q (about 26mV), obtains when room temperature T0：
VT=kT/q=VT0+(T-T0)k/q （9）
If, n=lnM* R1/R0 will be in the substitution formula 4 of formula 5 ~ 9：
Io=
=（10）
So, in temperature T=T0：
Io0=（11）
Ensure zero temp shift to Io, then when needing arbitrary temp T：
Io=Io0 （12）
If according to axiom A=Aggregative formula 10, formula 11 and formula 12 are derived：
Io =
=（13）
Since first resistor R0 is identical with the rate of temperature change of second resistance R1, coefficient n=lnM*R1/R0 is not by temperature
It influences.Vbe variation with temperature amountsIt is a fixed value in same technique, k/q is about constant 0.087mV/K,
M2 is the fixed temperature coefficient of resistance R2, is determined by technique material.The biased electrical of circuit output when formula 13 is arbitrary temp
Stream, the no longer coefficient containing temperature in formula.
According to formula 11 and formula 12：
Io*R20=Vbe0+nVT0 （14）
According to formula 13
Io*R20*m2=m1-kn/q （15）
It is obtained in conjunction with formula 14 and formula 15：
（Vbe0+nVT0）*m2=m1-kn/q （16）
n=Vbe0*(m1-m2)/( VT0*m2+k/q) （17）
In conclusion the bias current of above-mentioned zero temp shift current biasing circuit output realizes that the constraints of zero temp shift includes：
1）It, must m1 ＞ m2 because of n=lnM* R1/R0 ＞ 0.I.e.：When choosing 3rd resistor R2, the temperature change of material
Rate m2 is necessarily less than the rate of temperature change m1 of Vbe.
2）Coefficient n=lnM* R1/R0 are determined by formula 17.
The zero temp shift current biasing circuit of the present invention is carried out on CSMC 0.25um 60V 2P3MBCD technique platforms
It tests, in the process Vbe variation with temperature rate m1=2.5m；The Vbe0 in temperature T0（For values of the Vbe in T0）=
0.67V；3rd resistor R2 chooses rhr2km_sn_2t types, and the rate of temperature change of the resistance is 1.9m, then meets third electricity
The rate of temperature change for hindering R2 is less than the rate of temperature change of third transistor Q2 emitter junction forward voltage drops.
In addition, the emitter area ratio of the first triode Q0, the second triode Q1 are 8, obtained according to n=lnM* R1/R0
R1/R0 ≌ 1.42, first resistor R0 values are 20Kohm in this experiment, and second resistance R1 values are 28.4Kohm.
Io ≌ 0.747/R20 can be obtained according to formula 15, therefore R20 needs progress value according to Io sizes, in this experiment
In take Io be equal to 10uA, then the resistance value of R20 be 74.7Kohm.
The simulation result of experiment is as shown in figure 4, the bias current Io that bias current generating circuit generates is in room temperature T0
10.01uA, current offset maximum fluctuation is 224.4nA within the temperature range of -20 DEG C ~ 120 DEG C, and variable quantity 2.244% can
To meet general demand of the circuit to zero temp shift bias current.
The technical means disclosed in the embodiments of the present invention is not limited only to the technological means disclosed in the above embodiment, further includes
By the above technical characteristic arbitrarily the formed technical solution of combination.It should be pointed out that for those skilled in the art
For, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also considered as
Protection scope of the present invention.
Claims (9)
1. a kind of zero temp shift current biasing circuit, it is characterised in that：Electricity is generated including reference voltage generating circuit and bias current
Road, the reference voltage generating circuit include the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor,
First triode, the second triode, third transistor, first resistor and second resistance, first metal-oxide-semiconductor, the second metal-oxide-semiconductor,
Third metal-oxide-semiconductor uses the structure of cascade, and source electrode connects power vd D, and the drain electrode of the first metal-oxide-semiconductor connects the 4th metal-oxide-semiconductor
Drain electrode, the grid of the first metal-oxide-semiconductor is connected with drain electrode, and the drain electrode of the second metal-oxide-semiconductor connects the drain electrode of the 5th metal-oxide-semiconductor, third metal-oxide-semiconductor
Drain electrode connection second resistance one end, the grid of the 4th metal-oxide-semiconductor and the 5th metal-oxide-semiconductor is connected, the grid of the 5th metal-oxide-semiconductor and drain electrode
It is connected, one end of the source electrode connection first resistor of the 4th metal-oxide-semiconductor, the other end of first resistor connects the transmitting of the first triode
Pole, the source electrode of the 5th metal-oxide-semiconductor connect the emitter of the second triode, the transmitting of the other end connection third transistor of second resistance
Pole, the first triode, the second triode, the base stage of third transistor and collector are grounded GND, in the drain electrode of third metal-oxide-semiconductor
Output end of the branch as reference voltage generating circuit is drawn between second resistance；The bias current generating circuit packet
Include operational amplifier, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor and 3rd resistor, the reference voltage generating circuit it is defeated
Outlet connects the positive input of operational amplifier, and the reverse input end of operational amplifier connects the source electrode of the 6th metal-oxide-semiconductor, operation
The output end of amplifier connects the grid of the 6th metal-oxide-semiconductor, the drain electrode of drain electrode the 7th metal-oxide-semiconductor of connection of the 6th metal-oxide-semiconductor, the 7th MOS
The source electrode of pipe and the 8th metal-oxide-semiconductor is all connected with power vd D, and the grid of the 7th metal-oxide-semiconductor and the 8th metal-oxide-semiconductor is connected, the grid of the 7th metal-oxide-semiconductor
Pole is connected with drain electrode, and one end of 3rd resistor connects the source electrode of the 6th metal-oxide-semiconductor, and the other end is grounded GND, by the leakage of the 8th metal-oxide-semiconductor
Draw the output end as bias current generating circuit in pole.
2. a kind of zero temp shift current biasing circuit as described in claim 1, which is characterized in that first metal-oxide-semiconductor, second
Metal-oxide-semiconductor, third metal-oxide-semiconductor, the 7th metal-oxide-semiconductor and the 8th metal-oxide-semiconductor are all made of PMOS tube, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor and
Six metal-oxide-semiconductors are all made of NMOS tube.
3. a kind of zero temp shift current biasing circuit as claimed in claim 2, which is characterized in that first metal-oxide-semiconductor, second
Metal-oxide-semiconductor, third metal-oxide-semiconductor use the identical PMOS tube of breadth length ratio W/L values, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor to use breadth length ratio
The identical NMOS tube of W/L values, the 7th metal-oxide-semiconductor and the 8th metal-oxide-semiconductor use the identical PMOS tube of breadth length ratio W/L values.
4. a kind of zero temp shift current biasing circuit as described in claim 1, which is characterized in that first triode, second
Triode, third transistor are all made of PNP type triode.
5. a kind of zero temp shift current biasing circuit as claimed in claim 4, which is characterized in that the first triode, the two or three pole
It manages, the emitter area ratio of third transistor is M：1：1.
6. a kind of zero temp shift current biasing circuit as described in claim 1, which is characterized in that the first resistor, the second electricity
Resistance and 3rd resistor are made using identical material, the rate of temperature change phase of first resistor, second resistance and 3rd resistor
Together.
7. a kind of zero temp shift current biasing circuit as claimed in claim 6, which is characterized in that the first resistor, the second electricity
Resistance and 3rd resistor are the resistance with negative temperature characteristic.
8. a kind of zero temp shift current biasing circuit as claimed in claim 7, which is characterized in that the temperature of the 3rd resistor becomes
Rate is less than the rate of temperature change of third transistor emitter junction forward voltage drop.
9. a kind of zero temp shift current biasing circuit as claimed in claim 7, which is characterized in that the 3rd resistor is in room temperature
The bias current size that is exported by reference voltage generating circuit output end of value determine.
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| CN110275563A (en) * | 2019-07-12 | 2019-09-24 | 苏州锴威特半导体有限公司 | A kind of current biasing circuit with temperature-compensating |
| CN110474536A (en) * | 2019-07-12 | 2019-11-19 | 西安电子科技大学 | A kind of power circuit of high-low pressure conversion |
| CN112162584A (en) * | 2020-08-31 | 2021-01-01 | 江苏东海半导体科技有限公司 | Current bias circuit with adjustable and compensable current value |
| CN113114117A (en) * | 2021-04-08 | 2021-07-13 | 唐太平 | Biasing circuit for common-gate tube of cascode radio-frequency low-noise amplifier |
| CN113257179A (en) * | 2021-05-24 | 2021-08-13 | 中科芯集成电路有限公司 | Zero-temperature-drift current circuit for built-in resistor of LED display driving chip |
| CN114578112A (en) * | 2022-04-29 | 2022-06-03 | 深圳市鼎阳科技股份有限公司 | Attenuation temperature drift method for digital oscilloscope and digital oscilloscope |
| CN114756080A (en) * | 2022-04-21 | 2022-07-15 | 上海华虹宏力半导体制造有限公司 | Bias current generating circuit and current supply circuit |
| CN114764261A (en) * | 2021-01-14 | 2022-07-19 | 浙江聚芯集成电路有限公司 | Constant-temperature reference current source with zero temperature drift coefficient |
| CN114995568A (en) * | 2022-07-11 | 2022-09-02 | 上海必阳科技有限公司 | Current source with negative linear rate adjustment rate |
| CN116149420A (en) * | 2023-03-10 | 2023-05-23 | 上海艾为电子技术股份有限公司 | Zero temperature drift current generation circuit |
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| CN110275563B (en) * | 2019-07-12 | 2023-09-29 | 苏州锴威特半导体股份有限公司 | Current bias circuit with temperature compensation |
| CN110474536A (en) * | 2019-07-12 | 2019-11-19 | 西安电子科技大学 | A kind of power circuit of high-low pressure conversion |
| CN110275563A (en) * | 2019-07-12 | 2019-09-24 | 苏州锴威特半导体有限公司 | A kind of current biasing circuit with temperature-compensating |
| CN110474536B (en) * | 2019-07-12 | 2024-04-30 | 西安电子科技大学 | High-low voltage conversion power supply circuit |
| CN112162584A (en) * | 2020-08-31 | 2021-01-01 | 江苏东海半导体科技有限公司 | Current bias circuit with adjustable and compensable current value |
| CN112162584B (en) * | 2020-08-31 | 2022-05-20 | 江苏东海半导体科技有限公司 | Current bias circuit with adjustable and compensable current value |
| CN114764261A (en) * | 2021-01-14 | 2022-07-19 | 浙江聚芯集成电路有限公司 | Constant-temperature reference current source with zero temperature drift coefficient |
| CN113114117A (en) * | 2021-04-08 | 2021-07-13 | 唐太平 | Biasing circuit for common-gate tube of cascode radio-frequency low-noise amplifier |
| CN113257179A (en) * | 2021-05-24 | 2021-08-13 | 中科芯集成电路有限公司 | Zero-temperature-drift current circuit for built-in resistor of LED display driving chip |
| CN113257179B (en) * | 2021-05-24 | 2023-02-28 | 中科芯集成电路有限公司 | Zero-temperature-drift current circuit for built-in resistor of LED display driving chip |
| CN114756080B (en) * | 2022-04-21 | 2024-06-07 | 上海华虹宏力半导体制造有限公司 | Bias current generating circuit and current supplying circuit |
| CN114756080A (en) * | 2022-04-21 | 2022-07-15 | 上海华虹宏力半导体制造有限公司 | Bias current generating circuit and current supply circuit |
| CN114578112B (en) * | 2022-04-29 | 2022-07-15 | 深圳市鼎阳科技股份有限公司 | Attenuation temperature drift method for digital oscilloscope and digital oscilloscope |
| CN114578112A (en) * | 2022-04-29 | 2022-06-03 | 深圳市鼎阳科技股份有限公司 | Attenuation temperature drift method for digital oscilloscope and digital oscilloscope |
| CN114995568B (en) * | 2022-07-11 | 2023-11-17 | 苏州华芯半导体科技有限公司 | Current source with negative linear rate adjustment rate |
| CN114995568A (en) * | 2022-07-11 | 2022-09-02 | 上海必阳科技有限公司 | Current source with negative linear rate adjustment rate |
| CN116149420A (en) * | 2023-03-10 | 2023-05-23 | 上海艾为电子技术股份有限公司 | Zero temperature drift current generation circuit |
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