CN211979540U

CN211979540U - Simple zero-temperature-drift current bias circuit

Info

Publication number: CN211979540U
Application number: CN202020895777.XU
Authority: CN
Inventors: 周奕彤; 万志兵
Original assignee: Shenzhen Zhouli Electronic Technology Co ltd
Current assignee: Shenzhen Zhouli Electronic Technology Co ltd
Priority date: 2020-05-25
Filing date: 2020-05-25
Publication date: 2020-11-20
Anticipated expiration: 2030-05-25

Abstract

The utility model discloses a simple and easy zero temperature floats current bias circuit, including resistance R1, resistance R2, triode Q1, triode Q2, triode Q3, MOS pipe N1, MOS pipe N2 and MOS pipe N3, resistance R1's one end connecting resistance R2, triode Q2's projecting pole and power VCC, triode Q1's projecting pole is connected to resistance R1's the other end, and triode Q5's projecting pole is connected to resistance R2's the other end, the beneficial effects of the utility model are that: the circuit structure is simple, and the performance parameters are stable and reliable; the generated bias current is not influenced by the fluctuation of the production process any more, and the generated bias current is slightly influenced by the temperature change, and the variation is only about 1.4 percent within the temperature range of minus 40 ℃ to 120 ℃; the circuit needs few devices, and the chip layout area can be reduced by more than 80%.

Description

Simple zero-temperature-drift current bias circuit

Technical Field

The utility model relates to an integrated circuit field specifically is a simple and easy zero temperature drift current biasing circuit.

Background

In the field of integrated circuit design, current bias circuits are almost always kept away for integrated circuits with various functions. In some applications, a zero-temperature-drift current bias circuit is required, i.e., the magnitude of the current bias does not change significantly with temperature.

As shown in fig. 1 and 2, a typical zero-temperature-drift current bias generation method first generates a reference voltage Vref that is not affected by temperature by the bandgap reference circuit of fig. 1. Then, zero temperature drift current bias is generated through the circuit of fig. 2, RA and RB in fig. 2 are resistors of different materials, RA is a resistor with positive temperature characteristics (i.e. the resistance of RA will be larger when the temperature rises), RB is a resistor with negative temperature characteristics (i.e. the resistance of RB will be smaller when the temperature rises), and the positive and negative temperature drifts of RA and RB can be offset by properly selecting the resistances of RA and RB. Since Vref is not affected by temperature, we will get a bias current Io that is not affected by temperature.

But this circuit has a serious problem: since RA and RB are resistances of different materials, they are affected differently by process fluctuations. The resistance values of RA and RB are well matched under a certain process condition, so that the temperature drift of the resistance values is 0, when the process condition fluctuates, the resistance values of RA and RB can change, and the temperature drift is possibly not zero any more. Meanwhile, the circuit has a complex structure, a plurality of required devices and high application cost.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a simple and easy zero temperature floats current bias circuit to solve the problem that proposes among the above-mentioned background art.

In order to achieve the above object, the utility model provides a following technical scheme:

a simple zero-temperature drift current bias circuit comprises a resistor R, a triode Q, an MOS tube N and an MOS tube N, wherein one end of the resistor R is connected with the resistor R, an emitting electrode of the triode Q and a power VCC, the other end of the resistor R is connected with an emitting electrode of the triode Q, a collector electrode of the triode Q is connected with a base electrode of the triode Q and an emitting electrode of the triode Q, a collector electrode of the triode Q is connected with an emitting electrode of the triode Q and a base electrode of the triode Q, a base electrode of the triode Q is connected with a base electrode of the triode Q, a base electrode of the triode Q and a drain electrode of the MOS tube N, a collector electrode of the triode Q, a drain electrode of the MOS tube N, a grid electrode of the MOS tube N and a source electrode of the, the drain of the MOS transistor N3 is connected to the zero temperature drift current output terminal IO.

As a further technical solution of the present invention: the triode Q1, the triode Q2, the triode Q3, the triode Q3 and the triode Q5 are all PNP triodes.

As a further technical solution of the present invention: and the MOS transistor N1, the MOS transistor N2 and the MOS transistor N3 are all NMOS transistors.

As a further technical solution of the present invention: the resistor R1 is a polycrystalline resistor.

As a further technical solution of the present invention: the resistor R2 is a polycrystalline resistor, and the resistor R1 and the resistor R2 are made of the same material.

Compared with the prior art, the beneficial effects of the utility model are that: the circuit structure is simple, and the performance parameters are stable and reliable; the generated bias current is not influenced by the fluctuation of the production process any more, and the generated bias current is slightly influenced by the temperature change, and the variation is only about 1.4 percent within the temperature range of minus 40 ℃ to 120 ℃; the circuit needs few devices, and the chip layout area can be reduced by more than 80%.

Drawings

Fig. 1 is a diagram of a prior art bandgap reference circuit.

Fig. 2 is a circuit diagram of zero temperature drift current bias.

Fig. 3 is a circuit diagram of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 3, embodiment 1: a simple zero-temperature drift current bias circuit comprises a resistor R, a triode Q, an MOS tube N and an MOS tube N, wherein one end of the resistor R is connected with the resistor R, an emitting electrode of the triode Q and a power VCC, the other end of the resistor R is connected with an emitting electrode of the triode Q, a collector electrode of the triode Q is connected with a base electrode of the triode Q and an emitting electrode of the triode Q, a collector electrode of the triode Q is connected with an emitting electrode of the triode Q and a base electrode of the triode Q, a base electrode of the triode Q is connected with a base electrode of the triode Q, a base electrode of the triode Q and a drain electrode of the MOS tube N, a collector electrode of the triode Q, a drain electrode of the MOS tube N, a grid electrode of the MOS tube N and a source electrode of the, the drain of the MOS transistor N3 is connected to the zero temperature drift current output terminal IO.

Since the width-to-length ratios W/L of the NMOS transistors N1-N3 are the same, the current values flowing through N1-N3 are the same,

namely:

i1 ═ I2 ═ Io (equation 2)

I1 is the current flowing through the NMOS tube N1;

i2 is the current flowing through the NMOS tube N2;

io is the current flowing through the NMOS transistor N3 and is also the output current of the circuit of the present invention.

Neglecting the triode base current, it can be seen from fig. 3 that:

the current flowing through the transistor Q3 is equal to the current flowing through the NMOS transistor N2, i.e., IQ3 is equal to I2

The sum of the currents flowing through transistors Q4 and Q5 is equal to the current flowing through NMOS transistor N1,

namely:

IQ4+ IQ5 ═ I1 ═ I2 ═ I0 (formula 3)

According to the theory of bandgap references, IQ4 equals the current flowing through resistor R1:

IQ4 ═ Δ VBE/R1 ═ vtln (k)/R1 (formula 4)

The coefficient K in the equation is an emitter current density ratio of the transistors Q2 and Q1, and is approximately constant.

IQ5 equals the current through resistor R2:

IQ5 ═ VBE/R2 (equation 5)

The resistors R1 and R2 are polycrystalline resistors made of the same material, and have negative temperature coefficients of temperature characteristics:

r ═ R0 [ [1- (T-T0) ] C ] (formula 6)

R is the resistance value of the polycrystalline resistor at the temperature T;

r0 is the resistance of the resistor at room temperature (T0);

c is the temperature coefficient of the resistor;

in formula 4, VT is KT/q, which is a positive temperature coefficient of about 0.087 mV/deg.c, and R1 is a negative temperature coefficient, so current IQ4 is inevitably a positive temperature coefficient.

In equation 5, VBE is a negative temperature coefficient of about-2 mV/deg.C, and the temperature coefficient C defining poly resistance is <2m, then current IQ5 must be a negative temperature coefficient.

The output current of the circuit of the invention is obtained by integrating the formula 3, the formula 4, the formula 5 and the formula 6:

io IQ4+ IQ5 vtln (k)/R1+ VBE/R2 (formula 7)

By properly designing the resistance ratio of the resistors R1 and R2, the positive and negative temperature coefficients of IQ4 and IQ5 can be cancelled out, so as to obtain an output current Io with an approximately zero temperature coefficient.

The utility model discloses the qualification of circuit does: the temperature coefficient of the polycrystalline resistance C must be less than 2m, and there is no requirement for a specific value of C.

In example 2, in addition to example 1, Q1 to Q5 in fig. 3 are PNP transistors, and the emitter area ratio thereof is M: 1: 1: 1: 1. n1, N2 and N3 are NMOS tubes, and the width-to-length ratio W/L values of the NMOS tubes are the same. R1 and R2 are polycrystalline resistors of the same material.

It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. A simple zero-temperature drift current bias circuit comprises a resistor R, a triode Q, an MOS tube N and an MOS tube N, and is characterized in that one end of the resistor R is connected with the resistor R, an emitting electrode of the triode Q and a power supply VCC, the other end of the resistor R is connected with an emitting electrode of the triode Q, a collector electrode of the triode Q is connected with a base electrode of the triode Q and an emitting electrode of the triode Q, a collector electrode of the triode Q is connected with the emitting electrode of the triode Q and a base electrode of the triode Q, the base electrode of the triode Q is connected with the base electrode of the triode Q, the base electrode of the triode Q and a drain electrode of the MOS tube N, the collector electrode of the triode Q is connected with the drain electrode of the MOS tube N, the grid electrode of the MOS tube N and the source, the drain of the MOS transistor N3 is connected to the zero temperature drift current output terminal IO.

2. The simple zero-temperature-drift current bias circuit of claim 1, wherein the transistor Q1, the transistor Q2, the transistor Q3, the transistor Q3 and the transistor Q5 are PNP transistors.

3. The simple zero-temperature-drift current bias circuit as claimed in claim 1, wherein the MOS transistor N1, the MOS transistor N2 and the MOS transistor N3 are all NMOS transistors.

4. The simple zero-temperature-drift current bias circuit as claimed in claim 1, wherein the resistor R1 is a poly-crystal resistor.

5. The simple zero-temperature-drift current bias circuit as claimed in claim 4, wherein the resistor R2 is a poly-crystal resistor, and the resistor R1 and the resistor R2 are made of the same material.