CN103197716A - Band-gap reference voltage circuit for reducing offset voltage influence - Google Patents

Abstract

A band-gap reference voltage circuit for reducing offset voltage influence is based on a traditional band-gap reference voltage circuit structure and provided with plug-and-play (PNP) triodes Q1, Q2 and Q3, an operational amplifier OP, resistors R1 and R2, and P-channel metal oxide semiconductor tubes M1, M2 and M3. The band-gap reference voltage circuit is characterized in that a resistor R3 and a resistor R5 are respectively added between an emitter and a base of the PNP triodes Q1 and Q2, and a resistor R4 and a resistor R6 are respectively added between the bases of the PNP triodes Q1 and Q2 and the ground. By leading in a divider resistance network, the offset voltage VOS coefficients are structurally reduced, the influence of the offset voltage to the reference voltage is reduced accordingly, and the standard voltage with high accuracy and better stability can be obtained.

Description

A kind of bandgap voltage reference circuit that reduces the offset voltage influence

Technical field

The present invention relates to band-gap reference circuit, especially a kind of bandgap voltage reference circuit that reduces the offset voltage influence belongs to bipolar transistor (BJT) and metal-oxide semiconductor (MOS) (MOS) transistor integrated circuit technical field.

Background technology

There is a kind of traditional bandgap voltage reference circuit as shown in Figure 1 in the prior art, is provided with PNP triode Q1, Q2 and Q3, operational amplifier OP, resistance R 1 and R2, PMOS pipe M1, M2 and M3; PNP triode Q1, the equal ground connection of the base stage of Q2 and Q3 and collector, the emitter of PNP triode Q1 connects the drain electrode (node A) of in-phase input end and the PMOS pipe M1 of amplifier OP by resistance R 1, the emitter of PNP triode Q2 connects the drain electrode (Node B) of inverting input and the PMOS pipe M2 of amplifier OP, the output terminal of operational amplifier OP and PMOS pipe M1, M2, the grid of M3 connects, PMOS manages M1, M2, the source electrode of M3 all is connected power vd D with substrate, and the emitter of PNP triode Q3 is by the drain electrode (node C) of resistance R 2 connection PMOS pipe M3 and as output terminal output reference voltage V _Ref

Fig. 1 principle of work is as follows: the PMOS pipe M1 that breadth length ratio is identical, and M2 and M3 constitute the equal proportion current mirror, make and flow through triode Q1, and the branch current of Q2 and Q3 is equal, i.e. I _Q1=I _Q2=I _Q3The base-emitter voltage of triode Q2 is:

$V_{\mathrm{BE}2}=V_T\ln \left(\frac{I_{Q2}}{I_{S0}}\right)$ (formula 1)

Wherein, V _TBe thermal voltage, be about 26mv, I at normal temperatures _S0For saturation current and its value of triode Q2 is directly proportional with the emitter area of triode.The base-emitter voltage V of triode _BEBe the CTAT(negative temperature coefficient) voltage, at normal temperatures, work as V _BEDuring ≈ 750mV,

The base-emitter voltage of triode Q1 is:

$V_{\mathrm{BE}1}=V_T\ln \left(\frac{I_{Q1}}{{\mathrm{NI}}_{S0}}\right)$ (formula 2)

Wherein, N is the ratio of triode Q1 and Q2 emitter area, and better for the matching that makes triode Q1 and Q2, the N value gets 8 usually.Computing operational amplifier OP works in degree of depth negative feedback, and making in the same way, the voltage of input end and reverse input end node A and B equates that then the pressure drop on the resistance R 1 is:

${\mathrm{\ΔV}}_{\mathrm{BE}}=V_{\mathrm{BE}2}-V_{\mathrm{BE}1}=V_T\ln \left(\frac{I_{Q2}}{I_{S0}}\right)-V_T\ln \left(\frac{I_{Q1}}{{\mathrm{NI}}_{S0}}\right)=V_T\ln N=I_{Q1}{R}_1$ (formula 3)

V again _T=kT/q, k are Boltzmann constants, and q is the electric charge of an electron institute band, V _TTemperature coefficient be:

(formula 4)

Wherein, T ₀=300K is from following formula thermal voltage V as can be known _TPositive temperature coefficient is arranged, so Δ V _BETemperature coefficient also be on the occasion of, and Δ V _BEObtain a PTAT(positive temperature coefficient (PTC) by resistance R 1) electric current I _Q1(voltage commentaries on classics electric current) is because I _Q1=I _Q3, obvious I _Q3Also be the PTAT electric current, I _Q3Flow through resistance R 2 and produce a PTAT voltage (electric current commentaries on classics voltage), this voltage and CTAT voltage V _BE3Addition (voltage summation) has constituted output reference voltage V _Ref:

$V_{\mathrm{ref}}=V_{\mathrm{BE}3}+\frac{R_2}{R_1}{V}_T\ln N$ (formula 5)

Work as V _BE3≈ 750mV during N=8, regulates resistance R 1, and R2 makes

Can arrive approximate temperature independent reference voltage, a V at this moment _Ref≈ 1.2V.

Because computing operational amplifier in-phase end and the asymmetry of end of oppisite phase place branch road and limited gain can make it be subjected to importing the influence of imbalance.When there is offset voltage V in the computing operational amplifier _OsThe time, if V _b=V _a-V _Os, the output reference voltage V after then considering to lack of proper care _{Ref, os}For:

$V_{\mathrm{ref},\mathrm{os}}=V_{\mathrm{BE}3}+\frac{R_2}{R_1}{V}_T\ln N-\frac{R_2}{R_1}{V}_{\mathrm{os}}$ (formula 6)

Offset voltage has been exaggerated R2/R1 doubly, has introduced error in reference voltage, reduces the precision of reference voltage.In addition, offset voltage V _OsItself also can vary with temperature, and the temperature that has therefore increased reference voltage is floated.As can be seen from the above equation, offset voltage V _OsCoefficient and Δ V _BECoefficient identical, offset for satisfying positive and negative temperature coefficient, this coefficient is determined.For example in formula 5, work as V _BE3≈ 750mV gets N=8, then Offset voltage V _Os=± 5mV will cause datum drift Δ V _Ref≈ ± 41.5mV.As seen, offset voltage has been exaggerated 8.3 times, and is bigger to the reference precision influence.

In actual applications, the offset voltage problem can highlight more.Because not only circuit structure can be introduced imbalance, cause that in technology the factor of imbalance also has a lot, as not matching between resistance, transistorized not matching, not the matching etc. of amplifier input stage transistor threshold voltage.

In order to address this problem, prior art mostly is to reduce offset voltage V from the angle that operational amplifier is put in the design computing by the whole bag of tricks _OsValue reduce offset voltage to the influence of reference voltage.Yet, as mentioned above, V _OSBe to be difficult to eliminate fully.

Summary of the invention

The problem that reference voltage is exerted an influence at above-mentioned offset voltage, the invention provides a kind of bandgap voltage reference circuit that reduces the offset voltage influence, its inventive point is by reducing the coefficient of offset voltage, reduces offset voltage shared proportion in reference voltage.

For realizing the object of the invention, the technical scheme of taking is as follows: a kind of bandgap voltage reference circuit that reduces the offset voltage influence, based on traditional bandgap voltage reference circuit structure, be provided with PNP triode Q1, Q2 and Q3, operational amplifier OP, resistance R 1 and R2, PMOS pipe M1, M2 and M3; The base stage of PNP triode Q1, Q2 and Q3 and the equal ground connection of collector, the emitter of PNP triode Q1 connects the drain electrode of in-phase input end and the PMOS pipe M1 of amplifier OP by resistance R 1, the emitter of PNP triode Q2 connects the drain electrode of inverting input and the PMOS pipe M2 of amplifier OP, the output terminal of operational amplifier OP is connected with the grid of PMOS pipe M1, M2, M3, the source electrode of PMOS pipe M1, M2, M3 all is connected power vd D with substrate, and the emitter of PNP triode Q3 is by the drain electrode of resistance R 2 connection PMOS pipe M3 and as output terminal output reference voltage V _RefIt is characterized in that: between the emitter of PNP triode Q1 and Q2 and base stage, set up resistance R 3 and R5 respectively, between the base stage of PNP triode Q1 and Q2 and ground, set up resistance R 4 and R6 respectively.

Described resistance R 3=R5, R4=R6, R3＜R4.

Compared with prior art, the invention has the beneficial effects as follows:

Bandgap voltage reference circuit structure provided by the invention is not to reduce offset voltage from the angle that designs operational amplifier, but start with from more essential band-gap reference structure, realize the base-emitter voltage multiplication of triode by introducing resistance pressure-dividing network, reduce V from structure _OsCoefficient, thereby reduce offset voltage to the influence of reference voltage, have more general significance.

Description of drawings

Fig. 1 is a kind of bandgap voltage reference circuit of the prior art;

Fig. 2 reduces the bandgap voltage reference circuit of offset voltage influence for the present invention;

Fig. 3 is the another kind of embodiment of Fig. 2.

Embodiment

Below in conjunction with accompanying drawing principle of the present invention and feature are described, the example of lifting only is used for explaining the present invention, is not for limiting scope of the present invention.

Referring to Fig. 2, the bandgap voltage reference circuit that the present invention reduces the offset voltage influence comprises PNP triode Q1, Q2 and Q3, PMOS pipe M1, M2 and M3, operational amplifier OP, resistance R ₁, R ₂, R ₃, R ₄, R ₅, R ₆Resistance R 4 is connected across between the base stage and ground of PNP triode Q1, resistance R 3 is connected across between the base stage and emitter of PNP triode Q1, resistance R 6 is connected across between the base stage and ground of PNP triode Q2, resistance R 5 is connected across between the base stage and emitter of PNP triode Q2, the grounded collector of PNP triode Q1, Q2, base stage and the grounded collector of PNP triode Q3, the emitter of PNP triode Q1 passes through resistance R ₁Link to each other with the drain electrode of the in-phase input end of computing operational amplifier OP and PMOS pipe M1 and be designated as node A, the emitter of PNP triode Q2 links to each other with the drain electrode that inverting input and the PMOS of computing operational amplifier OP manage M2 and is designated as Node B, the output terminal of computing operational amplifier OP is connected with the grid of PMOS pipe M1, M2 and M3, and the emitter of PNP triode Q3 passes through resistance R ₂Link to each other with the drain electrode of PMOS pipe M3 and be designated as node C, source electrode and substrate that PMOS manages M1, M2 and M3 meet supply voltage VDD, node C output reference voltage V _Ref

Circuit of the present invention is compared with traditional structure among Fig. 1, between the base stage of PNP triode Q1 and ground and set up resistance R 4, R3 respectively between base stage and the emitter; Between the base stage of PNP triode Q2 and ground and set up resistance R 6, R5 respectively between base stage and the emitter, R3=R5, R4=R6, R3＜R4.

The principle of work of circuit of the present invention is:

The emitter area of supposing PNP triode Q1, Q2 and Q3 in the circuit diagram 2 of the present invention equates with the emitter area of PNP triode Q1, Q2 and Q3 among traditional structure Fig. 1 respectively; Circuit diagram 2 of the present invention flows through the electric current I of each PNP triode _Q1, I _Q2, I _Q3Also all with the electric current I of each PNP triode of traditional structure Fig. 1 _Q1, I _Q2, I _Q3Equate respectively, then the base-emitter voltage V of each PNP triode in the circuit diagram 2 of the present invention _BE1Also equate respectively.By the electric resistance partial pressure principle, the emitter voltage of Q1 is in the circuit diagram 2 of the present invention so

For in traditional band-gap reference circuit

Doubly, the emitter voltage of Q2 is

For in traditional band-gap reference circuit

Doubly.Operational amplifier OP is operated in degree of depth negative feedback makes the voltage of node A and Node B equate, namely

V _A=V _B(formula 7)

Because current mirror pipe M2 has identical breadth length ratio with M1, and for current mirror connects, so I ₁=I ₂, in order to guarantee I _Q1=I _Q2, the electric current that requires to flow through two resistor networks equates, gets here

Then the branch current at operational amplifier OP in-phase end and end of oppisite phase place is:

$I_1=I_2=\frac{\frac{R_5+R_6}{R_5}{V}_{\mathrm{BE}2}-\frac{R_3+R_4}{R_3}{V}_{\mathrm{BE}1}}{R_1}=\frac{R_3+R_4}{R_3}\frac{{\mathrm{\ΔV}}_{\mathrm{BE}}}{R_1}=\frac{R_3+R_4}{R_3}\frac{V_T\ln N}{R_1}$ (formula 8)

V _BE1And V _BE2Be the base-emitter voltage of PNP triode Q1 and Q2, N is the ratio of the emitter area of PNP triode Q1 and Q2,

Finish the voltage-to-current conversion in resistance R 1.I ₁Be proportional to thermal voltage V _T, i.e. I ₁It is the electric current (PTAT electric current) that is directly proportional with absolute temperature.Because current mirror pipe M3 has identical breadth length ratio with M1, M2, and for current mirror connects, therefore

I ₃=I ₁=I ₂(formula 9)

I ₃The resistance R of flowing through ₂Finish the current-voltage conversion, obtain the voltage (PTAT voltage) that is directly proportional with absolute temperature:

$R_2{I}_3=\frac{R_2}{R_1}\frac{R_3+R_4}{R_3}{V}_T\ln N$ (formula 10)

With this PTAT voltage R ₂I ₃With CTAT voltage V _BE3Addition obtains output reference voltage and is:

$V_{\mathrm{ref}}=V_{\mathrm{BE}3}+\frac{R_2}{R_1}\frac{R_3+R_4}{R_3}{V}_T\ln N$ (formula 11)

Work as V _BE3≈ 750mV gets N=8, order

The time can arrive an approximate temperature independent reference voltage, this moment V _Ref≈ 1.2V.

When considering that there is offset voltage V in operational amplifier _OsThe time, output reference voltage V _{Ref, os}For:

$V_{\mathrm{ref},\mathrm{os}}=V_{\mathrm{BE}3}+\frac{R_2}{R_1}\frac{R_3+R_4}{R_3}{V}_T\ln N-\frac{R_2}{R_1}{V}_{\mathrm{os}}$ (formula 12)

It should be noted that with the formula 6 in traditional band-gap circuit and compare offset voltage V in this structure _OsCoefficient only with Δ V _BEThe part coefficient relevant, can reduce the influence of offset voltage by adjusting the ratio of resistance R 1 and R2, when R2/R1＜1, offset voltage is attenuated, rather than as being exaggerated in the traditional structure.When getting V _BE3≈ 750mV gets N=8, R ₄=19R ₃The time, then

Offset voltage V _OsTo cause datum drift Δ V during=± 5mV _Ref≈ ± 2.075mV.In the present invention namely, offset voltage not only is not exaggerated, and be attenuated on the contrary, so the present invention can reduce offset voltage significantly to the influence to reference voltage.In the occasion that degree of accuracy is had relatively high expectations, will

Value be made as dozens or even hundreds of times and can make the influence of offset voltage be down to extremely low.

Fig. 3 is the another kind of embodiment of circuit of the present invention.Change the PNP triode among Fig. 2 into the NPN triode.

Analyze same Fig. 2, obtain output reference voltage and be:

$V_{\mathrm{ref}}=V_{\mathrm{BE}3}+\frac{R_2}{R_1}\frac{R_3+R_4}{R_3}{V}_T\ln N$ (formula 13)

When considering that there is offset voltage V in operational amplifier _OsThe time, output reference voltage V _{Ref, os}For

$V_{\mathrm{ref},\mathrm{os}}=V_{\mathrm{BE}3}+\frac{R_2}{R_1}\frac{R_3+R_4}{R_3}{V}_T\ln N-\frac{R_2}{R_1}{V}_{\mathrm{os}}$ (formula 14)

With Fig. 2 contrast, can find, adopt the NPN triode in the present embodiment, can realize reducing offset voltage equally to the effect of reference voltage influence.

The above is preferred embodiment of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (2)

1. a bandgap voltage reference circuit that reduces the offset voltage influence based on traditional bandgap voltage reference circuit structure, is provided with PNP triode Q1, Q2 and Q3, operational amplifier OP, resistance R 1 and R2, PMOS pipe M1, M2 and M3; The base stage of PNP triode Q1, Q2 and Q3 and the equal ground connection of collector, the emitter of PNP triode Q1 connects the drain electrode of in-phase input end and the PMOS pipe M1 of amplifier OP by resistance R 1, the emitter of PNP triode Q2 connects the drain electrode of inverting input and the PMOS pipe M2 of amplifier OP, the output terminal of operational amplifier OP is connected with the grid of PMOS pipe M1, M2, M3, the source electrode of PMOS pipe M1, M2, M3 all is connected power vd D with substrate, and the emitter of PNP triode Q3 is by the drain electrode of resistance R 2 connection PMOS pipe M3 and as output terminal output reference voltage V _RefIt is characterized in that: between the emitter of PNP triode Q1 and Q2 and base stage, set up resistance R 3 and R5 respectively, between the base stage of PNP triode Q1 and Q2 and ground, set up resistance R 4 and R6 respectively.

2. the bandgap voltage reference circuit of reduction offset voltage influence according to claim 1 is characterized in that: resistance R 3=R5, R4=R6, R3＞R4.

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