CN108052154A - A kind of no amplifier high-order Low Drift Temperature band-gap reference circuit - Google Patents
A kind of no amplifier high-order Low Drift Temperature band-gap reference circuit Download PDFInfo
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- CN108052154A CN108052154A CN201810110308.XA CN201810110308A CN108052154A CN 108052154 A CN108052154 A CN 108052154A CN 201810110308 A CN201810110308 A CN 201810110308A CN 108052154 A CN108052154 A CN 108052154A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
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Abstract
Disclose a kind of no amplifier high-order Low Drift Temperature band-gap reference circuit, including start-up circuit, biasing circuit, PTC circuit, negative temperature parameter circuit, positive temperature coefficient compensation circuit, negative temperature coefficient compensation circuit, using no operational amplifier circuit structure, the power supply rejection ratio (PSRR) of output reference voltage is improved using BJT current mirrors without amplifier high-order Low Drift Temperature band-gap reference circuit for this.Width funtion input of the circuit provided by the invention with 12V~36V, the adjustable wide output voltage of 0~7V generate the reference voltage that temperature coefficient is 5ppm/ DEG C, the extremely low 35mW of power consumption and high-order temperature compensated feature within the temperature range of 75 DEG C~125 DEG C.
Description
Technical field
The invention belongs to integrated circuit fields, are related to a kind of band-gap reference circuit of no amplifier high-order Low Drift Temperature.
Background technology
As high-precision ADC, DAC converter and the basic module in telecommunication circuit, it is band-gap reference circuit
Other circuit modules provide accurately voltage source or a current source.With the rapid development of system integration technology, reference voltage
Source has become indispensable basic circuit mould in extensive, super large-scale integration and nearly all digital simulator system
Block.Its temperature characterisitic and anti-noise jamming ability is to influence the key factor of integrated circuit precision and performance.Traditional band
Gap reference circuit generates the reference voltage that temperature coefficient is 50ppm/ DEG C or so within the temperature range of 0~70 DEG C.In high-precision
ADC, DAC converter and high performance requirements circuit module in, higher is proposed to core power component band-gap reference circuit
It is required that such as more Low Drift Temperature coefficient, wider range of control source and lower power consumption, to meet current high-performance, low-power consumption
Integrated circuit demand of new generation.
In traditional band gap reference voltage source circuit, nuclear structure is managed by BJT, operational amplifier and resistor network structure
Into.To obtain high performance bandgap voltage reference in traditional circuit, high performance operational amplifier is needed in circuit design
Burning voltage this not only adds the difficulty of design, improves complex circuit designs difficulty, and operational amplifier configuration occupy compared with
Large chip area increases design cost, seriously constrains the growth requirement of integrated circuit miniaturization；Operational amplifier is minimum simultaneously
Operating voltage limits the minimum input voltage of band-gap reference circuit.Prior art band gap reference voltage source circuit uses substantially to be contained
Amplifier structural circuit burning voltage, input voltage range is relatively low in 3.3V~5V or so, and temperature coefficient is in 10ppm or so, limit
The circuit mould that band gap reference voltage source circuit is applied to high-precision, the ADC of miniaturization, DAC converter and high performance requirements is made
Block.In order to obtain no amplifier, wide input voltage, small area, low-power consumption, ultra-low temperature drift coefficient band gap reference voltage source circuit,
It needs to design a kind of new band gap reference voltage source circuit, overcomes the technology bottle of current Low Drift Temperature high performance tape gap reference circuit
Neck improves the stability and reliability of band-gap reference.
The content of the invention
In view of one or more problems of the prior art, the present invention provides a kind of no amplifier high-order Low Drift Temperature band gap
Reference source circuit, including：
Start-up circuit, for starting without amplifier high-order Low Drift Temperature band-gap reference circuit；
High-order Low Drift Temperature compensation circuit, for generating positive temperature coefficient electric current and negative temperature parameter current, positive temperature coefficient
Electric current and negative temperature parameter current mutually compensate for generating Low Drift Temperature coefficient, including:Positive temperature coefficient compensation circuit and negative temperature system
Number compensation circuit；And
Bootstrapping biasing circuit, for providing the bias current of Positive and Negative Coefficient Temperature compensation circuit.
High-order Low Drift Temperature compensation circuit includes：
Positive temperature coefficient compensation circuit provides the voltage with ptc characteristics, is mended using positive temperature coefficient voltage
Repay negative temperature coefficient voltage；
Negative temperature coefficient compensation circuit provides the voltage with negative temperature coefficient feature, is mended using negative temperature coefficient voltage
Repay positive temperature coefficient voltage.
It is described without amplifier high-order Low Drift Temperature band-gap reference circuit, wherein, the start-up circuit includes：
First resistor R1, has a first end and a second end, first end be coupled to the first power end receive positive supply, second
End is coupled to the drain electrode of the first NMOS tube MN1 and the grid of the first NMOS tube MN1；
First NMOS tube MN1 has grid, drain electrode and source electrode, and grid is coupled to first resistor R1 second ends, drains
First resistor R1 second ends are coupled to, source electrode is coupled to the first positive-negative-positive bipolar transistor PNP1 emitters；
First positive-negative-positive bipolar transistor PNP1, has emitter, base stage and collector, and emitter is coupled to first
NMOS tube MN1 source electrodes, base stage are coupled to the 3rd bipolar npn transistor npn npn NPN3 base stages and the 4th bipolar npn type crystal
Pipe NPN4 base stages, collector are coupled to second source end and receive negative supply；
Second resistance R2, has a first end and a second end, and first end is coupled to the first power end and receives positive supply, the
Two ends are coupled to the first bipolar npn transistor npn npn NPN1 base stages and the first bipolar npn transistor npn npn NPN1 collectors；
First bipolar npn transistor npn npn NPN1, has collector, base stage and emitter, and collector is coupled to second
Resistance R2 second ends, base stage are coupled to second resistance R2 second ends, and emitter is coupled to the first zener diode D1 first
End and the second bipolar npn transistor npn npn NPN2 base stages；And
Second bipolar npn transistor npn npn NPN2, has base stage, collector and emitter, and base stage is coupled to the first NPN
Type bipolar transistor NPN1 emitters and the first zener diode D1 first ends, collector are coupled to the first power end VIN
Positive supply is received, emitter is coupled to the 3rd bipolar npn transistor npn npn NPN3 base stages and the 4th bipolar npn transistor npn npn
NPN4 base stages.
It is described without amplifier high-order Low Drift Temperature band-gap reference circuit, wherein, the bootstrapping biasing circuit includes：
First PMOS tube MP1, has source electrode, grid and drain electrode, and source electrode is coupled to the first power end VIN and receives positive electricity
Source, grid are coupled to the second positive-negative-positive bipolar transistor PNP2 emitters, and drain electrode is coupled to the ambipolar crystalline substance of the second positive-negative-positive
Body pipe PNP2 emitters；
Second positive-negative-positive bipolar transistor PNP2, has emitter, base stage and collector, and emitter is coupled to first
PMOS tube MP1 grids and the first PMOS tube MP1 drain electrode, base stage be coupled to the 4th positive-negative-positive bipolar transistor PNP4 base stages and
5th positive-negative-positive bipolar transistor PNP5 emitters, collector are coupled to the 3rd positive-negative-positive bipolar transistor PNP3 transmittings
Pole；
3rd positive-negative-positive bipolar transistor PNP3, has emitter, base stage and collector, and emitter is coupled to second
Positive-negative-positive bipolar transistor PNP2 collectors, base stage are coupled to the 5th positive-negative-positive bipolar transistor PNP5 base stages and the 3rd
Bipolar npn transistor npn npn NPN3 collectors, collector are coupled to the 3rd bipolar npn transistor npn npn NPN3 collectors；
Second PMOS tube MP2, has source electrode, grid and drain electrode, and source electrode is coupled to the first PMOS tube MP1 source electrodes and the 6th
Bipolar npn transistor npn npn NPN6 collectors, grid are coupled to the 4th positive-negative-positive bipolar transistor PNP4 emitters, leakage
Pole is coupled to the 4th positive-negative-positive bipolar transistor PNP4 emitters；
4th positive-negative-positive bipolar transistor PNP4, has emitter, base stage and collector, and emitter is coupled to second
PMOS tube MP2 grids and the second PMOS tube MP2 drain electrode, base stage be coupled to the second positive-negative-positive bipolar transistor PNP2 base stages and
5th positive-negative-positive bipolar transistor PNP5 emitters, collector be coupled to the second positive-negative-positive bipolar transistor PNP2 base stages and
5th positive-negative-positive bipolar transistor PNP5 emitters；
5th positive-negative-positive bipolar transistor PNP5, has emitter, base stage and collector, and emitter is coupled to second
Positive-negative-positive bipolar transistor PNP2 base stages and the 4th positive-negative-positive bipolar transistor PNP4 base stages, base stage are coupled to the 3rd PNP
Type bipolar transistor PNP3 base stages and the 5th bipolar npn transistor npn npn NPN5 collectors, collector are coupled to the 4th NPN
Type bipolar transistor NPN4 collectors and the 6th bipolar npn transistor npn npn NPN6 base stages；And
5th bipolar npn transistor npn npn NPN5, has collector, base stage and emitter, and collector is coupled to the 3rd
Positive-negative-positive bipolar transistor PNP3 collectors, the 3rd positive-negative-positive bipolar transistor PNP3 base stages and the 5th ambipolar crystalline substance of positive-negative-positive
Body pipe PNP5 base stages, base stage are coupled to first resistor R1 second ends and the first NMOS tube MN1 drain electrodes, and emitter is coupled to the
Three bipolar npn transistor npn npn NPN3 collectors.
The high-order Low Drift Temperature compensation circuit, wherein, the negative temperature coefficient compensation circuit includes：
First positive-negative-positive bipolar transistor PNP1, has emitter, base stage and collector, and collector is coupled to first
NMOS tube MN1 source electrodes, base stage are coupled to the 3rd bipolar npn transistor npn npn NPN3 base stages and the 4th bipolar npn type crystal
Pipe NPN4 base stages, emitter are coupled to second source end and receive negative supply；
First zener diode D1, has a first end and a second end, and first end is coupled to the first bipolar npn type crystal
Pipe NPN1 emitters and the second bipolar npn transistor npn npn NPN2 base stages, it is negative that second end is coupled to second source end GND receptions
Power supply；
3rd bipolar npn transistor npn npn NPN3, has collector, base stage and emitter, and collector is coupled to the 5th
Bipolar npn transistor npn npn NPN5 emitters, base stage are coupled to the second bipolar npn transistor npn npn NPN2 emitters and the 4th
Bipolar npn transistor npn npn NPN4 base stages, emitter is coupled to the second NMOS tube MN2 grids, the second NMOS tube MN2 drains,
4th resistance R4 second ends；
3rd resistor R3, has a first end and a second end, and first end is coupled to second source end GND and receives negative supply,
Its second end is coupled to the 4th resistance R4 first ends.
4th resistance R4, has a first end and a second end, and first end is coupled to 3rd resistor R3 second ends, second end
It is coupled to the 3rd bipolar npn transistor npn npn NPN3 emitters and the 5th resistance R5 second ends；
5th resistance R5, has a first end and a second end, and first end is coupled to the 3rd bipolar npn transistor npn npn NPN3
Base stage and the 4th bipolar npn transistor npn npn NPN4 base stages, second end are coupled to the 4th resistance R4 second ends；
Second NMOS tube MN2, has grid, drain electrode and source electrode, and drain electrode is coupled to the 3rd bipolar npn transistor npn npn
NPN3 emitters, grid are coupled to the 3rd bipolar npn transistor npn npn NPN3 emitters, and source electrode is coupled to the second positive supply
Noise is held to receive positive supply；And
6th bipolar npn transistor npn npn NPN6, has collector, base stage and emitter, and collector is coupled to second
PMOS tube MP2 grids and the second PMOS tube MP2 source electrodes, base stage are coupled to the 5th positive-negative-positive bipolar transistor PNP5 collectors
With the 4th bipolar npn transistor npn npn NPN4 collectors, emitter is coupled to the second zener diode D2 first ends.
The high-order Low Drift Temperature compensation circuit, wherein, the positive temperature coefficient compensation circuit includes：
4th bipolar npn transistor npn npn NPN4, has collector, base stage and emitter, and collector is coupled to the 5th
Positive-negative-positive bipolar transistor PNP5 collectors, base stage are coupled to the 3rd bipolar npn transistor npn npn NPN3 base stages, the 5th electricity
Resistance R5 first ends and the first positive-negative-positive bipolar transistor PNP1 base stages, emitter are coupled to the 7th bipolar npn transistor npn npn
NPN7 collectors；
7th bipolar npn transistor npn npn NPN7, has collector, base stage and emitter, and collector is coupled to the 4th
Bipolar npn transistor npn npn NPN4 emitters, base stage are coupled to the 6th resistance R6 second ends and the 7th resistance R7 first ends,
Emitter is coupled to second source end GND and receives negative supply；
Second zener diode D2, has a first end and a second end, and first end is coupled to the 6th bipolar npn type crystal
Pipe NPN6 emitters, second end are coupled to the 6th resistance R6 first ends；
6th resistance R6, has a first end and a second end, and first end is coupled to the second zener diode D2 second ends,
Second end is coupled to the 7th resistance R7 first ends；And
7th resistance R7, has a first end and a second end, and first end is coupled to the 6th resistance R6 second ends, second end
It is coupled to second source end GND and receives negative supply.
The positive temperature coefficient compensation circuit, wherein, the second zener diode D2 provides a constant voltage, for defeated
Go out stabilization, so that temperature coefficient is extremely low.
The high-order Low Drift Temperature compensation circuit, wherein, the 6th resistance R6 adjusts negative temperature coefficient, and the 7th resistance R7 is adjusted
Positive temperature coefficient.
Second zener diode includes adjusting temperature coefficient, is the 6th resistance, and the 7th resistance provides zero temperature
Spend the electric current of coefficient.
The 3rd resistor resistance value is equal with the 4th resistance.
Circuit use provided by the invention reduces output base without operational amplifier high-order Low Drift Temperature band-gap reference source circuit
The temperature coefficient of quasi- voltage improves the power supply rejection ratio (PSRR) of output reference voltage using BJT current mirrors.The present invention provides
Circuit with the Width funtion input of 12V~36V, the adjustable wide output voltage of 0~7V, in -75 DEG C~125 DEG C of temperature ranges
The interior temperature coefficient that generates is the reference voltage down to 5ppm/ DEG C, the extremely low 35mW of power consumption and high-order temperature compensated feature.
Description of the drawings
Fig. 1 shows the schematic diagram of existing band-gap reference circuit；
Fig. 2 shows a kind of showing for no amplifier high-order Low Drift Temperature band-gap reference circuit that one embodiment provides according to the present invention
It is intended to；And
Fig. 3 shows the temperature characteristics that one embodiment obtains according to the present invention.
Specific embodiment
Specific embodiment below represents exemplary embodiment of the present invention, and substantially merely illustrative explanation rather than
Limitation.In the following description, in order to provide a thorough understanding of the present invention, a large amount of specific details are elaborated.However, for ability
Domain those of ordinary skill it is evident that：These specific details are not required for the present invention.In other instances,
In order to avoid obscuring the present invention, well known circuit, material or method are not specifically described.
In the description, it is described specific with reference to the embodiment to refer to that " one embodiment " or " embodiment " means
Feature, structure or characteristic are included at least one embodiment of the present invention.Term " in one embodiment " is in specification
In each position occur not all referring to identical embodiment, nor mutually exclusive other embodiment or variable implementation
Example.All features or disclosed all methods disclosed in this specification or in the process the step of, except mutually exclusive feature
And/or beyond step, it can combine in any way.In addition, it should be understood by one skilled in the art that provided herein
Diagram is provided to the purpose of explanation, and diagram is not necessarily drawn to scale.It should be appreciated that when title " element " " connection
To " or during " coupled " to another element, it can be directly connected or coupled to another element or there may be intermediary element.
On the contrary, when claiming element " being directly connected to " or " being directly coupled to " another element, there is no intermediary elements.Identical attached drawing mark
Note indicates identical element.It when claiming " element " " reception " a certain signal, can make directly to receive, switch, electricity can also be passed through
The receptions such as resistance, level displacement shifter, signal processing unit.Term "and/or" used herein includes one or more correlations and lists
Project any and all combination.
Fig. 1 show no amplifier band-gap reference source circuit of the prior art.The circuit includes reference current generating circuit
And output circuit.Reference current generating circuit specifically includes three PMOS tube MP1, MP2 and MP3, two NMOS tubes MN1 and MN2
And zero resistance R0, for providing reference current to output circuit.MP1, MP2 are connected with the source electrode of MP3, and grid is connected, MP1
Drain electrode with MP2 connects the drain electrode of MN1 and MN2 respectively, and the drain and gate of MN1 connects the grid of MN2 respectively.Output circuit bag
The emitter of the triode Q1 and first resistor R1, Q1 that include series connection are connected with R1, base stage and the collector leakage with MP3 respectively of Q1
Extremely it is connected, tie point is as voltage output end.Wherein, the voltage difference between the drain and gate of MP1, MP2 and MP3 is m：m：N,
Voltage difference between MN1 and the drain and gate of MN2 is 1：P, wherein, m, n and p are positive integer.
Since the circuit includes a triode, output voltage VBG has negative temperature coefficient, i.e., bandgap voltage reference is to temperature
The variation of degree is sensitive, and the output voltage of the circuit is poor for the rejection ability of power source change.
The expression formula of bandgap voltage reference VBG is：VBG=VBE (Q2)+[Δ VBE/R1] * R2, wherein, VBE (Q2) is tool
There is the base-emitter voltage of the Q2 of negative temperature coefficient, Δ VBE=ln (N) * kT/e are the base-emitter voltage difference of Q0 and Q1, the voltage difference
With positive temperature coefficient, T is temperature, k=1.38 × 10-23J/K, e=1.6 × 10-19C.By above-mentioned bandgap voltage reference VBG
Expression formula can be seen that obtain desired VBG, it is necessary to temperature coefficient is accurately adjusted, and the tune of temperature coefficient
Save relatively difficult, therefore, which is difficult to realize the adjusting to bandgap voltage reference.It is more for prior art band-gap reference circuit
A technical bottleneck, the present invention provides a kind of no amplifier high-order Low Drift Temperature band-gap reference source circuits, realize no amplifier, wide input electricity
Pressure, small area, low-power consumption, ultra-low temperature drift coefficient overcome the technical bottleneck of current band-gap reference circuit, be high-precision adc,
DAC and other telecommunication circuits provide high performance power module.
Fig. 2 shows no amplifier high-order Low Drift Temperature band-gap reference circuit according to an embodiment of the invention, including：
Start-up circuit, for starting without amplifier high-order Low Drift Temperature band-gap reference circuit；
High-order Low Drift Temperature compensation circuit, for generating positive temperature coefficient electric current and negative temperature parameter current, positive temperature coefficient
Electric current and negative temperature parameter current mutually compensate for generating Low Drift Temperature coefficient, including:Positive temperature coefficient compensation circuit and negative temperature system
Number compensation circuit；And
Bootstrapping biasing circuit, for providing the bias current of Positive and Negative Coefficient Temperature compensation circuit.
High-order Low Drift Temperature compensation circuit includes：
Positive temperature coefficient compensation circuit provides the voltage with ptc characteristics, is mended using positive temperature coefficient voltage
Repay negative temperature coefficient voltage；
Negative temperature coefficient compensation circuit provides the voltage with negative temperature coefficient feature, is mended using negative temperature coefficient voltage
Repay positive temperature coefficient voltage.
Start-up circuit includes：
First resistor R1, has a first end and a second end, and first end is coupled to the first power end VIN and receives positive supply,
Second end is coupled to the drain electrode of the first NMOS tube MN1 and the grid of the first NMOS tube MN1；
First NMOS tube MN1 has grid, drain electrode and source electrode, and grid is coupled to first resistor R1 second ends, drains
First resistor R1 second ends are coupled to, source electrode is coupled to the first positive-negative-positive bipolar transistor PNP1 emitters；
First positive-negative-positive bipolar transistor PNP1, has emitter, base stage and collector, and emitter is coupled to first
NMOS tube MN1 source electrodes, base stage are coupled to the 3rd bipolar npn transistor npn npn NPN3 base stages and the 4th bipolar npn type crystal
Pipe NPN4 base stages, collector are coupled to second source end GND and receive negative supply；
Second resistance R2, has a first end and a second end, and first end is coupled to the first power end VIN and receives positive supply,
Its second end is coupled to the first bipolar npn transistor npn npn NPN1 base stages and the first bipolar npn transistor npn npn NPN1 collectors；
First bipolar npn transistor npn npn NPN1, has collector, base stage and emitter, and collector is coupled to second
Resistance R2 second ends, base stage are coupled to second resistance R2 second ends, and emitter is coupled to the first zener diode D1 first
End and the second bipolar npn transistor npn npn NPN2 base stages；And
Second bipolar npn transistor npn npn NPN2, has base stage, collector and emitter, and base stage is coupled to the first NPN
Type bipolar transistor NPN1 emitters and the first zener diode D1 first ends, collector are coupled to the first power end VIN
Positive supply is received, emitter is coupled to the 3rd bipolar npn transistor npn npn NPN3 base stages and the 4th bipolar npn transistor npn npn
NPN4 base stages.
First resistor R1, the first NMOS tube MN1 for playing the role of resistance play partial pressure, and it is bipolar to reduce the first positive-negative-positive
Voltage between transistor npn npn PNP1 collectors and emitter.Second resistance R2 plays the role of partial pressure, reduces the first bipolar npn
Voltage between transistor npn npn NPN1 collectors and emitter.
Bootstrapping biasing circuit includes：
First PMOS tube MP1, has source electrode, grid and drain electrode, and source electrode is coupled to the first power end VIN and receives positive electricity
Source, grid are coupled to the second positive-negative-positive bipolar transistor PNP2 emitters, and drain electrode is coupled to the ambipolar crystalline substance of the second positive-negative-positive
Body pipe PNP2 emitters；
Second positive-negative-positive bipolar transistor PNP2, has emitter, base stage and collector, and emitter is coupled to first
PMOS tube MP1 grids and the first PMOS tube MP1 drain electrode, base stage be coupled to the 4th positive-negative-positive bipolar transistor PNP4 base stages and
5th positive-negative-positive bipolar transistor PNP5 emitters, collector are coupled to the 3rd positive-negative-positive bipolar transistor PNP3 transmittings
Pole；
3rd positive-negative-positive bipolar transistor PNP3, has emitter, base stage and collector, and emitter is coupled to second
Positive-negative-positive bipolar transistor PNP2 collectors, base stage are coupled to the 5th positive-negative-positive bipolar transistor PNP5 base stages and the 3rd
Bipolar npn transistor npn npn NPN3 collectors, collector are coupled to the 3rd bipolar npn transistor npn npn NPN3 collectors；
Second PMOS tube MP2, has source electrode, grid and drain electrode, and source electrode is coupled to the first PMOS tube MP1 source electrodes and the 6th
Bipolar npn transistor npn npn NPN6 collectors, grid are coupled to the 4th positive-negative-positive bipolar transistor PNP4 emitters, leakage
Pole is coupled to the 4th positive-negative-positive bipolar transistor PNP4 emitters；
4th positive-negative-positive bipolar transistor PNP4, has emitter, base stage and collector, and emitter is coupled to second
PMOS tube MP2 grids and the second PMOS tube MP2 drain electrode, base stage be coupled to the second positive-negative-positive bipolar transistor PNP2 base stages and
5th positive-negative-positive bipolar transistor PNP5 emitters, collector be coupled to the second positive-negative-positive bipolar transistor PNP2 base stages and
5th positive-negative-positive bipolar transistor PNP5 emitters；
5th positive-negative-positive bipolar transistor PNP5, has emitter, base stage and collector, and emitter is coupled to second
Positive-negative-positive bipolar transistor PNP2 base stages and the 4th positive-negative-positive bipolar transistor PNP4 base stages, base stage are coupled to the 3rd PNP
Type bipolar transistor PNP3 base stages and the 5th bipolar npn transistor npn npn NPN5 collectors, collector are coupled to the 4th NPN
Type bipolar transistor NPN4 collectors and the 6th bipolar npn transistor npn npn NPN6 base stages；And
5th bipolar npn transistor npn npn NPN5, has collector, base stage and emitter, and collector is coupled to the 3rd
Positive-negative-positive bipolar transistor PNP3 collectors, the 3rd positive-negative-positive bipolar transistor PNP3 base stages and the 5th ambipolar crystalline substance of positive-negative-positive
Body pipe PNP5 base stages, base stage are coupled to first resistor R1 second ends and the first NMOS tube MN1 drain electrodes, and emitter is coupled to the
Three bipolar npn transistor npn npn NPN3 collectors.
In biasing circuit module of booting, it can generate an electric current unrelated with supply voltage, so, supply voltage
It is unstable on it without influence, be the biasing of circuit with stable.Wherein the first PMOS tube MP1 and the second PMOS tube MP2 conducts
Resistance adjusts the voltage between bipolar transistor collector and emitter.Second bipolar npn transistor npn npn NPN2 and the 4th
Positive-negative-positive bipolar transistor PNP4 forms current-mirror structure.It to output branch, gives the current copy for inputting branch to core electricity
Road provides bootstrapping bias current.3rd bipolar npn transistor npn npn NPN3 and the 5th positive-negative-positive bipolar transistor PNP5 composition electricity
Flow mirror structure.It to output branch, the current copy for inputting branch is provided to bootstrapping bias current to core circuit.Current mirror knot
Structure electric current substantially constant makes the 5th bipolar npn transistor npn npn NPN5 obtain a stable collector current and base current.
The high-order Low Drift Temperature compensation circuit, wherein, the negative temperature coefficient compensation circuit includes：
First positive-negative-positive bipolar transistor PNP1, has emitter, base stage and collector, and emitter is coupled to first
NMOS tube MN1 source electrodes, base stage are coupled to the 3rd bipolar npn transistor npn npn NPN3 base stages and the 4th bipolar npn type crystal
Pipe NPN4 base stages, collector are coupled to second source end GND and receive negative supply；
First zener diode D1, has a first end and a second end, and first end is coupled to the first bipolar npn type crystal
Pipe NPN1 emitters and the second bipolar npn transistor npn npn NPN2 base stages, it is negative that second end is coupled to second source end GND receptions
Power supply；
3rd bipolar npn transistor npn npn NPN3, has collector, base stage and emitter, and collector is coupled to the 5th
Bipolar npn transistor npn npn NPN5 emitters, base stage are coupled to the second bipolar npn transistor npn npn NPN2 emitters and the 4th
Bipolar npn transistor npn npn NPN4 base stages, emitter is coupled to the second NMOS tube MN2 grids, the second NMOS tube MN2 drains,
4th resistance R4 second ends；
3rd resistor R3, has a first end and a second end, and first end is coupled to second source end GND and receives negative supply,
Its second end is coupled to the 4th resistance R4 first ends.
4th resistance R4, has a first end and a second end, and first end is coupled to 3rd resistor R3 second ends, second end
It is coupled to the 3rd bipolar npn transistor npn npn NPN3 emitters and the 5th resistance R5 second ends；
The 3rd resistor resistance value is equal with the 4th resistance；
5th resistance R5, has a first end and a second end, and first end is coupled to the 3rd bipolar npn transistor npn npn NPN3
Base stage and the 4th bipolar npn transistor npn npn NPN4 base stages, second end are coupled to the 4th resistance R4 second ends；
Second NMOS tube MN2, has grid, drain electrode and source electrode, and drain electrode is coupled to the 3rd bipolar npn transistor npn npn
NPN3 emitters, grid are coupled to the 3rd bipolar npn transistor npn npn NPN3 emitters, and source electrode is coupled to the second positive supply
Noise is held to receive positive supply；And
6th bipolar npn transistor npn npn NPN6, has collector, base stage and emitter, and collector is coupled to second
PMOS tube MP2 grids and the second PMOS tube MP2 source electrodes, base stage are coupled to the 5th positive-negative-positive bipolar transistor PNP5 collectors
With the 4th bipolar npn transistor npn npn NPN4 collectors, emitter is coupled to the second zener diode D2 first ends.
Second NMOS tube MN2 plays partial pressure, the 5th resistance R5 as a resistance 3rd resistor R3 and the 4th resistance R4
The 3rd bipolar npn transistor npn npn NPN3 base currents are limited, play shunting function.
Second zener diode D2 provides a constant voltage, stablizes output, so that temperature coefficient is extremely low.Described
Two zener diode D2 include adjusting temperature coefficient, are the 6th resistance, and the 7th resistance provides the electric current of zero-temperature coefficient.
The high-order Low Drift Temperature compensation circuit, wherein, the positive temperature coefficient compensation circuit includes：
4th bipolar npn transistor npn npn NPN4, has collector, base stage and emitter, and collector is coupled to the 5th
Positive-negative-positive bipolar transistor PNP5 collectors, base stage are coupled to the 3rd bipolar npn transistor npn npn NPN3 base stages, the 5th electricity
Resistance R5 first ends and the first positive-negative-positive bipolar transistor PNP1 base stages, emitter are coupled to the 7th bipolar npn transistor npn npn
NPN7 collectors；
7th bipolar npn transistor npn npn NPN7, has collector, base stage and emitter, and collector is coupled to the 4th
Bipolar npn transistor npn npn NPN4 emitters, base stage are coupled to the 6th resistance R6 second ends and the 7th resistance R7 first ends,
Emitter is coupled to second source end GND and receives negative supply；
Second zener diode D2, has a first end and a second end, and first end is coupled to the 6th bipolar npn type crystal
Pipe NPN6 emitters, second end are coupled to the 6th resistance R6 first ends；
6th resistance R6, has a first end and a second end, and first end is coupled to the second zener diode D2 second ends,
Second end is coupled to the 7th resistance R7 first ends；And
7th resistance R7, has a first end and a second end, and first end is coupled to the 6th resistance R6 second ends, second end
It is coupled to second source end GND and receives negative supply.
The positive temperature coefficient compensation circuit, wherein, the second zener diode D2 provides a constant voltage, for defeated
Go out stabilization, so that temperature coefficient is extremely low.
The 6th resistance adjustment negative temperature coefficient, the 7th resistance adjustment positive temperature coefficient.
Second zener diode includes adjusting temperature coefficient, is the 6th resistance, and the 7th resistance provides zero temperature
Spend the electric current of coefficient.Temperature coefficient is adjusted using the second zener diode, the temperature drift coefficient of voltage-stablizer is greatly reduced, carries
The high reliability of voltage-stablizer, traditional band-gap reference circuit do not adjust temperature drift coefficient using zener diode, and two level is steady
Pressure pipe is the 6th resistance R6, and the 7th resistance R7 provides the electric current of zero-temperature coefficient.
The 3rd resistor resistance value is equal with the 4th resistance.
For a metal-oxide-semiconductor, there are three cut-off region, saturation region and triode working regions, in facing for cut-off region
V is worked as in battery limit (BL)GS≈VTHWhen, there are a sub-threshold-conducting areas, when being operated in sub-threshold-conducting area, the drain-source current I of metal-oxide-semiconductorDS
With its gate source voltage VGSThere is following exponential relationship：
In above formula, n is the slope factor of sub-threshold region, it is the amount related with technique, temperature independent, is typically sized to
1.5；It is the mobility of carrier；COXFor the gate oxide capacitance of unit area；W/L is the breadth length ratio of metal-oxide-semiconductor；VDSIt is MOS
The drain-source voltage of pipe；VTHIt is the threshold value voltage of metal-oxide-semiconductor, VTIt is the amount related with temperature, is called thermal voltage, formula is expressed as VT=
KT/q, wherein k are Boltzmann constant, and size is k=1.3806505 × 10-23J/K；Q be electronics the quantity of electric charge, size q
=1.6 × 10-19C；T is temperature.
The mobility [mu] of carrier is the amount related with temperature, is represented by as follows:
In formula, μ (T0) is the mobility of the carrier when reference temperature is T0, and w is constant, and size is 1≤w≤2.
Under normal circumstances, due to VDS＞ ＞ VT, so can be by formulaIn last product term dispense,After being updated to abbreviation
In, it can obtain:
Peer-to-peer both sides are taken respectively from right logarithm, can obtain the gate source voltage V of metal-oxide-semiconductorGSIt is as follows with the relational expression of temperature T
As a result:
To above-mentioned formula, gate source voltage seeks partial derivative to the time, takes w=2, and reference temperature is substituted into result, can obtain
Following relational expression：
In above-mentioned formula, the threshold voltage of equation right end Section 1 has negative temperature coefficient, equation right end Section 2
Logarithmic term is also negative, so conclusion can be obtained, the V of metal-oxide-semiconductorGSThere is negative temperature coefficient in sub-threshold region.
As one timing of temperature, the threshold voltage V of metal-oxide-semiconductorTHFor a constant, then if being in two MOS of sub-threshold region
The drain-source current of pipe is equal, during breadth length ratio difference, utilizes formula
It can draw two metal-oxide-semiconductor gate source voltage difference Δ VGS's
Relational expression can represent as follows：ΔVGS=VGS1-VGS2=nVTLnM,
In formula, M=(W/L)2/(W/L)1, it is temperature independent item, so Δ VGSWith positive temperature coefficient.Institute
With the bandgap voltage reference formed with metal-oxide-semiconductor is exactly the V that make use of metal-oxide-semiconductor in sub-threshold regionGSNegative temperature coefficient and Δ
VGSThe superposition of positive temperature coefficient obtain temperature independent bandgap voltage reference.
It is proved in many analog circuits it is essential with the voltage or current reference of temperature relation very little.Value
It is noted that because most of technological parameters be with temperature change, if a benchmark is temperature independent,
So usually it is also unrelated with technique.We assume that if there is opposite temperature coefficient (temperature by two
Coefficient voltage) is added with suitable weight, eventually obtains the reference voltage of zero-temperature coefficient.For example, voltage V+
There is positive temperature coefficient, voltage V_ has negative temperature coefficient, and there are suitable weight αs and β to meet:
In a variety of device parameters of semiconductor technology, the characterisitic parameter of bipolar transistor is proved to be with best
Repeatability, and positive temperature coefficient and negative temperature coefficient, strict difinition amount can be provided.Although many ginsengs of MOS device
Number is contemplated by generating reference voltage, but bipolar circuit still forms the core of this kind of circuit.Bipolar transistor
Managing (BJT) has following two characteristics:1. the base stage of two bipolar transistors with different current densities-emitter electricity
The difference DELTA V of pressureBEWith positive temperature coefficient；2. the Δ V of ground level-emitter voltage of bipolar transistorBEWith negative temperature
Spend coefficient.Both voltages are added with certain weight, obtained voltage just approximate there can be zero-temperature coefficient.
For a bipolar transistor, collector current (IC) and base stage-emitter voltage (Δ VBE) relation
For：
IC=ISexp(VBE/VT)
For the bipolar transistor of emitter junction positively biased, Collector Current Density and Δ VBERelation be represented by:
Wherein,It is electronics average diffusion coefficient；WBFor base width；np0=ni 2/NAFor the electron concentration of base, ni
It is intrinsic carrier concentration, NAIt is acceptor impurity concentration, and
D is the constant unrelated with temperature, Vg0For band gap voltage.
Fig. 3 shows one embodiment temperature characteristics according to the present invention, for the triode of a positive job,
Tsividist derived V in 1980BEIt is with temperature and the relevant equation of technique：
Wherein Vg0The band gap voltage of silicon when being 0K, T are absolute temperature, and η is one temperature independent and related with technique
Parameter, its value are about between 3.6-4, and α is a temperature-independent parameter for flowing through triode bias current, works as biased electrical
Stream is that absolute temperature is proportional to (PTAT) electric current is α=1；When bias current is temperature independent, α=0.Above formula is into one
Step arranges：
Wherein, a0=Vg0,-a1Tshi is linear
,-a2TlnT is higher order term.
VBE(T) it is single order temperature-compensating that single order item, which balances out,.Due to VBE(T) higher order term-a is contained2TlnT is so only
By single order temperature-compensating, the very low band-gap reference of temperature coefficient is hardly resulted in, we need to carry out high-order temperature compensated therefore.
Temperature drift coefficient is to weigh the very important index that bandgap voltage reference output voltage varies with temperature.Temperature
It is smaller to float coefficient, output signal is influenced by temperature smaller, its calculation formula is：
As ((reference voltage maximum)-(reference voltage minimum value)/(reference voltage average value * temperature ranges)) * 10^6.
Due to base stage-emitter voltage V of bipolarity triodeBEIt is not linear for varying with temperature.Traditional single order temperature
Degree compensation, temperature coefficient are still higher, it is impossible to meet high-precision, the Low Drift Temperature coefficient requirements of present IC system, need therefore
Carry out the temperature-compensating of high-order.The present invention has the function of high-order temperature compensated, temperature characteristics such as Fig. 3.
In this disclosure used quantifier "one", " one kind " etc. be not excluded for plural number." first " in text, "
Two " etc. only represent to distinguish the like occurred in describing the embodiments of the present." first ", " second " going out in detail in the claims
It has been now only convenient for the fast understanding of claim rather than in order to be limited.Any attached drawing in claims
Mark should be construed as the limitation to scope.
The above is the preferred embodiment of the present invention, cannot limit the right model of the present invention with this certainly
It encloses, it is noted that for those skilled in the art, modify or wait to technical scheme
With replacing, without departure from the protection domain of technical solution of the present invention.
Claims (10)
1. a kind of no amplifier high-order Low Drift Temperature band-gap reference circuit, including：
Start-up circuit, for starting without amplifier high-order Low Drift Temperature band-gap reference circuit；Including：
First resistor has a first end and a second end, and first end is coupled to the first power end and receives positive supply, second end coupling
To the drain electrode of the first NMOS tube and the grid of the first NMOS tube；
First NMOS tube has grid, drain electrode and source electrode, and grid is coupled to first resistor second end, and drain electrode is coupled to the
One resistance second end, source electrode are coupled to the first positive-negative-positive emitter bipolar transistor；
First positive-negative-positive bipolar transistor, has emitter, base stage and collector, and collector is coupled to the first NMOS tube source
Pole, base stage are coupled to the 3rd bipolar npn transistor npn npn base stage and the 4th bipolar npn transistor npn npn base stage, emitter
It is coupled to second source end and receives negative supply；
Second resistance has a first end and a second end, and first end is coupled to the first power end and receives positive supply, second end coupling
It is connected to the first bipolar npn transistor npn npn base stage and the first bipolar npn transistor npn npn collector；
First bipolar npn transistor npn npn, has collector, base stage and emitter, and collector is coupled to second resistance second
End, base stage are coupled to second resistance second end, and emitter is coupled to the first zener diode first end and the second NPN type is double
Bipolar transistor base stage；And
Second bipolar npn transistor npn npn, has base stage, collector and emitter, and base stage is coupled to the first bipolar npn type
Emitter and the first zener diode first end, collector are coupled to the first power end and receive positive supply, transmitting
Pole is coupled to the 3rd bipolar npn transistor npn npn base stage and the 4th bipolar npn transistor npn npn base stage；
High-order Low Drift Temperature compensation circuit, for generating positive temperature coefficient electric current and negative temperature parameter current, positive temperature coefficient electric current
It mutually compensates for generating Low Drift Temperature coefficient with negative temperature parameter current, including:Positive temperature coefficient compensation circuit and negative temperature coefficient are mended
Repay circuit；And
Bootstrapping biasing circuit, for providing the bias current of Positive and Negative Coefficient Temperature compensation circuit.
2. no amplifier high-order Low Drift Temperature band-gap reference circuit according to claim 1, wherein, the high-order Low Drift Temperature is mended
Repaying circuit includes：
Positive temperature coefficient compensation circuit provides the voltage with ptc characteristics, is born using positive temperature coefficient voltage compensation
Temperaturecoefficient voltage；
Negative temperature coefficient compensation circuit provides the voltage with negative temperature coefficient feature, using negative temperature coefficient voltage compensation just
Temperaturecoefficient voltage.
3. no amplifier high-order Low Drift Temperature band-gap reference circuit according to claim 1, wherein, the bootstrapping biasing circuit bag
It includes：
First PMOS tube, has source electrode, grid and drain electrode, and source electrode is coupled to the first power end and receives positive supply, grid coupling
The second positive-negative-positive emitter bipolar transistor is connected to, drain electrode is coupled to the second positive-negative-positive emitter bipolar transistor；
Second positive-negative-positive bipolar transistor, has emitter, base stage and collector, and emitter is coupled to the first gate pmos
Pole and the drain electrode of the first PMOS tube, base stage are coupled to the 4th positive-negative-positive bipolar transistor base stage and the 5th positive-negative-positive bipolar transistor
Pipe emitter, collector are coupled to the 3rd positive-negative-positive emitter bipolar transistor；
3rd positive-negative-positive bipolar transistor has emitter, base stage and collector, and it is bipolar that emitter is coupled to the second positive-negative-positive
Transistor npn npn collector, base stage are coupled to the 5th positive-negative-positive bipolar transistor base stage and the 3rd bipolar npn transistor npn npn collection
Electrode, collector are coupled to the 3rd bipolar npn transistor npn npn collector；
Second PMOS tube, has source electrode, grid and drain electrode, and source electrode is coupled to the first PMOS tube source electrode and the 6th bipolar npn
Transistor npn npn collector, grid are coupled to the 4th positive-negative-positive emitter bipolar transistor, and drain electrode is coupled to the 4th positive-negative-positive
Emitter bipolar transistor；
4th positive-negative-positive bipolar transistor, has emitter, base stage and collector, and emitter is coupled to the second gate pmos
Pole and the drain electrode of the second PMOS tube, base stage are coupled to the second positive-negative-positive bipolar transistor base stage and the 5th positive-negative-positive bipolar transistor
Pipe emitter, collector are coupled to the second positive-negative-positive bipolar transistor base stage and the 5th positive-negative-positive bipolar transistor emitter
Pole；
5th positive-negative-positive bipolar transistor has emitter, base stage and collector, and it is bipolar that emitter is coupled to the second positive-negative-positive
Transistor npn npn base stage and the 4th positive-negative-positive bipolar transistor base stage, base stage are coupled to the 3rd positive-negative-positive bipolar transistor base stage
With the 5th bipolar npn transistor npn npn collector, collector is coupled to the 4th bipolar npn transistor npn npn collector and the 6th
Bipolar npn transistor npn npn base stage；And
5th bipolar npn transistor npn npn has collector, base stage and emitter, and it is bipolar that collector is coupled to the 3rd positive-negative-positive
Transistor npn npn collector, the 3rd positive-negative-positive bipolar transistor base stage and the 5th positive-negative-positive bipolar transistor base stage, base stage coupling
First resistor second end and the drain electrode of the first NMOS tube are connected to, emitter is coupled to the 3rd bipolar npn transistor npn npn collector.
4. high-order Low Drift Temperature compensation circuit according to claim 2, wherein, the negative temperature coefficient compensation circuit includes：
First positive-negative-positive bipolar transistor, has emitter, base stage and collector, and emitter is coupled to the first NMOS tube source
Pole, base stage are coupled to the 3rd bipolar npn transistor npn npn base stage and the 4th bipolar npn transistor npn npn base stage, collector
It is coupled to second source end and receives negative supply；
First zener diode, has a first end and a second end, and first end is coupled to the transmitting of the first bipolar npn transistor npn npn
Pole and the second bipolar npn transistor npn npn base stage, second end are coupled to second source end and receive negative supply；
3rd bipolar npn transistor npn npn, has collector, base stage and emitter, and collector is coupled to the 5th bipolar npn
Transistor npn npn emitter, base stage are coupled to the second bipolar npn transistor npn npn emitter and the 4th bipolar npn transistor npn npn
Base stage, emitter are coupled to the second NMOS tube grid, the drain electrode of the second NMOS tube, the 4th resistance second end；
3rd resistor has a first end and a second end, and first end is coupled to second source end and receives negative supply, second end coupling
It is connected to the 4th resistance first end；
4th resistance, has a first end and a second end, and first end is coupled to 3rd resistor second end, and second end is coupled to
Three bipolar npn transistor npn npn emitters and the 5th resistance second end；
5th resistance, has a first end and a second end, and first end is coupled to the 3rd bipolar npn transistor npn npn base stage and the 4th
Bipolar npn transistor npn npn base stage, second end are coupled to the 4th resistance second end；
Second NMOS tube has grid, drain electrode and source electrode, and drain electrode is coupled to the 3rd bipolar npn transistor npn npn emitter,
Grid is coupled to the 3rd bipolar npn transistor npn npn emitter, and source electrode is coupled to the second positive power source terminal and receives positive supply；And
6th bipolar npn transistor npn npn, has collector, base stage and emitter, and collector is coupled to the second gate pmos
Pole and the second PMOS tube source electrode, base stage is coupled to the 5th positive-negative-positive bipolar transistor pipe collector and the 4th bipolar npn type is brilliant
Body pipe collector, emitter are coupled to the second zener diode first end.
5. high-order Low Drift Temperature compensation circuit according to claim 2, wherein, the positive temperature coefficient compensation circuit includes：
4th bipolar npn transistor npn npn has collector, base stage and emitter, and it is bipolar that collector is coupled to the 5th positive-negative-positive
Transistor npn npn collector, base stage are coupled to the 3rd bipolar npn transistor npn npn base stage, the 5th resistance first end and the first PNP
Type bipolar transistor base stage, emitter are coupled to the 7th bipolar npn transistor npn npn collector；
7th bipolar npn transistor npn npn, has collector, base stage and emitter, and collector is coupled to the 4th bipolar npn
Transistor npn npn emitter, base stage are coupled to the 6th resistance second end and the 7th resistance first end, and emitter is coupled to second
Power end receives negative supply；
Second zener diode, has a first end and a second end, and first end is coupled to the 6th bipolar npn type zener diode
Emitter, second end are coupled to the 6th resistance first end；
6th resistance, has a first end and a second end, and first end is coupled to the second zener diode second end, second end coupling
It is connected to the 7th resistance first end；And
7th resistance, has a first end and a second end, and first end is coupled to the 6th resistance second end, and second end is coupled to
Two power ends receive negative supply.
6. positive temperature coefficient compensation circuit according to claim 5, wherein, the second zener diode provides a constant electricity
Pressure exports for stablizing.
7. the second zener diode according to claim 6, using Zener diode, for providing zero-temperature coefficient electricity
Stream.
8. high-order Low Drift Temperature compensation circuit according to claim 2, wherein, the 6th resistance adjustment negative temperature coefficient,
7th resistance adjustment positive temperature coefficient.
It is the 6th resistance 9. the second zener diode according to claim 7 includes adjusting temperature coefficient, the 7th is electric
Resistance provides the electric current of zero-temperature coefficient.
10. high-order Low Drift Temperature compensation circuit according to claim 4, which is characterized in that the 3rd resistor resistance value and institute
It is equal to state the 4th resistance.
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| CN115437442B (en) * | 2022-08-17 | 2024-03-19 | 成都华微电子科技股份有限公司 | High-order compensation band gap voltage reference circuit |
| CN115877908A (en) * | 2023-03-02 | 2023-03-31 | 盈力半导体(上海)有限公司 | Band gap voltage reference circuit and second-order nonlinear correction circuit and chip thereof |
| CN115877908B (en) * | 2023-03-02 | 2023-04-28 | 盈力半导体(上海)有限公司 | Band gap voltage reference circuit, second-order nonlinear correction circuit and chip thereof |
| CN117519403A (en) * | 2024-01-05 | 2024-02-06 | 深圳市山海半导体科技有限公司 | Band gap reference circuit and electronic equipment |
| CN117519403B (en) * | 2024-01-05 | 2024-04-09 | 深圳市山海半导体科技有限公司 | Band gap reference circuit and electronic equipment |
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| CN108052154B (en) | 2023-08-01 |
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