CN116166078A - Low-temperature drift high-precision reference voltage source for CAN bus transceiver - Google Patents

Low-temperature drift high-precision reference voltage source for CAN bus transceiver Download PDF

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CN116166078A
CN116166078A CN202310158794.3A CN202310158794A CN116166078A CN 116166078 A CN116166078 A CN 116166078A CN 202310158794 A CN202310158794 A CN 202310158794A CN 116166078 A CN116166078 A CN 116166078A
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resistor
generating circuit
circuit
pmos tube
pmos
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王雪文
王艺蒙
郭轩阳
涂慧浩
彭超
赵武
马晓龙
邓周虎
齐晓斐
翟春雪
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NORTHWEST UNIVERSITY
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    • G05—CONTROLLING; REGULATING
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    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract

The invention discloses a low-temperature drift high-precision reference voltage source for a CAN bus transceiver, which comprises a band gap reference generating circuit and a VDD/2 reference generating circuit, wherein the band gap reference generating circuit is used for generating 1.2V output voltage, and the VDD/2 reference generating circuit is used for outputting reference voltage; the band gap reference generating circuit includes: the core reference generating circuit is used for generating stable direct-current voltage, the starting circuit is used for ensuring that the core reference generating circuit is electrified under the condition of zero current, the starting circuit is not operated under the condition of normal operation of the core reference generating circuit, the high-order curvature compensation circuit is used for carrying out high-order compensation on the temperature drift of the stable direct-current voltage output by the core reference generating circuit, and the resistor trimming circuit is used for trimming the reference voltage of the direct-current voltage output by the core reference generating circuit. The invention can generate all references needed in the transceiver, so that the reference voltage has the characteristics of low temperature drift coefficient and high PSRR, and consumes lower static power consumption.

Description

Low-temperature drift high-precision reference voltage source for CAN bus transceiver
Technical Field
The invention belongs to the technical field of integrated circuits, and relates to a design of a reference module suitable for a CAN bus transceiver.
Background
There are a variety of communication modes in various electronic systems at present, and among them, CAN communication is one of the most widely used communication modes. As one of the important components in CAN communication, a CAN bus transceiver is indispensable, and is located between a CAN controller and a physical bus for data transfer. The reference module is an essential module in the transceiver for providing stable voltage or current which does not change with temperature, and the accuracy and stability of the reference module directly affect the accuracy of the whole system.
In order to simplify the design of the traditional CAN bus transceiver and the reference voltage of VDD/2 required by an output module of a transmitter, a band gap reference circuit is designed by directly adopting a current-mode basic structure, so that the output reference voltage is VDD/2. However, the bandgap reference module generally obtained by the architecture generally consumes larger static power consumption, has larger disturbance to an output point and has higher temperature drift coefficient.
Disclosure of Invention
The invention aims to provide a reference module circuit suitable for a CAN bus transceiver. If a unified reference circuit is adopted in the circuit, larger static power consumption is generated, and larger disturbance is generated on an output point. To solve this problem, reference blocks of the circuit are designed separately in response to demands for different precision and temperature drift coefficients of reference voltage and current in the circuit. The invention generates all references needed inside the transceiver through the band gap reference circuit module and the VDD/2 reference circuit module of the voltage module structure, so that the obtained reference voltage has the characteristics of low temperature drift coefficient and high PSRR, and consumes lower static power consumption.
In order to achieve the above purpose, the invention adopts the following technical scheme:
the low-temperature drift high-precision reference voltage source for the CAN bus transceiver comprises a band-gap reference generating circuit and a VDD/2 reference generating circuit, wherein the band-gap reference generating circuit is used for generating 1.2V output voltage, and the VDD/2 reference generating circuit is used for outputting reference voltage;
the band gap reference generating circuit includes the following parts:
the core reference generating circuit is used for generating stable direct-current voltage;
the starting circuit is used for ensuring that the core reference generating circuit is electrified under the condition of zero current and ensuring that the starting circuit does not work under the condition that the core reference generating circuit normally works and has current;
the high-order curvature compensation circuit is used for carrying out high-order compensation on the temperature drift of the stable direct-current voltage output by the core reference generation circuit;
and the resistor trimming circuit is used for trimming the reference voltage of the direct-current voltage output by the core reference generating circuit.
Further, the core reference source generating circuit comprises an operational amplifier A1, a pnp transistor Q2, a pnp transistor Q3, a PMOS transistor M1, a PMOS transistor M2, a PMOS transistor M3, a resistor R1, a resistor R2, a resistor R3 and a resistor R4; the grid electrodes of the PMOS tubes M1, M2 and M3 are connected with the output end of the operational amplifier A1, the drain electrode of the PMOS tube M1 is connected with one end of a resistor R3, the other end of the resistor R3 is connected with the positive input end of the operational amplifier A1 and the resistor R1, the other end of the resistor R1 is connected with the emitter electrode of a pnp transistor Q2, and the base electrode and the collector electrode of the Q2 are grounded; the drain electrode of the PMOS tube M2 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with the inverting input end of the operational amplifier A1 and the emitter electrode of the pnp transistor Q1, and the base electrode and the collector electrode of the Q1 are grounded; the PMOS tube M3 replicates the current flowing through the PMOS tube M2, and the drain electrode of the PMOS tube M3 is connected with one end of the resistor R2 and generates a direct-current voltage Vout1; the other end of the resistor R2 is connected with the emitter of the pnp transistor Q3, and the base and the collector of the pnp transistor Q3 are grounded.
Further, the resistor R1 and the resistor R2 have the same resistor type, and the ratio of the width to the length of the PMOS tube M1, the PMOS tube M2 and the PMOS tube M3 is 1:1:1, the ratio of the areas of pnp transistor Q1, pnp transistor Q2, pnp transistor Q3 is 1:8:1.
further, the starting circuit comprises a capacitor C1, an NMOS tube M4, an NMOS tube M5 and a PMOS tube M6, wherein the grid electrode of the NMOS tube M4 is connected with the direct current voltage Vout1 output by the core reference source generating circuit; the drain end of the NMOS tube M4 is connected with an NMOS tube M5 connected with a diode as a load and connected with the grid electrode of an NMOS tube M6, the drain electrode of the NMOS tube M6 is connected with the grid electrodes of a PMOS tube M1, a PMOS tube M2 and a PMOS tube M3 of the core reference source generating circuit and is connected with a power supply voltage VDD through a capacitor C1; the sources of the NMOS tube M4 and the PMOS tube M6 are grounded, and the sources of the PMOS tube M1, the PMOS tube M2, the PMOS tube M3 and the NMOS tube M5 are connected to the power supply voltage VDD.
Further, the high-order curvature compensation circuit comprises an operational amplifier A2, a PMOS tube M7, a PMOS tube M8, a pnp transistor Q4, a resistor R5 and a resistor R6; the direct-current voltage Vout1 output by the core reference source generating circuit is the input voltage of the inverting terminal of the operational amplifier A2, the positive input terminal of the operational amplifier A2 is connected to the drain electrode of the PMOS tube M7, and the output terminal of the operational amplifier A2 is connected to the grid electrodes of the PMOS tube M7 and the PMOS tube M8; the drain electrode of the PMOS tube M7 is connected to the ground through a resistor R5, the drain electrode of the PMOS tube M8 is connected with the emitter electrode of a pnp transistor Q4 with the base electrode and the collector electrode grounded, and meanwhile, one end of a resistor R6 is connected, and the other end of the resistor R6 is connected with the drain electrode of a PMOS tube M3 in the output branch circuit of the core reference source generating circuit.
Further, the resistor trimming circuit comprises a resistor R, a resistor 2R, a resistor 4R, a resistor 8R, a resistor 16R, and a switch T1, a switch T2, a switch T3, a switch T4 and a switch T5 which sequentially correspond to each other, wherein each resistor is connected with the corresponding switch in parallel to obtain a module circuit, all the module circuits are sequentially connected in series, one end of the resistor R, which is not connected with the resistor 2R, is Vi, one end of the resistor is Vi, which is connected with the drain electrode of a PMOS tube M3 of the core reference generating circuit, one end of the resistor 16R, which is not connected with the resistor 8R, is Vo, and one end of the resistor R2, which is not connected with the pnp transistor Q3, of the core reference generating module is connected with Vo.
Further, the switches T1-T5 are PIN PINs controlled by the MOS tube switch, when the PIN PINs are 1, the switches are closed, and the corresponding resistors are short-circuited; when the PIN is 0, the switch is opened, and the corresponding resistor is connected to the circuit.
Further, the VDD/2 reference generating circuit includes a two-stage unit operational amplifier A3, a resistor R7, and a resistor R8, where an inverting terminal of the operational amplifier A3 is connected to an output terminal of the operational amplifier A3, and is used as an output terminal Vout2 of the VDD/2 reference generating circuit, a non-inverting terminal of the operational amplifier A3 is connected to 2 identical resistors R7 and R8, another end of the resistor R7 is connected to a power supply voltage VDD, and another end of the resistor R8 is connected to ground.
The invention forms the reference module circuit in the CAN bus transceiver through two different types of reference source circuits, not only obtains the band-gap reference source with low power consumption and low temperature drift coefficient, but also meets the reference voltage required in the CAN bus, and the band-gap reference source with higher precision is beneficial to better work of the transceiver on the basis of completing the function. Under the SMIC 0.18um BCD process, the temperature drift coefficient of the band gap reference circuit module is only 5.12 ppm/DEG C, and the average temperature drift coefficient under different process angles is 6.78 ppm/DEG C.
Drawings
FIG. 1 is a schematic diagram of a bandgap core circuit with a start-up circuit of the present invention;
FIG. 2 is a schematic diagram of a high-order curvature compensation circuit according to the present invention;
FIG. 3 is a schematic diagram of a resistor trimming circuit according to the present invention;
FIG. 4 is a schematic diagram of the structure of the VDD/2 reference generation circuit according to the present invention.
Detailed Description
The invention will be described in detail below with reference to the drawings and the detailed description.
The low-temperature drift high-precision reference voltage source for the CAN bus transceiver comprises a band gap reference generating circuit and a VDD/2 reference generating circuit, wherein the band gap reference generating circuit is used for generating 1.2V output voltage, and the VDD/2 reference generating circuit is used for outputting reference voltage.
The band gap reference generating circuit comprises a core reference generating circuit, a starting circuit, a high-order curvature compensating circuit and a resistance trimming circuit. The starting circuit, the high-order curvature compensation circuit and the resistance trimming circuit are respectively connected with the core reference generating circuit.
The core reference generating circuit is used for generating stable direct-current voltage;
the starting circuit is used for ensuring that the core reference generating circuit is electrified under the condition of zero current and ensuring that the starting circuit does not work under the condition that the core reference generating circuit normally works and has current;
the high-order curvature compensation circuit is used for carrying out high-order compensation on the temperature drift of the stable direct-current voltage output by the core reference generation circuit to generate a reference voltage with a lower temperature drift coefficient;
and the resistor trimming circuit is used for trimming the reference voltage of the direct-current voltage output by the core reference generating circuit. The reference voltage is convenient to repair and regulate after chip production, and errors caused by process factors are reduced.
As shown in fig. 1, the core reference source generating circuit includes an operational amplifier A1, a pnp transistor Q2, a pnp transistor Q3, a PMOS transistor M1, a PMOS transistor M2, a PMOS transistor M3, a resistor R1, a resistor R2, a resistor R3, and a resistor R4. The grid electrodes of the PMOS tubes M1, M2 and M3 are connected with the output end of the operational amplifier A1, the drain electrode of the PMOS tube M1 is connected with one end of a resistor R3, the other end of the resistor R3 is connected with the positive input end of the operational amplifier A1 and the resistor R1, the other end of the resistor R1 is connected with the emitter electrode of a pnp transistor Q2, and the base electrode and the collector electrode of the Q2 are grounded; the drain electrode of the PMOS tube M2 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with the inverting input end of the operational amplifier A1 and the emitter electrode of the pnp transistor Q1, and the base electrode and the collector electrode of the Q1 are grounded; the PMOS tube M3 replicates the current flowing through the PMOS tube M2, and the drain electrode of the PMOS tube M3 is connected with one end of the resistor R2 and generates a direct-current voltage Vout1; the other end of the resistor R2 is connected with the emitter of the pnp transistor Q3, and the base and the collector of the pnp transistor Q3 are grounded.
Preferably, the resistance types of the resistor R1 and the resistor R2 are completely the same, a POLY layer resistor is selected, and the ratio of the resistance values of R1 and R2 is 1:7.3 The R3, R4 and R2 resistances are identical in type and magnitude. The ratio of the width to the length of the PMOS tube M1, the PMOS tube M2 and the PMOS tube M3 is 4/2, 4/2 and 80/2 respectively, and the ratio of the numbers of the pnp transistors Q1, the pnp transistors Q2 and the pnp transistors Q3 is 1:8:1.
the starting circuit is connected between the output direct-current voltage Vout1 of the core reference generating circuit and the grid electrodes connected with the PMOS tubes M1-M3, and whether the starting circuit works is determined by judging the magnitude of the direct-current voltage Vout1 output by the core reference generating circuit, so that the zero-current state in the core reference generating circuit is eliminated. Specifically, the starting circuit comprises a capacitor C1, an NMOS tube M4, an NMOS tube M5 and a PMOS tube M6, wherein the grid electrode of the NMOS tube M4 is connected with a direct current voltage Vout1 output by the core reference source generating circuit, and whether the tube M4 is started or not depends on the size of the Vout1; the drain end of the M4 is connected with an NMOS tube M5 connected with a diode as a load, and is connected with the grid electrode of an NMOS tube M6, the drain electrode of the M6 tube is connected with the grid electrodes of a PMOS tube M1, a PMOS tube M2 and a PMOS tube M3 of the core reference source generating circuit, and is connected with a power supply voltage VDD through a capacitor C1; the sources of the NMOS tube M4 and the PMOS tube M6 are connected to the ground, and the sources of the PMOS tube M1, the PMOS tube M2, the PMOS tube M3 and the NMOS tube M5 are connected to the power supply voltage VDD.
Preferably, the width-to-length ratios of the NMOS tube M4, the NMOS tube M5 and the PMOS tube M6 are respectively 4, 16, 2/0.5, and C1 is 0.5pF.
In the starting circuit, the capacitor C1 is used for preventing the device from being damaged by power supply fluctuation during power-up. When no current flows through the PMOS current mirror formed by the PMOS tubes M1-M3, vout1 is low potential, the M1 tube is cut off, and the M2 potential is biased to VDD-V by the M6 tube thp And the gate of the NMOS tube M5 is pulled down to be conducted so that the circuit gets rid of the degeneracy of zero current. At this time, vout1 increases in voltage, which turns on the M1 pipe, and cuts off the connection between the start-up circuit and the core module.
As shown in fig. 2, the high-order curvature compensation circuit includes an operational amplifier A2, a PMOS transistor M7, a PMOS transistor M8, a pnp transistor Q4, a resistor R5, and a resistor R6. The direct-current voltage Vout1 output by the core reference source generating circuit is the input voltage of the inverting terminal of the operational amplifier A2, the positive input terminal of the operational amplifier A2 is connected to the drain electrode of the PMOS tube M7, and the output terminal of the operational amplifier A2 is connected to the grid electrodes of the PMOS tube M7 and the PMOS tube M8 and used for controlling the passing current of the M7 and the M8; the drain electrode of the PMOS tube M7 is connected to the ground through a resistor R5, the drain electrode of the PMOS tube M8 is connected with the emitter electrode of a pnp transistor Q4 with the base electrode and the collector electrode grounded, and meanwhile, one end of a resistor R6 is connected, and the other end of the resistor R6 is connected with the drain electrode of a PMOS tube M3 in the output branch circuit of the core reference source generating circuit.
The higher order curvature compensation circuit compensates the curvature of the semiconductor substrate by passing two base-emitter voltages V through different temperature coefficient currents BE And making a difference, and enabling a compensation current generated by the voltage difference through a resistor to flow through a resistor R2 to realize temperature drift compensation of the output direct-current voltage Vout 1. The high-order curvature compensation circuit is used for counteracting the high-order part in the temperature drift function, which is already counteracted in the core reference source generating circuit. By utilizing the clamping function of the input stage of the operational amplifier A2, the voltage at the point A is identical to Vout1, a temperature-independent current is generated through a resistor R4, and the current is copied to the branch where Q4 is located through a PMOS current mirror.
V BE At a reference temperature T r The relationship with the optional temperature T can be expressed as:
Figure SMS_1
wherein I is S Can be expressed as:
Figure SMS_2
wherein A is the base-emitter area, n i Is the intrinsic carrier concentration, D is the minority carrier diffusion constant, N B Is the impurity concentration per unit area.
n i The relationship with the bandgap voltage is:
Figure SMS_3
wherein V is G And (T) is the value of the band gap voltage when the temperature is T.
To move toThe displacement is expressed as
Figure SMS_4
It can also be expressed as μ=ct -(4-η) Where C is a temperature independent parameter, η is a constant determined by the bipolar transistor and has a value of about 4.
Handle I C Expressed as: i C (T) =ft delta, wherein F is I C Temperature independent items in (a). Obtaining:
Figure SMS_5
the current flowing through transistor Q4 in the higher order curvature compensation circuit is artificially adjusted to a temperature independent amount, thus the base-emitter voltage V of Q4 BE4 δ=0 in (T). The current flowing through the triode Q3 in the output branch of the band gap core circuit is PTAT current which is duplicated by a PMOS current mirror and is positively related to absolute temperature, thus the base-emitter voltage V of the Q3 BE3 δ=1 in (T). All other items are the same, so V BE3 (T) and V BE4 The expression of (T) is:
Figure SMS_6
/>
Figure SMS_7
when Q3 is connected with Q4, the voltage at two ends of the resistor R6 is in nonlinear correlation with temperature, and the expression is as follows:
Figure SMS_8
the current generated by the voltage at the two ends of R6 is still related to the temperature in a nonlinear way, and is led into the output stage branch of the band gap reference, so that the voltage drop of the two ends of the resistor of the output stage branch can be influenced, and a proper resistance value is selected to ensure that
Figure SMS_9
Can counteract V BE Thereby reducing the temperature drift coefficient of the bandgap reference circuit module.
Preferably, pnp transistors Q4 and Q3 are identical, and the ratio of the sizes of PMOS transistors M7 and M8 is 1:1, the resistors R5 and R6 are also POLY layer resistors, the resistance of R5 is 120KΩ, and the resistance of R6 is 1/3 of the resistance of R2.
Because of the various unavoidable factors in CMOS fabrication, the resistor may be mismatched, such as temperature, process errors, doping non-uniformity, and the like. In consideration of the above factors, the invention adds a resistor trimming circuit which can be changed after the chip is produced, and adjusts the ratio of positive and negative temperature coefficient voltages by changing the resistance ratio of the resistor, thereby trimming the reference voltage of the output branch. Firstly, a band gap reference circuit module before a Trim circuit is not added is measured, and the precision offset caused by errors is determined, so that the resistance value and the precision required by the resistance trimming circuit are determined. After the determination, the resistor string is controlled by a switch formed by MOS tubes in a binary coding mode, the total resistance of the Trim circuit is controlled, and the size of the resistor proportion is changed after the resistor string is connected into a core reference source generating circuit.
The resistor trimming circuit is connected in series with the resistor R2 of the core reference generating circuit, and the resistor R is equivalent to the resistor trimming circuit trim The variable resistor can be changed after the chip is produced, so that the output direct-current voltage Vout1 can be changed and modified conveniently by changing the resistance proportion. In this embodiment, the resistor trimming circuit is shown in fig. 3, and includes a resistor R, a resistor 2R, a resistor 4R, a resistor 8R, a resistor 16R, and sequentially corresponding switches T1, T2, T3, T4, and T5, where each resistor is connected in parallel with the corresponding switch to obtain a module circuit, for example, R is connected in parallel with T1, 16R is connected in parallel with T5, all the module circuits are sequentially connected in series, one end of the resistor R, which is not connected with the resistor 2R, is Vi, which is connected with the drain of the PMOS transistor M3 of the core reference generating circuit, one end of the resistor 16R, which is not connected with the resistor 8R, is Vo, which is connected with one end of the resistor R2, which is not connected with the pnp transistor Q3, of the core reference generating module, and outputting direct currentThe voltage Vout1 takes the voltage at Vi. Wherein, T1-T5 are PIN feet controlled by the MOS tube switch, when the PIN feet are 1, the switch is closed, and the corresponding resistor is short-circuited; when the PIN is 0, the switch is opened, and the corresponding resistor is connected to the circuit. The total resistance of the Trim circuit (resistance trimming circuit) is changed by changing the value of the PIN PIN, so that the resistance of the core reference generating circuit is changed, and the voltage precision of the reference voltage output by the band gap reference circuit is improved.
In this embodiment, as shown in fig. 4, the VDD/2 reference generating circuit includes a two-stage unit operational amplifier A3, a resistor R7, and a resistor R8, wherein the inverting terminal of the operational amplifier A3 is connected to the output terminal of the operational amplifier A3, and is used as the output terminal Vout2 of the VDD/2 reference generating circuit, the non-inverting terminal is connected to 2 identical resistors R7 and R8, the other end of the resistor R7 is connected to the power supply voltage VDD, and the other end of the resistor R8 is grounded.
The VDD/2 reference generating circuit uses two identical resistors R7 and R8 to divide voltage, and outputs the divided voltage after passing through the unity gain two-stage amplifier. For the selection of the resistors R7 and R8, the consideration of the temperature coefficient of resistance and the chip area should be combined, and the POLY layer resistor with the maximum block resistance and the minimum temperature drift coefficient should be selected. In the design of the layout, the matching of the two resistors needs to be designed carefully, so that the process error is reduced to the minimum. Since the two resistors are identical, a substantially constant reference voltage VDD/2 can be obtained from the output-to-input follow-up characteristics of the unity gain amplifier.
In summary, in the specific implementation environment facing the CAN bus transceiver, the reference voltage source of the invention divides the reference module into two parts on the basis of meeting the system requirements, and the reference source with lower power consumption and lower temperature drift coefficient is skillfully designed under the condition facing different precision requirements. According to the actual measured change analysis of the output voltage curve, under the action of a higher-order curvature compensation circuit and a resistance trimming network, trimming the output voltage so that the temperature drift coefficient of the output voltage is smaller than 7 ppm/DEG C under each process angle.
The embodiments described above are described in order to facilitate the understanding and application of the present invention to those skilled in the art, and it will be apparent to those skilled in the art that various modifications may be made to the embodiments described above and that the general principles described herein may be applied to other embodiments without the need for inventive faculty. Therefore, the present invention is not limited to the above-described embodiments, and those skilled in the art, based on the present disclosure, should make improvements and modifications within the scope of the present invention.

Claims (8)

1. The low-temperature drift high-precision reference voltage source for the CAN bus transceiver is characterized by comprising a band-gap reference generating circuit and a VDD/2 reference generating circuit, wherein the band-gap reference generating circuit is used for generating 1.2V output voltage, and the VDD/2 reference generating circuit is used for outputting reference voltage;
the band gap reference generating circuit includes the following parts:
the core reference generating circuit is used for generating stable direct-current voltage;
the starting circuit is used for ensuring that the core reference generating circuit is electrified under the condition of zero current and ensuring that the starting circuit does not work under the condition that the core reference generating circuit normally works and has current;
the high-order curvature compensation circuit is used for carrying out high-order compensation on the temperature drift of the stable direct-current voltage output by the core reference generation circuit;
and the resistor trimming circuit is used for trimming the reference voltage of the direct-current voltage output by the core reference generating circuit.
2. The low temperature drift high precision reference voltage source for CAN bus transceiver of claim 1, wherein the core reference source generating circuit comprises an operational amplifier A1, a pnp transistor Q2, a pnp transistor Q3, a PMOS transistor M1, a PMOS transistor M2, a PMOS transistor M3, a resistor R1, a resistor R2, a resistor R3, and a resistor R4; the grid electrodes of the PMOS tubes M1, M2 and M3 are connected with the output end of the operational amplifier A1, the drain electrode of the PMOS tube M1 is connected with one end of a resistor R3, the other end of the resistor R3 is connected with the positive input end of the operational amplifier A1 and the resistor R1, the other end of the resistor R1 is connected with the emitter electrode of a pnp transistor Q2, and the base electrode and the collector electrode of the Q2 are grounded; the drain electrode of the PMOS tube M2 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with the inverting input end of the operational amplifier A1 and the emitter electrode of the pnp transistor Q1, and the base electrode and the collector electrode of the Q1 are grounded; the PMOS tube M3 replicates the current flowing through the PMOS tube M2, and the drain electrode of the PMOS tube M3 is connected with one end of the resistor R2 and generates a direct-current voltage Vout1; the other end of the resistor R2 is connected with the emitter of the pnp transistor Q3, and the base and the collector of the pnp transistor Q3 are grounded.
3. The low temperature drift high precision reference voltage source for CAN bus transceiver of claim 2, wherein the resistor R1 is the same type as the resistor R2, and the ratio of the width to the length of the PMOS transistor M1, the PMOS transistor M2, and the PMOS transistor M3 is 1:1:1, the ratio of the areas of pnp transistor Q1, pnp transistor Q2, pnp transistor Q3 is 1:8:1.
4. the low temperature drift high precision reference voltage source for CAN bus transceiver of claim 1, wherein the start-up circuit comprises a capacitor C1, an NMOS transistor M4, an NMOS transistor M5 and a PMOS transistor M6, wherein the gate of the NMOS transistor M4 is connected with the dc voltage Vout1 output from the core reference source generating circuit; the drain end of the NMOS tube M4 is connected with an NMOS tube M5 connected with a diode as a load and connected with the grid electrode of an NMOS tube M6, the drain electrode of the NMOS tube M6 is connected with the grid electrodes of a PMOS tube M1, a PMOS tube M2 and a PMOS tube M3 of the core reference source generating circuit and is connected with a power supply voltage VDD through a capacitor C1; the sources of the NMOS tube M4 and the PMOS tube M6 are grounded, and the sources of the PMOS tube M1, the PMOS tube M2, the PMOS tube M3 and the NMOS tube M5 are connected to the power supply voltage VDD.
5. The low temperature drift high precision reference voltage source for CAN bus transceiver of claim 1, wherein the high order curvature compensation circuit comprises an operational amplifier A2, a PMOS transistor M7, a PMOS transistor M8, a pnp transistor Q4, a resistor R5, and a resistor R6; the direct-current voltage Vout1 output by the core reference source generating circuit is the input voltage of the inverting terminal of the operational amplifier A2, the positive input terminal of the operational amplifier A2 is connected to the drain electrode of the PMOS tube M7, and the output terminal of the operational amplifier A2 is connected to the grid electrodes of the PMOS tube M7 and the PMOS tube M8; the drain electrode of the PMOS tube M7 is connected to the ground through a resistor R5, the drain electrode of the PMOS tube M8 is connected with the emitter electrode of a pnp transistor Q4 with the base electrode and the collector electrode grounded, and meanwhile, one end of a resistor R6 is connected, and the other end of the resistor R6 is connected with the drain electrode of a PMOS tube M3 in the output branch circuit of the core reference source generating circuit.
6. The low temperature drift high precision reference voltage source for CAN bus transceiver of claim 1, wherein the resistor trimming circuit comprises a resistor R, a resistor 2R, a resistor 4R, a resistor 8R, a resistor 16R, and their corresponding switches T1, T2, T3, T4 and T5 in sequence, each resistor is connected in parallel with the corresponding switch to obtain a module circuit, all the module circuits are connected in series in sequence, one end of the resistor R, which is not connected with the resistor 2R, is Vi, which is connected with the drain of PMOS tube M3 of the core reference generating circuit, one end of the resistor 16R, which is not connected with the resistor 8R, is Vo, and Vo is connected with one end of the core reference generating module, which is not connected with pnp transistor Q3.
7. The low temperature drift high precision reference voltage source for CAN bus transceiver of claim 6, wherein switches T1-T5 are PIN controlled by MOS transistor switches, and when PIN is "1", the switch is turned off and the corresponding resistor is shorted; when the PIN is 0, the switch is opened, and the corresponding resistor is connected to the circuit.
8. The low temperature drift high precision reference voltage source for CAN bus transceiver of claim 1, wherein the VDD/2 reference generating circuit comprises a two-stage unit operational amplifier A3 and a resistor R7, a resistor R8, an inverting terminal of the operational amplifier A3 is connected to an output terminal of the operational amplifier A3, as an output terminal Vout2 of the VDD/2 reference generating circuit, a non-inverting terminal is connected to 2 identical resistors R7 and R8, another end of the resistor R7 is connected to a power supply voltage VDD, and another end of the resistor R8 is connected to ground.
CN202310158794.3A 2023-02-23 2023-02-23 Low-temperature drift high-precision reference voltage source for CAN bus transceiver Pending CN116166078A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117970992A (en) * 2024-04-01 2024-05-03 青岛元通电子有限公司 High-precision power reference voltage source control circuit and control method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117970992A (en) * 2024-04-01 2024-05-03 青岛元通电子有限公司 High-precision power reference voltage source control circuit and control method

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