CN116795164B - Band gap reference circuit based on broken line compensation - Google Patents

Band gap reference circuit based on broken line compensation Download PDF

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Publication number
CN116795164B
CN116795164B CN202310174706.9A CN202310174706A CN116795164B CN 116795164 B CN116795164 B CN 116795164B CN 202310174706 A CN202310174706 A CN 202310174706A CN 116795164 B CN116795164 B CN 116795164B
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mos tube
electrode
mos
transistor
gate
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CN116795164A (en
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庄浩宇
刘明宇
黄良辰
李强
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters

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  • Physics & Mathematics (AREA)
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Abstract

The invention discloses a bandgap reference circuit based on broken line compensation, which comprises an I generating PTAT current proportional to temperature PTAT A generator for generating a CTAT current I inversely proportional to temperature by using the PTAT current CTAT A generator for generating I of BASE current for compensation by PTAT current BASE A generator for generating I of FOLD current for FOLD line compensation by PTAT current and CTAT current FOLD A generator for generating a reference voltage VBG using PTAT current, CTAT current and BASE BASE current and performing foldback using FOLD current BG A generator. The band gap voltage reference circuit of the invention is provided with I FOLD The generator generates a folding current I with a current value not equal to 0 only when the temperature is smaller than the set temperature FOLD The compensation is carried out on the part of the original output voltage with the temperature smaller than the set temperature, so that a more ideal temperature coefficient is obtained. The design solves the problem of larger temperature coefficient of output voltage when the temperature is smaller in the prior art, and obtains the band-gap reference voltage which is more stable along with the temperature change.

Description

Band gap reference circuit based on broken line compensation
Technical Field
The invention belongs to an analog integrated circuit, and particularly relates to a band gap reference circuit based on broken line compensation.
Background
The bandgap reference (Bandgap Reference, BGR) functions to generate a reference voltage. Because its reference voltage is not much different from the bandgap voltage of silicon, it is called bandgap reference. The bandgap reference technology is mainly used for generating a voltage reference in a chip, can provide a stable working point for a system, and has an irreplaceable position in an electronic system.
The working principle of the band gap reference is as follows: the voltage of positive temperature coefficient and the voltage of negative temperature coefficient are generated first, and then the two voltages are added, so that the voltage of zero temperature coefficient is realized. In bulk CMOS technology, BJT (Bipolar Junction Transistor) is often used for designing BGR circuits, as long as the current density of two BJT transistors is guaranteed to be fixed and proportional, wherein the base-emitter voltage of any one BJT has a negative temperature coefficient, the difference between the base-emitter voltage drops of two BJT transistors has a positive temperature coefficient, and the voltages of the two BJT transistors are added to realize the zero temperature coefficient voltage.
In designing a high-precision BGR circuit, the base-emitter voltage characteristics of the BJT transistor itself affect the accuracy of the BGR circuit, and it is desirable to minimize the effect of higher-order nonlinear terms. A method of compensating the current is generally adopted, and a nonlinear term is approximated as much as possible, so that a linear base-emitter voltage difference is obtained.
The difference between the base-emitter voltages of the BJT is:
it can be seen that the formula contains a linear term and a higher order nonlinear termWhen a low temperature drift coefficient is required, higher order terms cannot be ignored.
The prior art solution to this is shown in fig. 1, 2, in which in fig. 2 the voltages at nodes C and D are guaranteed to be approximately equal by clamping of the MOS current mirror, thereby making R 8 The voltage on is equal to Q 0 And Q 1 The difference in base-emitter voltage differences. Due to BJT tube Q 0 And Q 1 The ratio of emitter areas is 2:1, thus Q 0 And Q 1 The difference between the base-emitter voltage differences is positive temperature coefficient voltage, which is calculated by R 8 Generating a positive temperature coefficient current I 1 The method comprises the following steps:
wherein V is T Is a thermal voltage.
And R is 9 The voltage drop on the BJT tube corresponds to the BJT tube Q 2 The voltage is negative temperature coefficient voltage, and generates negative temperature coefficient current I 2 Is that
In FIG. 1, as can be seen from the KVL theorem, deltaV GS ＝ΔV BE Wherein DeltaV GS Representing the difference in gate-source voltage differences, deltaV, of M1, M2 BE Represents Q 5 ，Q 3 Is a difference in base-emitter voltage differences. Because of Q 5 ，Q 3 The emitter areas are equal, so
Wherein I is COMP The current output by the circuit of fig. 1 is used to compensate for the higher order nonlinear term of the output reference voltage.
From KCL theorem
Due to Q 5 ，Q 4 ，Q 3 All operate in constant current region, and M 1 ，M 2 With the same on voltage, so
Where μ (T) is a function of carrier mobility as a function of temperature, in generalBeta (T) is a function of the common emitter current gain as a function of temperature, typically +.>Wherein beta is ∞ Is the maximum common emitter current gain, ΔE, of the BJT g Is the emitter forbidden band width.
Due to Q 5 Base current of (2)Far less than->It is ignored. Substitution into I 1 ，I 2 The compensation current can be solved:
by adjusting the correlation coefficient, I COMP Can be used for fitting a curveThereby reducing the effects of higher order terms. I COMP The simulation results of (2) are shown in fig. 3.
It can be seen from FIG. 3 that the prior art scheme has the disadvantage that when the temperature is small, the fitting effect between the compensation current and the nonlinear term is poor, and V is finally generated BG The accuracy of (2) is lowered.
Disclosure of Invention
The invention aims to provide a band gap reference circuit based on broken line compensation, which mainly solves the problem that the temperature coefficient of output voltage is larger when the temperature of the existing band gap reference circuit is smaller.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
a bandgap reference circuit based on broken line compensation comprises I for generating PTAT current proportional to temperature PTAT A generator for generating a CTAT current I inversely proportional to temperature by using the PTAT current CTAT A generator for generating I of BASE current for compensation by PTAT current BASE A generator for generating I of FOLD current for FOLD line compensation by PTAT current and CTAT current FOLD A generator for generating a reference voltage VBG using PTAT current, CTAT current and BASE BASE current and performing foldback using FOLD current BG A generator.
Further, in the present invention, the I PTAT The generator comprises 18 MOS tubes M 1 ～M 18 5 transistors Q 1 ～Q 5 And resistance R 1 Resistance R 2 The method comprises the steps of carrying out a first treatment on the surface of the Wherein, MOS tube M 1 Gate and source of (a) and MOS transistor M 2 The grid electrode and the source electrode are correspondingly connected, and the MOS tube M 3 Source electrode of (d) and MOS transistor M 1 Is connected with the drain electrode of the MOS tube M 4 Source electrode of (d) and MOS transistor M 2 Is connected with the drain electrode of the MOS tube M 3 Gate and MOS tube M of (2) 4 Gate electrode of MOS tube M is connected with 4 Drain electrode of (d) and MOS transistor M 2 Gate electrode of MOS tube M is connected with 5 Gate and MOS tube M of (2) 6 Gate electrode of MOS tube M is connected with 5 Drain electrode of (d) and MOS transistor M 3 Is connected with the drain electrode of the MOS tube M 5 Gate and MOS tube M of (2) 5 Is connected with the drain electrode of the MOS tube M 6 Drain electrode of (d) and MOS transistor M 4 Is connected to the drain of transistor Q 1 Is connected with the base electrode and the collector electrode and then is connected with the MOS tube M 5 Is connected to the source of transistor Q 2 Collector electrode of (d) and MOS transistor M 6 Is connected to the source of transistor Q 5 Is connected with the base electrode and the collector electrode of the transistor Q 1 Emitter connected to resistor R 1 Connected to transistor Q 1 Emitter and transistor Q of (2) 5 Between the emitters of (a), resistance R 2 Connected to transistor Q 2 Emitter and transistor Q of (2) 5 Between the collector electrodes of MOS tube M 7 Gate and source of (a) and MOS transistor M 8 The grid electrode and the source electrode are correspondingly connected, and the MOS tube M 9 Source electrode of (d) and MOS transistor M 7 Is connected with the drain electrode of the MOS tube M 10 Source electrode of (d) and MOS transistor M 8 Is connected with the drain electrode of the MOS tube M 9 Gate and MOS tube M of (2) 10 Gate electrode of MOS tube M is connected with 11 Gate and MOS tube M of (2) 12 Gate electrode of MOS tube M is connected with 11 Drain electrode of (d) and MOS transistor M 9 Is connected with the drain electrode of the MOS tube M 12 Drain electrode of (d) and MOS transistor M 10 Is connected to the drain of transistor Q 3 Collector electrode of (d) and MOS transistor M 11 Is connected to the source of transistor Q 4 Collector electrode of (d) and MOS transistor M 12 Is connected with the source electrode of the MOS tube M 13 Gate and MOS tube M of (2) 9 Is connected with the drain electrode of the MOS tube M 13 Source of (d) and transistor Q 3 Is connected with the base of transistor Q 2 Is connected to the base of transistor Q 3 Emitter and transistor Q of (2) 4 Is connected with the emitter of the transistor Q 5 Is connected with the collector electrode of the MOS tube M 15 Gate and source of (a) and MOS transistor M 16 The grid electrode and the source electrode are correspondingly connected, and the MOS tube M 15 Gate and MOS tube M of (2) 15 Is connected with the drain electrode of the MOS tube M 14 Drain electrode of (d) and MOS transistor M 15 Is connected with the drain electrode of the MOS tube M 14 Source of (d) and transistor Q 4 Is connected with the base electrode of the MOS tube M 14 Gate and MOS tube M of (2) 12 Is connected with the drain electrode of the MOS tube M 17 Is connected with the grid electrode and the drain electrode of the MOS tube M 16 Is connected with the drain electrode of the MOS tube M 18 Gate and source of (a) and MOS transistor M 17 The grid electrode and the source electrode are correspondingly connected, and the MOS tube M 18 Drain of (d) and transistor Q 2 Is connected with the emitter of the MOS tube M 18 Source of (d) and transistor Q 5 The emitter of the capacitor is connected with the ground; wherein, MOS tube M 1 Source electrode of (2), MOS tube M 2 Source electrode of (2), MOS tube M 7 Source electrode of (2), MOS tube M 8 Source electrode of (2), MOS tube M 15 Source electrode of (2), MOS tube M 16 Source electrode of (2) and MOS transistor M 13 The drains of which are connected with a power supply V DD 。
Further, in the present invention, the I CTAT The generator comprises 14 MOS tubes M 19 ～M 31 、M 200 3 transistors Q 6 ～Q 8 And resistance R 3 Resistance R 4 The method comprises the steps of carrying out a first treatment on the surface of the MOS tube M 19 Gate and MOS tube M of (2) 1 Gate electrode of MOS tube M is connected with 20 Gate and MOS tube M of (2) 3 Is connected with the grid electrode of the power supply; MOS tube M 19 Drain electrode of (d) and MOS transistor M 20 Is connected with the source electrode of the MOS tube M 22 Gate and source of (a) and MOS transistor M 23 The grid electrode and the source electrode of the MOS tube M are correspondingly connected 20 Drain electrode of (d) and MOS transistor M 21 Gate electrode of MOS tube M is connected with 21 Drain electrode of (d) and MOS transistor M 22 Is connected to the drain of transistor Q 6 Collector electrode of (d) and MOS transistor M 21 Is connected to the gate of transistor Q 6 Base electrode of (d) and MOS transistor M 21 Is connected with the source electrode of the MOS tube M 24 Gate and MOS tube M of (2) 22 The grid electrode and the drain electrode of the resistor R are connected 3 Is connected with MOS tube M 23 Drain of (d) and transistor Q 6 Between the emitters of (a), resistance R 4 Is connected with MOS tube M 24 Drain of (d) and transistor Q 6 Between the emitters of MOS tube M 27 Gate and source of (a) and MOS transistor M 28 The grid electrode and the source electrode of the MOS tube M are correspondingly connected 29 Gate and MOS tube M of (2) 30 Is connected with the grid electrode of the MOS tube M 20 Gate electrode of MOS tube M is connected with 29 Source electrode of (d) and MOS transistor M 27 Is connected with the drain electrode of the MOS tube M 30 Source electrode of (d) and MOS transistor M 28 Is connected to the drain of transistor Q 7 Collector electrode of (d) and MOS transistor M 25 Is connected with the grid electrode of the MOS tube M 29 Is connected with the drain electrode of the MOS tube M 200 Is connected with the grid electrode and then is connected with the MOS tube M 25 Is connected to the drain of transistor Q 7 Base electrode of (d) and MOS transistor M 25 Is connected with the MOS tube M after the source electrode of the transistor is connected with 24 Is connected to the drain of transistor Q 8 Collector electrode of (d) and MOS transistor M 26 Is connected with the grid electrode of the MOS tube M 30 Is connected to the drain of transistor Q 8 Base electrode of (d) and MOS transistor M 26 Is connected with the MOS tube M after the source electrode of the transistor is connected with 23 Is connected to the drain of transistor Q 7 Emitter and transistor Q of (2) 8 Is connected with the emitter of the transistor Q 6 The emitter of the MOS tube M is connected with the ground 31 Is connected with the drain electrode and the grid electrode of the MOS tube M 26 Is connected with the drain electrode of the transistor; wherein, MOS tube M 19 Source electrode of (2), MOS tube M 22 Source electrode of (2), MOS tube M 23 Source electrode of (2), MOS tube M 24 Source electrode of (2), MOS tube M 27 Source electrode of (2), MOS tube M 28 Source electrode of (2), MOS tube M 31 And MOS tube M 200 The sources of (a) are connected with a power supply V DD The method comprises the steps of carrying out a first treatment on the surface of the MOS tube M 31 Is connected with the drain electrode and the grid electrode and then is connected with I FOLD The generator is connected.
Further, in the present invention, the I BASE The generator comprises 6 MOS tubes M 32 ～M 37 And a transistor Q 9 Composition, MOS tube M 32 Gate and MOS tube M of (2) 1 Is a gate of (2)The poles are connected with each other, and the MOS tube M 33 Gate and MOS tube M of (2) 3 Gate electrode of MOS tube M is connected with 32 Drain electrode of (d) and MOS transistor M 33 Is connected with the source electrode of the MOS tube M 37 Gate and MOS tube M of (2) 33 Is connected with the drain electrode of transistor Q 9 Is connected with the collector electrode of the MOS tube M 37 Source of (d) and transistor Q 9 Is connected with the base electrode of the MOS tube M 36 Source of (d) and transistor Q 9 The emitter of the MOS tube M is connected with the ground 36 Is connected with the grid electrode and the drain electrode and then is connected with the MOS tube M 35 Is connected with the drain electrode of the MOS tube M 35 Gate and MOS tube M of (2) 34 Is connected with the grid electrode of I FOLD The generator is connected with the MOS tube M 34 Is connected with the grid electrode and the drain electrode and then is connected with the MOS tube M 37 Is connected with the drain electrode of the transistor; wherein, MOS tube M 32 Source electrode of (2), MOS tube M 34 Source electrode of (2) and MOS transistor M 35 The sources of (a) are connected with a power supply V DD 。
Further, in the present invention, the I FOLD The generator consists of 23 MOS tubes M 38 ～M 60 And 6 resistors R 5 ～R 10 Composition, the MOS tube M 60 Gate and MOS tube M of (2) 200 Gate electrode of MOS tube M is connected with 60 Drain of (d) and resistor R 5 Is connected with one end of MOS tube M 38 Drain of (d) and resistor R 5 Is connected with the other end of the MOS tube M 38 Gate and MOS tube M of (2) 60 Is connected with the drain electrode of the MOS tube M 38 Source electrode of (d) and MOS transistor M 39 Is connected with the drain electrode of the MOS tube M 39 Gate and MOS tube M of (2) 38 Is connected with the drain electrode of the MOS tube M 40 MOS tube M 41 MOS tube M 42 And MOS tube M 43 Drain electrodes of (C) are all connected with MOS tube M 38 Gate electrode of MOS tube M is connected with 44 Drain electrode of (d) and MOS transistor M 40 Is connected with the source electrode of the MOS tube M 45 Drain electrode of (d) and MOS transistor M 41 Is connected with the source electrode of the MOS tube M 46 Drain electrode of (d) and MOS transistor M 42 Is connected with the source electrode of the MOS tube M 47 Drain electrode of (d) and MOS transistor M 43 Is connected with the source electrode of the MOS tube M 48 Gate and MOS tube M of (2) 40 Is connected with the source electrode of the MOS tube M 49 Gate and MOS tube M of (2) 41 Is connected with the source electrode of the MOS tube M 50 Is a gate of (2)Electrode and MOS tube M 42 Is connected with the source electrode of the MOS tube M 51 Gate and MOS tube M of (2) 43 Is connected with the source electrode of the MOS tube M 52 MOS tube M 53 MOS tube M 54 And MOS tube M 55 The grid electrode of the transistor is all connected with the MOS tube M 39 Gate electrode of MOS tube M is connected with 48 MOS tube M 49 MOS tube M 50 And MOS tube M 51 Source electrode of (d) and MOS transistor M 52 MOS tube M 53 MOS tube M 54 And MOS tube M 55 The drains of the MOS transistors M are correspondingly connected 39 MOS tube M 52 MOS tube M 53 MOS tube M 54 And MOS tube M 55 Source of (d) and resistor R 6 ～R 10 One end of (a) is correspondingly connected with the resistor R 6 ～R 10 Is provided with the other end and MOS tube M 44 MOS tube M 45 MOS tube M 46 And MOS tube M 47 The source electrode of the MOS tube M is connected with the ground 57 Drain electrode of (d) and MOS transistor M 51 Is connected with the drain electrode of the MOS tube M 56 Drain electrode of (d) and MOS transistor M 57 Is connected with the source electrode of the MOS tube M 59 Is connected with the drain electrode and the grid electrode of the MOS tube M 51 Is connected with the drain electrode of the MOS tube M 58 Is connected with the drain electrode and the grid electrode of the MOS tube M 59 Is connected with the source electrode of the MOS tube M 56 Gate and MOS tube M of (2) 1 Gate electrode of MOS tube M is connected with 57 Gate and MOS tube M of (2) 3 Gate electrode of MOS tube M is connected with 60 Source electrode of (2), MOS tube M 56 Source electrode of (2) and MOS transistor M 58 The sources of (a) are connected with a power supply V DD MOS tube M 58 Is connected with the grid electrode and then is connected with V BG The generator is connected.
Further, in the present invention, the V BG The generator comprises 3 curvature compensation modules which are identical in circuit structure and are connected in series, and a broken line compensation module which is connected with the curvature compensation module of the last stage.
Further, in the present invention, the curvature compensation module is composed of 9 MOS tubes M 61 ～M 69 And 2 transistors Q 10 、Q 11 Composition; the MOS tube M 61 Gate and MOS tube M of (2) 62 Gate electrode of MOS tube M is connected with 61 Is connected with the grid electrode and the drain electrode and then is connected with the MOS tube M 63 Is connected with the drain electrode of the MOS tube M 63 Gate and MOS tube M of (2) 65 Is connected with the drain electrode of transistor Q 10 Is connected with the collector electrode of the MOS tube M 65 Source electrode of (d) and MOS transistor M 64 Is connected with the drain electrode of the MOS tube M 62 Drain of (d) and transistor Q 10 Is connected with the base of transistor Q 11 Is connected with the base electrode of the MOS tube M 67 Drain electrode of (d) and MOS transistor M 69 Is connected with the drain electrode of transistor Q 11 Is connected with the collector electrode of the MOS tube M 66 Drain electrode of (d) and MOS transistor M 67 Is connected with the source electrode of the MOS tube M 68 Drain of (d) and transistor Q 11 Is connected with the MOS tube M of the next stage after the emitter of the MOS tube M is connected with the emitter of the next stage 63 Source electrode of MOS tube with same position and MOS tube M 68 Gate of (d) and transistor Q 11 Is connected with the collector electrode of the MOS tube M 63 Source, transistor Q 10 Emitter and MOS transistor M of (2) 68 The source electrode of the MOS tube M is connected with the ground 61 Source electrode of (2), MOS tube M 62 Source electrode of (2), MOS tube M 66 Source electrode of (2) and MOS transistor M 69 The sources of (a) are connected with a power supply V DD MOS tube M 64 Gate and MOS transistor M of (2) 66 Is connected with the grid electrode of the MOS tube M 1 Gate electrode of MOS tube M is connected with 65 Gate and MOS transistor M of (2) 67 Is connected with the grid electrode of the MOS tube M 3 Is connected to the gate of (c).
Further, in the invention, the fold line compensation module consists of 14 MOS tubes M 88 ～M 101 2 transistors Q 16 、Q 17 And 3 resistors R 11 ～R 13 Composition; MOS tube M 88 Drain electrode of (d) and MOS transistor M 89 Is connected with the source electrode of the MOS tube M 89 MOS tube M in the same first-stage curvature compensation module in the drain electrode and the last-stage curvature compensation module 68 The drains of the MOS tubes with the same positions are connected, and the resistor R 11 One end of (2) is connected with MOS tube M 89 Is connected with the drain electrode of the resistor R 11 And transistor Q 16 Is connected with the emitter of the MOS tube M 93 Drain electrode of (d) and MOS transistor M 94 Is connected with the gate of transistor Q 16 Is connected with the collector electrode of the MOS tube M 93 Source electrode of (2) and MOS transistor M 92 Is connected with the drain electrode of MOS tube M 90 The grid electrode is connected with the drain electrode and then connected with the MOS tube M 94 Is connected with the drain electrode of the MOS tube M 90 Gate and MOS transistor M of (2) 91 Gate electrode of MOS tube M is connected with 91 Drain of (d) and transistor Q 16 Is connected with the base of transistor Q 17 Is connected with the base electrode of the MOS tube M 99 Drain electrode of (d) and MOS transistor M 100 Is connected with the drain electrode of transistor Q 17 Is connected with the collector electrode of the MOS tube M 98 Drain electrode of (d) and MOS transistor M 99 Is connected with the source electrode of the MOS tube M 99 Drain electrode of (d) and MOS transistor M 101 Is connected with the source electrode of the MOS tube M 95 Source electrode of (d) and MOS transistor M 96 Is connected with the source of transistor Q 16 Is connected with the emitter of the MOS tube M 97 Drain of (d) and transistor Q 17 Emitter connected to resistor R 13 One end of (2) is connected with MOS tube M 97 Is connected with the drain electrode of the resistor R 13 And the other end of (2) is connected with resistor R 12 Is connected to one end of resistor R 12 And transistor Q 17 Is connected with the base electrode of the MOS tube M 94 Source electrode of (2), MOS tube M 95 Drain electrode of (d), MOS transistor M 96 Drain electrode of (d), MOS transistor M 101 Drain electrode of (d) and MOS transistor M 97 The source electrodes of the MOS tube M are all grounded 90 Source electrode of (2), MOS tube M 91 Source electrode of (2), MOS tube M 98 Source electrode of (2) and MOS transistor M 100 The sources of (a) are connected with a power supply V DD MOS tube M 92 Gate and MOS transistor M of (2) 98 Is connected with the grid electrode of the MOS tube M 1 Gate electrode of MOS tube M is connected with 93 Gate and MOS transistor M of (2) 99 Is connected with the grid electrode of the MOS tube M 3 Gate electrode of MOS tube M is connected with 100 Gate and MOS tube M of (2) 31 Gate electrode of MOS tube M is connected with 101 Gate and MOS tube M of (2) 58 Is connected with the grid electrode of the resistor R 13 And resistance R 12 The connected common terminal generates a bandgap reference voltage VBG.
Further, in the present invention, it further includes generating I of Trim current for compensating unavoidable errors in the production process by using PTAT current and CTAT current TRIM A generator.
Compared with the prior art, the invention has the following beneficial effects:
the band gap voltage reference circuit of the invention is provided with I FOLD The generator generates a folding current I with a current value not equal to 0 only when the temperature is smaller than the set temperature FOLD The compensation is carried out on the part of the original output voltage with the temperature smaller than the set temperature, so that a more ideal temperature coefficient is obtained. The design solves the problem of larger temperature coefficient of output voltage when the temperature is smaller in the prior art, and obtains the band-gap reference voltage which is more stable along with the temperature change. At the same time, this compensation is a precise compensation for a specific temperature interval, that is to say only for I FOLD The temperature coefficient of the output reference voltage can be met by adjusting, so that the temperature coefficient adjusting device has a wider application range.
Drawings
Fig. 1 is a schematic diagram of a prior art high-order compensation circuit.
Fig. 2 is a schematic diagram of a bias current generating circuit in the prior art.
FIG. 3 is a graph of a normalized compensation current simulation of the prior art.
Fig. 4 is a block diagram of an embodiment of the present invention.
FIG. 5 shows I in an embodiment of the invention PTAT The circuit structure of the generator is schematically shown.
FIG. 6 is a diagram of I in an embodiment of the invention CTAT The circuit structure of the generator is schematically shown.
FIG. 7 shows an embodiment I of the present invention BASE The circuit structure of the generator is schematically shown.
FIG. 8 is a diagram of I in an embodiment of the invention FOLD The circuit structure of the generator is schematically shown.
FIG. 9 is a diagram of V in an embodiment of the invention BG The circuit structure of the generator is schematically shown.
FIG. 10 is a diagram of I in an embodiment of the invention TRIM The circuit structure of the generator is schematically shown.
FIG. 11 is a diagram of I in an embodiment of the invention PTAT And I CTAT Is a simulation graph of (1).
FIG. 12 is a diagram of I in an embodiment of the invention FOLD Is a simulation graph of (1).
FIG. 13 is a simulation diagram of an embodiment of the present invention without polyline compensation.
FIG. 14 is a simulation diagram of polyline compensation in an embodiment of the present invention.
Detailed Description
The invention will be further illustrated by the following description and examples, which include but are not limited to the following examples.
Examples
As shown in FIG. 4, the bandgap reference circuit based on foldback according to the present invention comprises I for generating PTAT current proportional to temperature PTAT A generator for generating a CTAT current I inversely proportional to temperature by using the PTAT current CTAT A generator for generating I of BASE current for compensation by PTAT current BASE A generator for generating I of FOLD current for FOLD line compensation by PTAT current and CTAT current FOLD A generator for generating a reference voltage VBG using PTAT current, CTAT current and BASE BASE current and performing foldback using FOLD current BG A generator. The circuit is mainly composed of I FOLD The generator generates a folding current I with a current value not equal to 0 only when the temperature is smaller than the set temperature FOLD The compensation is carried out on the part of the original output voltage with the temperature smaller than the set temperature, so that a more ideal temperature coefficient is obtained. The design solves the problem of larger temperature coefficient of output voltage when the temperature is smaller in the prior art, and obtains the band-gap reference voltage which is more stable along with the temperature change.
In the present embodiment, as shown in FIG. 5, the said I PTAT The generator comprises 18 MOS tubes M 1 ～M 18 5 transistors Q 1 ～Q 5 And resistance R 1 Resistance R 2 The method comprises the steps of carrying out a first treatment on the surface of the Wherein, MOS tube M 1 Gate and source of (a) and MOS transistor M 2 The grid electrode and the source electrode are correspondingly connected, and the MOS tube M 3 Source electrode of (d) and MOS transistor M 1 Is connected with the drain electrode of the MOS tube M 4 Source electrode of (d) and MOS transistor M 2 Is connected with the drain electrode of the MOS tube M 3 Gate and MOS tube M of (2) 4 Gate electrode of MOS tube M is connected with 4 Drain electrode of (d) and MOS transistor M 2 Gate electrode of (C) is connected with MOS tubeM 5 Gate and MOS tube M of (2) 6 Gate electrode of MOS tube M is connected with 5 Drain electrode of (d) and MOS transistor M 3 Is connected with the drain electrode of the MOS tube M 5 Gate and MOS tube M of (2) 5 Is connected with the drain electrode of the MOS tube M 6 Drain electrode of (d) and MOS transistor M 4 Is connected to the drain of transistor Q 1 Is connected with the base electrode and the collector electrode and then is connected with the MOS tube M 5 Is connected to the source of transistor Q 2 Collector electrode of (d) and MOS transistor M 6 Is connected to the source of transistor Q 5 Is connected with the base electrode and the collector electrode of the transistor Q 1 Emitter connected to resistor R 1 Connected to transistor Q 1 Emitter and transistor Q of (2) 5 Between the emitters of (a), resistance R 2 Connected to transistor Q 2 Emitter and transistor Q of (2) 5 Between the collector electrodes of MOS tube M 7 Gate and source of (a) and MOS transistor M 8 The grid electrode and the source electrode are correspondingly connected, and the MOS tube M 9 Source electrode of (d) and MOS transistor M 7 Is connected with the drain electrode of the MOS tube M 10 Source electrode of (d) and MOS transistor M 8 Is connected with the drain electrode of the MOS tube M 9 Gate and MOS tube M of (2) 10 Gate electrode of MOS tube M is connected with 11 Gate and MOS tube M of (2) 12 Gate electrode of MOS tube M is connected with 11 Drain electrode of (d) and MOS transistor M 9 Is connected with the drain electrode of the MOS tube M 12 Drain electrode of (d) and MOS transistor M 10 Is connected to the drain of transistor Q 3 Collector electrode of (d) and MOS transistor M 11 Is connected to the source of transistor Q 4 Collector electrode of (d) and MOS transistor M 12 Is connected with the source electrode of the MOS tube M 13 Gate and MOS tube M of (2) 9 Is connected with the drain electrode of the MOS tube M 13 Source of (d) and transistor Q 3 Is connected with the base of transistor Q 2 Is connected to the base of transistor Q 3 Emitter and transistor Q of (2) 4 Is connected with the emitter of the transistor Q 5 Is connected with the collector electrode of the MOS tube M 15 Gate and source of (a) and MOS transistor M 16 The grid electrode and the source electrode are correspondingly connected, and the MOS tube M 15 Gate and MOS tube M of (2) 15 Is connected with the drain electrode of the MOS tube M 14 Drain electrode of (d) and MOS transistor M 15 Is connected with the drain electrode of the MOS tube M 14 Source of (d) and transistor Q 4 Is connected with the base electrode of the MOS tube M 14 Gate and MOS of (2)Tube M 12 Is connected with the drain electrode of the MOS tube M 17 Is connected with the grid electrode and the drain electrode of the MOS tube M 16 Is connected with the drain electrode of the MOS tube M 18 Gate and source of (a) and MOS transistor M 17 The grid electrode and the source electrode are correspondingly connected, and the MOS tube M 18 Drain of (d) and transistor Q 2 Is connected with the emitter of the MOS tube M 18 Source of (d) and transistor Q 5 The emitter of the capacitor is connected with the ground; wherein, MOS tube M 1 Source electrode of (2), MOS tube M 2 Source electrode of (2), MOS tube M 7 Source electrode of (2), MOS tube M 8 Source electrode of (2), MOS tube M 15 Source electrode of (2), MOS tube M 16 Source electrode of (2) and MOS transistor M 13 The drains of which are connected with a power supply V DD 。
At I PTAT In the generator, transistor Q 2 、Q 3 Emitter voltage difference DeltaV of (2) BE ＝V T ln (N), where V T Is a thermal voltage, N is Q 2 And Q 3 Area ratio of (2). It can be seen that DeltaV BE Is PTAT voltage and thus flows through resistor R 2 The current of (2) is also PTAT current, set as I PTAT . Due to MOS tube M 2 And M 8 ，M 4 And M 10 ，M 6 And M 12 The gate voltages are the same and are VP 1 ，VP 2 And VN 1 Thus flowing through transistor Q 2 、Q 4 The current at the collector is the same. At the same time due to transistor Q 2 、Q 4 The areas of (2) are the same, so are their base currents, I BASE . And Q is 4 The base current of (2) is copied to the MOS tube M through a current mirror 18 Thus if to BJT Q 2 The KCL can be used to obtain the MOS tube M 6 Current I M6 ＝I PTAT +I BASE -I BASE ＝I PTAT . And I M6 May be utilized by other modules through a current mirror.
In the present embodiment, as shown in FIG. 6, the said I CTAT The generator comprises 14 MOS tubes M 19 ～M 31 、M 200 3 transistors Q 6 ～Q 8 And resistance R 3 Resistance R 4 The method comprises the steps of carrying out a first treatment on the surface of the MOS tube M 19 Gate and MOS tube M of (2) 1 Gate electrode of MOS tube M is connected with 20 Gate and MOS tube M of (2) 3 Is connected with the grid electrode of the power supply; MOS tube M 19 Drain electrode of (d) and MOS transistor M 20 Is connected with the source electrode of the MOS tube M 22 Gate and source of (a) and MOS transistor M 23 The grid electrode and the source electrode of the MOS tube M are correspondingly connected 20 Drain electrode of (d) and MOS transistor M 21 Gate electrode of MOS tube M is connected with 21 Drain electrode of (d) and MOS transistor M 22 Is connected to the drain of transistor Q 6 Collector electrode of (d) and MOS transistor M 21 Is connected to the gate of transistor Q 6 Base electrode of (d) and MOS transistor M 21 Is connected with the source electrode of the MOS tube M 24 Gate and MOS tube M of (2) 22 The grid electrode and the drain electrode of the resistor R are connected 3 Is connected with MOS tube M 23 Drain of (d) and transistor Q 6 Between the emitters of (a), resistance R 4 Is connected with MOS tube M 24 Drain of (d) and transistor Q 6 Between the emitters of MOS tube M 27 Gate and source of (a) and MOS transistor M 28 The grid electrode and the source electrode of the MOS tube M are correspondingly connected 29 Gate and MOS tube M of (2) 30 Is connected with the grid electrode of the MOS tube M 20 Gate electrode of MOS tube M is connected with 29 Source electrode of (d) and MOS transistor M 27 Is connected with the drain electrode of the MOS tube M 30 Source electrode of (d) and MOS transistor M 28 Is connected to the drain of transistor Q 7 Collector electrode of (d) and MOS transistor M 25 Is connected with the grid electrode of the MOS tube M 29 Is connected with the drain electrode of the MOS tube M 200 Is connected with the grid electrode and then is connected with the MOS tube M 25 Is connected to the drain of transistor Q 7 Base electrode of (d) and MOS transistor M 25 Is connected with the MOS tube M after the source electrode of the transistor is connected with 24 Is connected to the drain of transistor Q 8 Collector electrode of (d) and MOS transistor M 26 Is connected with the grid electrode of the MOS tube M 30 Is connected to the drain of transistor Q 8 Base electrode of (d) and MOS transistor M 26 Is connected with the MOS tube M after the source electrode of the transistor is connected with 23 Is connected to the drain of transistor Q 7 Emitter and transistor Q of (2) 8 Is connected with the emitter of the transistor Q 6 The emitter of the MOS tube M is connected with the ground 31 Is connected with the drain electrode and the grid electrode of the MOS tube M 26 Is connected with the drain electrode of the transistor; wherein, MOS tube M 19 Source electrode of (2), MOS tube M 22 Source electrode of (2), MOS tube M 23 Is a source of (a)Electrode and MOS tube M 24 Source electrode of (2), MOS tube M 27 Source electrode of (2), MOS tube M 28 Source electrode of (2), MOS tube M 31 And MOS tube M 200 The sources of (a) are connected with a power supply V DD The method comprises the steps of carrying out a first treatment on the surface of the MOS tube M 31 Is connected with the drain electrode and the grid electrode and then is connected with I FOLD The generator is connected.
In fig. 6, VP3 x=vp 3 (because I PTAT The generator is made up of two identical PTAT generators).
At I CTAT In the generator, due to the MOS tube M 27 And M 29 Is VP 1 And VP 2 So it flows through transistor Q 7 The current of the collector is I PTAT . Thus Q 7 Is a base-emitter voltage difference V BE Possess a negative temperature coefficient, being a CTAT voltage. Then flows through the resistor R 4 Is a CTAT current. But if only so, flows through the MOS transistor M 25 Current I of pole M25 ＝I CTAT +I BASE Wherein I BASE Is transistor Q 7 Is provided. Obviously this is not the CTAT current we want, so a base current compensation circuit is needed to cancel Q 7 Base current I of (2) BASE 。
MOS tube M 19 And M 20 Is VP 1 ，VP 2 Thus, the flow-through transistor Q can be obtained as well 6 The current of the collector is I PTAT . Due to Q 6 And Q 7 Has the same area, thus Q 7 Is also I BASE . Using a current mirror to couple I BASE Copy to MOS tube M 24 At this time, I can be obtained by using KCL theorem M25 ＝I CTAT +I BASE -I BASE ＝I CTAT . Thus obtaining the CTAT current we want.
The MOS tube M can be obtained by the same method 31 Is the current I of (2) M31 ＝I CTAT 。
In the present embodiment, as shown in FIG. 7, the said I BASE The generator comprises 6 MOS tubes M 32 ～M 37 And a transistor Q 9 Composition, MOS tube M 32 Gate and MOS tube M of (2) 1 Gate electrode of MOS tube M is connected with 33 Gate and MOS tube M of (2) 3 Gate electrode of MOS tube M is connected with 32 Drain electrode of (d) and MOS transistor M 33 Is connected with the source electrode of the MOS tube M 37 Gate and MOS tube M of (2) 33 Is connected with the drain electrode of transistor Q 9 Is connected with the collector electrode of the MOS tube M 37 Source of (d) and transistor Q 9 Is connected with the base electrode of the MOS tube M 36 Source of (d) and transistor Q 9 The emitter of the MOS tube M is connected with the ground 36 Is connected with the grid electrode and the drain electrode and then is connected with the MOS tube M 35 Is connected with the drain electrode of the MOS tube M 35 Gate and MOS tube M of (2) 34 Is connected with the grid electrode of I FOLD The generator is connected with the MOS tube M 34 Is connected with the grid electrode and the drain electrode and then is connected with the MOS tube M 37 Is connected with the drain electrode of the transistor; wherein, MOS tube M 32 Source electrode of (2), MOS tube M 34 Source electrode of (2) and MOS transistor M 35 The sources of (a) are connected with a power supply V DD 。
I BASE The purpose of the generator is to generate the compensated post V BG The current of the extra base current in the generator is shown in fig. 7. By combining I PTAT Implanted into transistor Q 9 The collector electrode of (2) obtains base current, and the base current is copied to the MOS tube M through a current mirror 36 On the basis of the above, I is obtained BASE 。
In the present embodiment, the I FOLD The generator consists of 23 MOS tubes M 38 ～M 60 And 6 resistors R 5 ～R 10 Composition, the MOS tube M 60 Gate and MOS tube M of (2) 200 Gate electrode of MOS tube M is connected with 60 Drain of (d) and resistor R 5 Is connected with one end of MOS tube M 38 Drain of (d) and resistor R 5 Is connected with the other end of the MOS tube M 38 Gate and MOS tube M of (2) 60 Is connected with the drain electrode of the MOS tube M 38 Source electrode of (d) and MOS transistor M 39 Is connected with the drain electrode of the MOS tube M 39 Gate and MOS tube M of (2) 38 Is connected with the drain electrode of the MOS tube M 40 MOS tube M 41 MOS tube M 42 And MOS tube M 43 Drain electrodes of (C) are all connected with MOS tube M 38 Gate electrode of MOS tube M is connected with 44 Drain of (2)And MOS tube M 40 Is connected with the source electrode of the MOS tube M 45 Drain electrode of (d) and MOS transistor M 41 Is connected with the source electrode of the MOS tube M 46 Drain electrode of (d) and MOS transistor M 42 Is connected with the source electrode of the MOS tube M 47 Drain electrode of (d) and MOS transistor M 43 Is connected with the source electrode of the MOS tube M 48 Gate and MOS tube M of (2) 40 Is connected with the source electrode of the MOS tube M 49 Gate and MOS tube M of (2) 41 Is connected with the source electrode of the MOS tube M 50 Gate and MOS tube M of (2) 42 Is connected with the source electrode of the MOS tube M 51 Gate and MOS tube M of (2) 43 Is connected with the source electrode of the MOS tube M 52 MOS tube M 53 MOS tube M 54 And MOS tube M 55 The grid electrode of the transistor is all connected with the MOS tube M 39 Gate electrode of MOS tube M is connected with 48 MOS tube M 49 MOS tube M 50 And MOS tube M 51 Source electrode of (d) and MOS transistor M 52 MOS tube M 53 MOS tube M 54 And MOS tube M 55 The drains of the MOS transistors M are correspondingly connected 39 MOS tube M 52 MOS tube M 53 MOS tube M 54 And MOS tube M 55 Source of (d) and resistor R 6 ～R 10 One end of (a) is correspondingly connected with the resistor R 6 ～R 10 Is provided with the other end and MOS tube M 44 MOS tube M 45 MOS tube M 46 And MOS tube M 47 The source electrode of the MOS tube M is connected with the ground 57 Drain electrode of (d) and MOS transistor M 51 Is connected with the drain electrode of the MOS tube M 56 Drain electrode of (d) and MOS transistor M 57 Is connected with the source electrode of the MOS tube M 59 Is connected with the drain electrode and the grid electrode of the MOS tube M 51 Is connected with the drain electrode of the MOS tube M 58 Is connected with the drain electrode and the grid electrode of the MOS tube M 59 Is connected with the source electrode of the MOS tube M 56 Gate and MOS tube M of (2) 1 Gate electrode of MOS tube M is connected with 57 Gate and MOS tube M of (2) 3 Gate electrode of MOS tube M is connected with 60 Source electrode of (2), MOS tube M 56 Source electrode of (2) and MOS transistor M 58 The sources of (a) are connected with a power supply V DD MOS tube M 58 Is connected with the grid electrode and then is connected with V BG The generator is connected.
A circuit diagram for generating a folding current is shown in fig. 8. I produced by it FOLD The following must be satisfied: 1. only at a temperature less than a specific temperatureThe current value is not 0 at the time of the degree; 2. the current level must be able to compensate for the bias of the bandgap reference voltage at small temperatures.
To meet these two requirements, the present embodiment considers utilizing the previously generated I PTAT And I CTAT To obtain the desired I FOLD . As shown in fig. 8, the switch Trim<0>～Trim<3>，Trim<0>B～Trim<3>B is controlled by programming mode for controlling MOS tube M 52 ～M 55 The on-off state of the four current mirrors is controlled to control I CTAT Is of a size of (a) and (b). Regulated I CTAT The current is subtracted by I PTAT After flowing to MOS tube M 59 Is provided. MOS tube M 52 The function of (2) is to cut off, only when I CTAT -I PTAT When the voltage is larger than zero, the MOS tube is turned on, and the MOS tube is turned off at other times. As can be seen from FIGS. 11 and 12 obtained by simulation, when I CTAT ＞I PTAT Time I FOLD The current value is inversely proportional to the temperature, when I CTAT <I PTAT Time I FOLD The current value is zero. That is to say folding current I FOLD Can be expressed as:
in this way, I is obtained which meets the requirements of the present embodiment FOLD 。
In the present embodiment, the V BG The generator comprises 3 curvature compensation modules which are identical in circuit structure and are connected in series, and a broken line compensation module which is connected with the curvature compensation module of the last stage. Wherein the curvature compensation module consists of 9 MOS tubes M 61 ～M 69 And 2 transistors Q 10 、Q 11 Composition; the MOS tube M 61 Gate and MOS tube M of (2) 62 Gate electrode of MOS tube M is connected with 61 Is connected with the grid electrode and the drain electrode and then is connected with the MOS tube M 63 Is connected with the drain electrode of the MOS tube M 63 Gate and MOS tube M of (2) 65 Is connected with the drain electrode of transistor Q 10 Is connected with the collector electrode of the MOS tube M 65 Source electrode of (d) and MOS transistor M 64 Drain phase of (a)MOS tube M 62 Drain of (d) and transistor Q 10 Is connected with the base of transistor Q 11 Is connected with the base electrode of the MOS tube M 67 Drain electrode of (d) and MOS transistor M 69 Is connected with the drain electrode of transistor Q 11 Is connected with the collector electrode of the MOS tube M 66 Drain electrode of (d) and MOS transistor M 67 Is connected with the source electrode of the MOS tube M 68 Drain of (d) and transistor Q 11 Is connected with the MOS tube M of the next stage after the emitter of the MOS tube M is connected with the emitter of the next stage 63 Source electrode of MOS tube with same position and MOS tube M 68 Gate of (d) and transistor Q 11 Is connected with the collector electrode of the MOS tube M 63 Source, transistor Q 10 Emitter and MOS transistor M of (2) 68 The source electrode of the MOS tube M is connected with the ground 61 Source electrode of (2), MOS tube M 62 Source electrode of (2), MOS tube M 66 Source electrode of (2) and MOS transistor M 69 The sources of (a) are connected with a power supply V DD MOS tube M 64 Gate and MOS transistor M of (2) 66 Is connected with the grid electrode of the MOS tube M 1 Gate electrode of MOS tube M is connected with 65 Gate and MOS transistor M of (2) 67 Is connected with the grid electrode of the MOS tube M 3 Is connected to the gate of (c).
In this embodiment, the broken line compensation module is formed by 14 MOS transistors M 88 ～M 101 2 transistors Q 16 、Q 17 And 3 resistors R 11 ～R 13 Composition; MOS tube M 88 Drain electrode of (d) and MOS transistor M 89 Is connected with the source electrode of the MOS tube M 89 MOS tube M in the same first-stage curvature compensation module in the drain electrode and the last-stage curvature compensation module 68 The drains of the MOS tubes with the same positions are connected, and the resistor R 11 One end of (2) is connected with MOS tube M 89 Is connected with the drain electrode of the resistor R 11 And transistor Q 16 Is connected with the emitter of the MOS tube M 93 Drain electrode of (d) and MOS transistor M 94 Is connected with the gate of transistor Q 16 Is connected with the collector electrode of the MOS tube M 93 Source electrode of (2) and MOS transistor M 92 Is connected with the drain electrode of the MOS tube M 90 The grid electrode is connected with the drain electrode and then connected with the MOS tube M 94 Is connected with the drain electrode of the MOS tube M 90 Gate and MOS transistor M of (2) 91 Gate electrode of MOS tube M is connected with 91 Drain of (d) and transistor Q 16 Is based on (2)The electrodes are connected with the transistor Q 17 Is connected with the base electrode of the MOS tube M 99 Drain electrode of (d) and MOS transistor M 100 Is connected with the drain electrode of transistor Q 17 Is connected with the collector electrode of the MOS tube M 98 Drain electrode of (d) and MOS transistor M 99 Is connected with the source electrode of the MOS tube M 99 Drain electrode of (d) and MOS transistor M 101 Is connected with the source electrode of the MOS tube M 95 Source electrode of (d) and MOS transistor M 96 Is connected with the source of transistor Q 16 Is connected with the emitter of the MOS tube M 97 Drain of (d) and transistor Q 17 Emitter connected to resistor R 13 One end of (2) is connected with MOS tube M 97 Is connected with the drain electrode of the resistor R 13 And the other end of (2) is connected with resistor R 12 Is connected to one end of resistor R 12 And transistor Q 17 Is connected with the base electrode of the MOS tube M 94 Source electrode of (2), MOS tube M 95 Drain electrode of (d), MOS transistor M 96 Drain electrode of (d), MOS transistor M 101 Drain electrode of (d) and MOS transistor M 97 The source electrodes of the MOS tube M are all grounded 90 Source electrode of (2), MOS tube M 91 Source electrode of (2), MOS tube M 98 Source electrode of (2) and MOS transistor M 100 The sources of (a) are connected with a power supply V DD MOS tube M 92 Gate and MOS transistor M of (2) 98 Is connected with the grid electrode of the MOS tube M 1 Gate electrode of MOS tube M is connected with 93 Gate and MOS transistor M of (2) 99 Is connected with the grid electrode of the MOS tube M 3 Gate electrode of MOS tube M is connected with 100 Gate and MOS tube M of (2) 31 Gate electrode of MOS tube M is connected with 101 Gate and MOS tube M of (2) 58 Is connected with the grid electrode of the resistor R 13 And resistance R 12 The connected common terminal generates a bandgap reference voltage VBG.
As one of key modules for performing broken line compensation, V is shown in figure 9 BG The generator is divided into two main parts, namely a curvature compensation module and a broken line compensation module, wherein the curvature compensation module consists of three identical submodules of No. 1, no. 2 and No. 3, as shown in fig. 10. Wherein the ellipsis section is a number 2 curvature compensation sub-module.
Since the voltage difference between the base-emitter of the transistor is:
wherein V is g0 Is the deduced bandgap voltage at 0K; t (T) r Is a reference temperature, typically selected to be near room temperature;is the base-emitter voltage at a temperature Tr; η is a normal number related to the process, generally 3 to 4; θ is the temperature index of the collector current; v (V) T Is a thermal voltage. It can be seen that V BE There is a higher-order term +.>It is this higher order term that results in non-linearities of the final bandgap voltage reference. We counteract this higher order term by curvature compensation and polyline compensation.
The curvature compensation is mainly performed by a curvature compensation module. Due to transistor Q 10 Collector current of (1) is PTAT current, transistor Q 11 The collector current of (1) is a constant current (the current temperature coefficient is 0), so transistor Q 10 The base-emitter voltage difference of (a) is:
transistor Q 11 The base-emitter voltage difference of (a) is:
thus transistor Q 10 And transistor Q 11 Is of DeltaV of (2) BE The method comprises the following steps:
if a plurality of DeltaV BE And the materials are overlapped to obtainTo partially cancel V BE The influence of higher-order terms in the expression. The invention uses 4 DeltaV BE Superposition (three DeltaV) BE Provided by a curvature compensation module, a DeltaV BE Provided by the polyline compensation module), the resulting simulation is fig. 13.
It can be seen that the last output reference voltage creates the same problems as in the prior art, creating a temperature coefficient dip at lower temperatures. Thus, this embodiment proposes a polyline compensation scheme.
The polyline compensation is performed by a polyline compensation module. As shown in fig. 9, flows through transistor Q 16 The current of the collector is I PTAT Flows through transistor Q 17 The current of the collector is I PTAT +I CTAT -I FOLD . Redundant current I FOLD Will result in transistor Q 17 Generates an additional voltage V between the base and the emitter FOLD And this V FOLD It is the key to polyline compensation. At this time transistor Q 16 And transistor Q 17 The emitter voltage difference of (2) is:
v of output BG And also receives current I TRIM And resistance R 12 And resistance R 13 Is a function of (a) and (b). The KCL theorem can obtain the flow-through resistance R 11 The current of (2) is I TRIM -I PTAT Thus at resistance R 11 Pressure drop V generated on 1 ＝R 11 I TRIM -R 11 I PTAT . All voltages are overlapped and then pass through a resistor R 12 And resistance R 13 The resulting bandgap reference voltage is:
the simulation diagram is shown in FIG. 14, it can be seen that due to V FOLD In the prior art, bandgap reference voltage isThe problem of large fluctuation at small temperature is solved well, and V is finally BG The temperature coefficient of (C) was 2.3 ppm/DEG C.
In another embodiment, the bandgap reference circuit is further provided with I for generating Trim current for compensating unavoidable errors in the production process using PTAT current and CTAT current TRIM A generator. Triming is a common means of current/voltage regulation. This embodiment generates Trim current to adjust the slope and absolute value of the final bandgap reference voltage to counteract the inevitable errors in processing. For easy regulation, trim current must meet the following three points: 1. the size is 0 at room temperature; 2. preferably in a linear relationship with temperature; 3. has stronger adjustability. Because of I PTAT And I CTAT Condition 2 has been satisfied, thus consider utilization of I PTAT And I CTAT To generate I TRIM . The circuit diagram is shown in fig. 10.
The Trim switch is controlled by programming, wherein the Trim switch<0>～Trim<6>，Trim<9>～Trim<14>Control I CTAT And I PTAT Is a size of (2), and switch Trim<8>，Trim<8>B control I CTAT And I PTAT Is a direction of (2). Finally obtaining the current I with the current value of zero at room temperature by adjusting Trim switch TRIM 。
Through the design, the band gap voltage reference circuit of the invention is characterized in that FOLD The generator generates a folding current I with a current value not equal to 0 only when the temperature is smaller than the set temperature FOLD The compensation is carried out on the part of the original output voltage with the temperature smaller than the set temperature, so that a more ideal temperature coefficient is obtained. The design solves the problem of larger temperature coefficient of output voltage when the temperature is smaller in the prior art, and obtains the band-gap reference voltage which is more stable along with the temperature change.
The above embodiment is only one of the preferred embodiments of the present invention, and should not be used to limit the scope of the present invention, but all the insubstantial modifications or color changes made in the main design concept and spirit of the present invention are still consistent with the present invention, and all the technical problems to be solved are included in the scope of the present invention.

Claims (8)

1. A bandgap reference circuit based on broken line compensation is characterized by comprising I for generating PTAT current proportional to temperature PTAT A generator for generating a CTAT current I inversely proportional to temperature by using the PTAT current CTAT A generator for generating I of BASE current for compensation by PTAT current BASE A generator for generating I of FOLD current for FOLD line compensation by PTAT current and CTAT current FOLD A generator for generating a reference voltage VBG using PTAT current, CTAT current and BASE BASE current and performing foldback using FOLD current BG A generator;
the I is FOLD The generator consists of 23 MOS tubes M 38 ～M 60 And 6 resistors R 5 ～R 10 Composition, the MOS tube M 60 Gate and I of (2) CTAT MOS tube M in generator 200 Gate electrode of MOS tube M is connected with 60 Drain of (d) and resistor R 5 Is connected with one end of MOS tube M 38 Drain of (d) and resistor R 5 Is connected with the other end of the MOS tube M 38 Gate and MOS tube M of (2) 60 Is connected with the drain electrode of the MOS tube M 38 Source electrode of (d) and MOS transistor M 39 Is connected with the drain electrode of the MOS tube M 39 Gate and MOS tube M of (2) 38 Is connected with the drain electrode of the MOS tube M 40 MOS tube M 41 MOS tube M 42 And MOS tube M 43 Drain electrodes of (C) are all connected with MOS tube M 38 Gate electrode of MOS tube M is connected with 44 Drain electrode of (d) and MOS transistor M 40 Is connected with the source electrode of the MOS tube M 45 Drain electrode of (d) and MOS transistor M 41 Is connected with the source electrode of the MOS tube M 46 Drain electrode of (d) and MOS transistor M 42 Is connected with the source electrode of the MOS tube M 47 Drain electrode of (d) and MOS transistor M 43 Is connected with the source electrode of the MOS tube M 48 Gate and MOS tube M of (2) 40 Is connected with the source electrode of the MOS tube M 49 Gate and MOS tube M of (2) 41 Is connected with the source electrode of the MOS tube M 50 Gate and MOS tube M of (2) 42 Is connected with the source electrode of the MOS tube M 51 Gate and MOS tube M of (2) 43 Is connected with the source electrode of the MOS tube M 52 MOS tube M 53 MOS tube M 54 And MOS tube M 55 The grid electrode of the transistor is all connected with the MOS tube M 39 Gate electrode of MOS tube M is connected with 48 MOS tube M 49 MOS tube M 50 And MOS tube M 51 Source electrode of (d) and MOS transistor M 52 MOS tube M 53 MOS tube M 54 And MOS tube M 55 The drains of the MOS transistors M are correspondingly connected 39 MOS tube M 52 MOS tube M 53 MOS tube M 54 And MOS tube M 55 Source of (d) and resistor R 6 ～R 10 One end of (a) is correspondingly connected with the resistor R 6 ～R 10 Is provided with the other end and MOS tube M 44 MOS tube M 45 MOS tube M 46 And MOS tube M 47 The source electrode of the MOS tube M is connected with the ground 57 Drain electrode of (d) and MOS transistor M 51 Is connected with the drain electrode of the MOS tube M 56 Drain electrode of (d) and MOS transistor M 57 Is connected with the source electrode of the MOS tube M 59 Is connected with the drain electrode and the grid electrode of the MOS tube M 51 Is connected with the drain electrode of the MOS tube M 58 Is connected with the drain electrode and the grid electrode of the MOS tube M 59 Is connected with the source electrode of the MOS tube M 56 Gate and I of (2) PTAT MOS tube M in generator 1 Gate electrode of MOS tube M is connected with 57 Gate and I of (2) PTAT MOS tube M in generator 3 Gate electrode of MOS tube M is connected with 60 Source electrode of (2), MOS tube M 56 Source electrode of (2) and MOS transistor M 58 The sources of (a) are connected with a power supply V DD MOS tube M 58 Is connected with the grid electrode and then is connected with V BG The generator is connected.
2. A bandgap reference circuit based on polyline compensation as claimed in claim 1, wherein said I PTAT The generator comprises 18 MOS tubes M 1 ～M 18 5 transistors Q 1 ～Q 5 And resistance R 1 Resistance R 2 The method comprises the steps of carrying out a first treatment on the surface of the Wherein, MOS tube M 1 Gate and source of (a) and MOS transistor M 2 The grid electrode and the source electrode are correspondingly connected, and the MOS tube M 3 Source electrode of (d) and MOS transistor M 1 Is connected with the drain electrode of the MOS tube M 4 Source electrode of (d) and MOS transistor M 2 Is connected with the drain electrode of the MOS tube M 3 Gate and MOS tube M of (2) 4 Gate electrode of MOS tube M is connected with 4 Drain electrode of (d) and MOS transistor M 2 Gate electrode of MOS tube M is connected with 5 Gate and MOS tube M of (2) 6 Gate electrode of MOS tube M is connected with 5 Drain electrode of (d) and MOS transistor M 3 Is connected with the drain electrode of the MOS tube M 5 Gate and MOS tube M of (2) 5 Is connected with the drain electrode of the MOS tube M 6 Drain electrode of (d) and MOS transistor M 4 Is connected to the drain of transistor Q 1 Is connected with the base electrode and the collector electrode and then is connected with the MOS tube M 5 Is connected to the source of transistor Q 2 Collector electrode of (d) and MOS transistor M 6 Is connected to the source of transistor Q 5 Is connected with the base electrode and the collector electrode of the transistor Q 1 Emitter connected to resistor R 1 Connected to transistor Q 1 Emitter and transistor Q of (2) 5 Between the emitters of (a), resistance R 2 Connected to transistor Q 2 Emitter and transistor Q of (2) 5 Between the collector electrodes of MOS tube M 7 Gate and source of (a) and MOS transistor M 8 The grid electrode and the source electrode are correspondingly connected, and the MOS tube M 9 Source electrode of (d) and MOS transistor M 7 Is connected with the drain electrode of the MOS tube M 10 Source electrode of (d) and MOS transistor M 8 Is connected with the drain electrode of the MOS tube M 9 Gate and MOS tube M of (2) 10 Gate electrode of MOS tube M is connected with 11 Gate and MOS tube M of (2) 12 Gate electrode of MOS tube M is connected with 11 Drain electrode of (d) and MOS transistor M 9 Is connected with the drain electrode of the MOS tube M 12 Drain electrode of (d) and MOS transistor M 10 Is connected to the drain of transistor Q 3 Collector electrode of (d) and MOS transistor M 11 Is connected to the source of transistor Q 4 Collector electrode of (d) and MOS transistor M 12 Is connected with the source electrode of the MOS tube M 13 Gate and MOS tube M of (2) 9 Is connected with the drain electrode of the MOS tube M 13 Source of (d) and transistor Q 3 Is connected with the base of transistor Q 2 Is connected to the base of transistor Q 3 Emitter and transistor Q of (2) 4 Is connected with the emitter of the transistor Q 5 Is connected with the collector electrode of the MOS tube M 15 Gate and source of (a) and MOS transistor M 16 The grid electrode and the source electrode are correspondingly connected, and the MOS tube M 15 Gate and MOS tube M of (2) 15 Is connected with the drain electrode of the MOS tube M 14 Drain electrode of (d) and MOS transistor M 15 Is connected with the drain electrode of the MOS tube M 14 Source of (d) and transistor Q 4 Is connected with the base electrode of the MOS tube M 14 Gate and MOS tube M of (2) 12 Is connected with the drain electrode of the MOS tube M 17 Is connected with the grid electrode and the drain electrode of the MOS tube M 16 Is connected with the drain electrode of the MOS tube M 18 Gate and source of (a) and MOS transistor M 17 The grid electrode and the source electrode are correspondingly connected, and the MOS tube M 18 Drain of (d) and transistor Q 2 Is connected with the emitter of the MOS tube M 18 Source of (d) and transistor Q 5 The emitter of the capacitor is connected with the ground; wherein, MOS tube M 1 Source electrode of (2), MOS tube M 2 Source electrode of (2), MOS tube M 7 Source electrode of (2), MOS tube M 8 Source electrode of (2), MOS tube M 15 Source electrode of (2), MOS tube M 16 Source electrode of (2) and MOS transistor M 13 The drains of which are connected with a power supply V DD 。
3. A bandgap reference circuit based on polyline compensation as claimed in claim 2, wherein said I CTAT The generator comprises 14 MOS tubes M 19 ～M 31 、M 200 3 transistors Q 6 ～Q 8 And resistance R 3 Resistance R 4 The method comprises the steps of carrying out a first treatment on the surface of the MOS tube M 19 Gate and MOS tube M of (2) 1 Gate electrode of MOS tube M is connected with 20 Gate and MOS tube M of (2) 3 Is connected with the grid electrode of the power supply; MOS tube M 19 Drain electrode of (d) and MOS transistor M 20 Is connected with the source electrode of the MOS tube M 22 Gate and source of (a) and MOS transistor M 23 The grid electrode and the source electrode of the MOS tube M are correspondingly connected 20 Drain electrode of (d) and MOS transistor M 21 Gate electrode of MOS tube M is connected with 21 Drain electrode of (d) and MOS transistor M 22 Is connected to the drain of transistor Q 6 Collector electrode of (d) and MOS transistor M 21 Is connected to the gate of transistor Q 6 Base electrode of (d) and MOS transistor M 21 Is connected with the source electrode of the MOS tube M 24 Gate and MOS tube M of (2) 22 The grid electrode and the drain electrode of the resistor R are connected 3 Is connected with MOS tube M 23 Drain of (d) and transistor Q 6 Between the emitters of (a), resistance R 4 Is connected with MOS tube M 24 Drain of (d) and transistor Q 6 Between the emitters of MOS tube M 27 Gate and source of (a) and MOS transistor M 28 The grid electrode and the source electrode of the MOS tube M are correspondingly connected 29 Gate and MOS tube M of (2) 30 Is connected with the grid electrode of the MOS tube M 20 Gate electrode of MOS tube M is connected with 29 Source electrode of (d) and MOS transistor M 27 Is connected with the drain electrode of the MOS tube M 30 Source electrode of (d) and MOS transistor M 28 Is connected to the drain of transistor Q 7 Collector electrode of (d) and MOS transistor M 25 Is connected with the grid electrode of the MOS tube M 29 Is connected with the drain electrode of the MOS tube M 200 Is connected with the grid electrode and then is connected with the MOS tube M 25 Is connected to the drain of transistor Q 7 Base electrode of (d) and MOS transistor M 25 Is connected with the MOS tube M after the source electrode of the transistor is connected with 24 Is connected to the drain of transistor Q 8 Collector electrode of (d) and MOS transistor M 26 Is connected with the grid electrode of the MOS tube M 30 Is connected to the drain of transistor Q 8 Base electrode of (d) and MOS transistor M 26 Is connected with the MOS tube M after the source electrode of the transistor is connected with 23 Is connected to the drain of transistor Q 7 Emitter and transistor Q of (2) 8 Is connected with the emitter of the transistor Q 6 The emitter of the MOS tube M is connected with the ground 31 Is connected with the drain electrode and the grid electrode of the MOS tube M 26 Is connected with the drain electrode of the transistor; wherein, MOS tube M 19 Source electrode of (2), MOS tube M 22 Source electrode of (2), MOS tube M 23 Source electrode of (2), MOS tube M 24 Source electrode of (2), MOS tube M 27 Source electrode of (2), MOS tube M 28 Source electrode of (2), MOS tube M 31 And MOS tube M 200 The sources of (a) are connected with a power supply V DD The method comprises the steps of carrying out a first treatment on the surface of the MOS tube M 31 Is connected with the drain electrode and the grid electrode and then is connected with I FOLD The generator is connected.
4. A bandgap reference circuit based on polyline compensation as claimed in claim 3, wherein said I BASE The generator comprises 6 MOS tubes M 32 ～M 37 And a transistor Q 9 Composition, MOS tube M 32 Gate and MOS tube M of (2) 1 Gate electrode of MOS tube M is connected with 33 Gate and MOS tube M of (2) 3 Gate electrode of MOS tube M is connected with 32 Drain electrode of (d) and MOS transistor M 33 Is connected with the source electrode of the MOS tube M 37 Gate and MOS tube M of (2) 33 Is connected with the drain electrode of transistor Q 9 Is connected with the collector electrode of the MOS tube M 37 Source of (d) and transistor Q 9 Is connected with the base electrode of the MOS tube M 36 Source of (d) and transistor Q 9 The emitter of the MOS tube M is connected with the ground 36 Is connected with the grid electrode and the drain electrode and then is connected with the MOS tube M 35 Is connected with the drain electrode of the MOS tube M 35 Gate and MOS tube M of (2) 34 Is connected with the grid electrode of I FOLD The generator is connected with the MOS tube M 34 Is connected with the grid electrode and the drain electrode and then is connected with the MOS tube M 37 Is connected with the drain electrode of the transistor; wherein, MOS tube M 32 Source electrode of (2), MOS tube M 34 Source electrode of (2) and MOS transistor M 35 The sources of (a) are connected with a power supply V DD 。
5. The bandgap reference circuit based on foldback as claimed in claim 4, wherein said V BG The generator comprises 3 curvature compensation modules which are identical in circuit structure and are connected in series, and a broken line compensation module which is connected with the curvature compensation module of the last stage.
6. The band gap reference circuit based on broken line compensation according to claim 5, wherein the curvature compensation module is composed of 9 MOS tubes M 61 ～M 69 And 2 transistors Q 10 、Q 11 Composition; the MOS tube M 61 Gate and MOS tube M of (2) 62 Gate electrode of MOS tube M is connected with 61 Is connected with the grid electrode and the drain electrode and then is connected with the MOS tube M 63 Is connected with the drain electrode of the MOS tube M 63 Gate and MOS tube M of (2) 65 Is connected with the drain electrode of transistor Q 10 Is connected with the collector electrode of the MOS tube M 65 Source electrode of (d) and MOS transistor M 64 Is connected with the drain electrode of the MOS tube M 62 Drain of (d) and transistor Q 10 Is connected with the base of transistor Q 11 Is connected with the base electrode of the MOS tube M 67 Drain electrode of (d) and MOS transistor M 69 Is connected with the drain electrode of transistor Q 11 Is connected with the collector electrode of the MOS tube M 66 Drain electrode of (d) and MOS transistor M 67 Is connected with the source electrode of the MOS tube M 68 Drain of (d) and transistor Q 11 Is connected with the MOS tube M of the next stage after the emitter of the MOS tube M is connected with the emitter of the next stage 63 Source electrode of MOS tube with same position and MOS tube M 68 Gate of (d) and transistor Q 11 Is connected with the collector electrode of the MOS tube M 63 Source, transistor Q 10 Emitter and MOS transistor M of (2) 68 The source electrode of the MOS tube M is connected with the ground 61 Source electrode of (2), MOS tube M 62 Source electrode of (2), MOS tube M 66 Source electrode of (2) and MOS transistor M 69 The sources of (a) are connected with a power supply V DD MOS tube M 64 Gate and MOS transistor M of (2) 66 Is connected with the grid electrode of the MOS tube M 1 Gate electrode of MOS tube M is connected with 65 Gate and MOS transistor M of (2) 67 Is connected with the grid electrode of the MOS tube M 3 Is connected to the gate of (c).
7. The bandgap reference circuit based on broken line compensation according to claim 6, wherein the broken line compensation module is composed of 14 MOS tubes M 88 ～M 101 2 transistors Q 16 、Q 17 And 3 resistors R 11 ～R 13 Composition; MOS tube M 88 Drain electrode of (d) and MOS transistor M 89 Is connected with the source electrode of the MOS tube M 89 MOS tube M in the same first-stage curvature compensation module in the drain electrode and the last-stage curvature compensation module 68 The drains of the MOS tubes with the same positions are connected, and the resistor R 11 One end of (2) is connected with MOS tube M 89 Is connected with the drain electrode of the resistor R 11 And transistor Q 16 Is connected with the emitter of the MOS tube M 93 Drain electrode of (d) and MOS transistor M 94 Is connected with the gate of transistor Q 16 Is connected with the collector electrode of the MOS tube M 93 Source electrode of (2) and MOS transistor M 92 Is connected with the drain electrode of the MOS tube M 90 The grid electrode is connected with the drain electrode and then connected with the MOS tube M 94 Is connected with the drain electrode of the MOS tube M 90 Gate and MOS transistor M of (2) 91 Gate electrode of MOS tube M is connected with 91 Drain of (d) and transistor Q 16 Is connected with the base of transistor Q 17 Is connected with the base electrode of the MOS tube M 99 Drain electrode of (d) and MOS transistor M 100 Is connected with the drain electrode of transistor Q 17 Is connected with the collector electrode of the MOS tube M 98 Drain electrode of (d) and MOS transistor M 99 Is connected with the source electrode of the MOS tube M 99 Drain electrode of (d) and MOS transistor M 101 Is connected with the source electrode of the MOS tube M 95 Source electrode of (d) and MOS transistor M 96 Is connected with the source of transistor Q 16 Is connected with the emitter of the MOS tube M 97 Drain of (d) and transistor Q 17 Emitter connected to resistor R 13 One end of (2) is connected with MOS tube M 97 Is connected with the drain electrode of the resistor R 13 And the other end of (2) is connected with resistor R 12 Is connected to one end of resistor R 12 And transistor Q 17 Is connected with the base electrode of the MOS tube M 94 Source electrode of (2), MOS tube M 95 Drain electrode of (d), MOS transistor M 96 Drain electrode of (d), MOS transistor M 101 Drain electrode of (d) and MOS transistor M 97 The source electrodes of the MOS tube M are all grounded 90 Source electrode of (2), MOS tube M 91 Source electrode of (2), MOS tube M 98 Source electrode of (2) and MOS transistor M 100 The sources of (a) are connected with a power supply V DD MOS tube M 92 Gate and MOS transistor M of (2) 98 Is connected with the grid electrode of the MOS tube M 1 Gate electrode of MOS tube M is connected with 93 Gate and MOS transistor M of (2) 99 Is connected with the grid electrode of the MOS tube M 3 Gate electrode of MOS tube M is connected with 100 Gate and MOS tube M of (2) 31 Gate electrode of MOS tube M is connected with 101 Gate and MOS tube M of (2) 58 Is connected with the grid electrode of the resistor R 13 And resistance R 12 The connected common terminal generates a bandgap reference voltage VBG.
8. The bandgap reference circuit based on foldback as claimed in claim 1, further comprising the step of generating I of Trim current for compensating unavoidable errors in the production process by using PTAT current and CTAT current TRIM A generator.
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