CN214795740U - Band-gap reference voltage source - Google Patents

Band-gap reference voltage source Download PDF

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CN214795740U
CN214795740U CN202121957150.3U CN202121957150U CN214795740U CN 214795740 U CN214795740 U CN 214795740U CN 202121957150 U CN202121957150 U CN 202121957150U CN 214795740 U CN214795740 U CN 214795740U
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resistor
transistor
bipolar
transistors
collector
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谢勇坚
方永松
黄建宝
庄艳萍
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Xiamen Technology Industrialization Group Co ltd
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Xiamen Technology Industrialization Group Co ltd
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Abstract

Band gap reference voltage source belongs to the integrated circuit field, the utility model discloses a it is big to solve traditional band gap reference voltage source and receive the technological deviation influence, and output voltage is not accurate and with the temperature problem that is relevant. The utility model comprises resistors R1-R11, bipolar transistors Q1-Q7, NMOS transistors NM 1-NM 2, PMOS transistors PM 1-PM 2 and a capacitor C1; the base electrodes of the transistors Q3 and Q4 are connected to two ends of the resistor R5 to realize generation of IPTAT current, and the transistors Q5, NM2 and Q6 and the resistors R9 and R8 form a negative feedback loop for inhibiting power supply fluctuation and improving the power supply rejection ratio, so that the voltage of VBG is more stable under the condition of power supply ripple. A zero setting resistor R10 and a miller compensation capacitor C1 are also used in the loop to adjust the phase margin of the loop. The transistors Q1 and Q2, the resistors R1, R2, R3 and R4 and the transistors NM1, PM1 and PM2 form a cascode voltage and current bias part with zero temperature coefficient together, so that the interference of power ripple waves is effectively prevented and the temperature influence is reduced.

Description

Band-gap reference voltage source
Technical Field
The utility model relates to a band gap reference voltage source technique belongs to the integrated circuit field.
Background
Within all chips, a voltage reference that has a small temperature dependence has proven to be essential in many analog circuits. Most process parameters vary with temperature, so if a reference is temperature independent, it is usually process independent. The zero temperature coefficient voltage reference is obtained by adding two quantities having opposite temperature relationships with appropriate weights. The zero temperature coefficient voltage output by the band-gap reference voltage source can be transmitted to a current module with a zero temperature coefficient, a low-dropout linear regulator or a key module (ADC) to provide more accurate reference voltage which is irrelevant to temperature.
FIG. 1 is a conventional bandgap reference voltage source, if two bipolar transistors are operated at unequal current densities, then their base-emitter voltages are different by an amount Δ VBEIs proportional to absolute temperature. Then the voltage difference is applied to a resistor and the current through the resistor is copied using a current mirror to obtain the PTAT current (a current proportional to absolute temperature).
The voltages of the nodes X and Y are pulled to be equal by utilizing the clamping action of the operational amplifier, and finally I is enabled1＝I2. The difference Δ V of the base-emitter voltagesBEIs the voltage across resistor R1. Difference value DeltaV of base-emitter voltageBECan be expressed as:
Figure BDA0003220233470000011
VBE2representing the turn-on voltage, V, of transistor Q2BE1Represents the turn-on voltage of transistor Q1;
VTrepresenting the thermal voltage of the transistor ISRepresenting the saturation current of the transistor, two crystalsThe saturation current of the transistor is the same, and N is the ratio of the parallel connection number of the Q1 transistor and the Q2 transistor.
The expression for IPTAT current proportional to temperature is:
Figure BDA0003220233470000012
this current forms a voltage positively correlated with temperature through the current mirror of the PMOS transistors PM1, PM2, PM3 and the resistor R2. Therefore, the band gap reference voltage VBG with zero temperature coefficient is expressed as:
Figure BDA0003220233470000021
VBE_Q3representing the base-emitter voltage of Q3.
In practical application, the transistor PMOS cannot mirror IPTAT current very accurately due to the deviation of the manufacturing process, and the performance of the PNP transistor manufactured at the present stage is far less stable and excellent than that of the NPN transistor, so that the value of the zero temperature coefficient voltage VBG is larger or smaller, and is not a voltage quantity unrelated to temperature.
SUMMERY OF THE UTILITY MODEL
The utility model discloses the purpose is that it is big in order to solve traditional band gap reference voltage source and receive the technological deviation influence, and output voltage is not accurate and with the temperature problem that is relevant, provides a band gap reference voltage source.
The band gap reference voltage source comprises resistors R1-R11, bipolar transistors Q1-Q7, NMOS transistors NM 1-NM 2, PMOS transistors PM 1-PM 2 and a capacitor C1;
the power supply VDD is simultaneously connected with one end of the resistor R3, the source end of the PMOS transistor PM1, the source end of the PMOS transistor PM2 and the collector and the base of the bipolar collector transistor Q7; the emitter of the bipolar collector transistor Q7 is connected with one end of a resistor R7, and the other end of the resistor R7 is connected with the collector of the bipolar collector transistor Q6;
the power ground GND is simultaneously connected with the emitters of the bipolar transistors Q1, Q3, Q4 and Q5, one end of the resistor R4 and one end of the resistor R11;
the base of the bipolar transistor Q1 is simultaneously connected with one end of the resistor R1 and one end of the resistor R2;
the collector of the bipolar transistor Q1 is simultaneously connected with the other end of the resistor R1 and the base of the bipolar transistor Q2;
the other end of the resistor R2 is simultaneously connected to the other end of the resistor R3, the gate of the NMOS transistor NM1, and the gate of the NMOS transistor NM 2; the source end of NM2 of the NMOS transistor is connected with the collector of a bipolar collector transistor Q5;
the other end of the resistor R4 is connected with the emitter of a bipolar collector transistor Q2;
the collector of the bipolar transistor Q2 is connected with the source end of the NMOS transistor NM 1;
the drain terminal of the NMOS transistor NM1 is simultaneously connected to the gate of the PMOS transistor PM2, the drain terminal and the gate of the PMOS transistor PM 1;
the base of the bipolar transistor Q3 is connected with one end of the resistor R5 and one end of the resistor R6 at the same time;
the collector of the bipolar collector transistor Q3 is simultaneously connected with the other end of the resistor R5 and the base of the bipolar collector transistor Q4;
the collector of the bipolar collector transistor Q4 is simultaneously connected with one end of a resistor R8, one end of a capacitor C1 and the base of the bipolar collector transistor Q5; the other end of the capacitor C1 is connected with one end of the resistor R10;
the other end of the resistor R8 is connected with one end of the resistor R9;
the other end of the resistor R9 is simultaneously connected with the other end of the resistor R6, the other end of the resistor R11 and the emitter of the bipolar transistor Q6 and is used as an output port of the band-gap reference voltage VBG;
the base of the bipolar transistor Q6 is connected to the drain of the PMOS transistor PM2, one end of the resistor R10 and the drain of the NMOS transistor NM2 at the same time, and serves as an output port for the external voltage VBIAS.
Preferably, the resistances of the resistors R6 and R9 are equal and matched on the layout.
Preferably, the resistances of the resistors R5 and R8 are equal and matched on the layout.
Preferably, the number of the bipolar transistors Q3 in parallel is N times that of the bipolar transistors Q4, N is more than 4, and the bipolar transistors Q4 are arranged in the middle of the N bipolar transistors Q3 to form an array structure.
The utility model has the advantages that: the utility model provides a novel band gap reference voltage source abandons traditional band gap reference voltage source's design theory, need use PMOS pipe mirror image IPTAT electric current, and PNP transistor performance wherein is not as the NPN transistor, and the result can cause band gap reference voltage source to be relevant with the temperature, the utility model relates to a novel band gap reference voltage source structure does not need mirror image IPTAT electric current and the better NPN transistor of performance, can be fine obtain with the temperature irrelevant and receive the less reference voltage of process deviation influence.
Drawings
FIG. 1 is a circuit schematic of a conventional bandgap reference voltage source;
fig. 2 is a schematic circuit diagram of the bandgap reference voltage source of the present invention.
Detailed Description
The first embodiment is as follows: the present embodiment will be described with reference to fig. 2, and the bandgap reference voltage source of the present embodiment includes resistors R1 to R11, bipolar transistors Q1 to Q7, NMOS transistors NM1 to NM2, PMOS transistors PM1 to PM2, and a capacitor C1;
the power supply VDD is simultaneously connected with one end of the resistor R3, the source end of the PMOS transistor PM1, the source end of the PMOS transistor PM2 and the collector and the base of the bipolar collector transistor Q7; the emitter of the bipolar collector transistor Q7 is connected with one end of a resistor R7, and the other end of the resistor R7 is connected with the collector of the bipolar collector transistor Q6;
the power ground GND is simultaneously connected with the emitters of the bipolar transistors Q1, Q3, Q4 and Q5, one end of the resistor R4 and one end of the resistor R11;
the base of the bipolar transistor Q1 is simultaneously connected with one end of the resistor R1 and one end of the resistor R2;
the collector of the bipolar transistor Q1 is simultaneously connected with the other end of the resistor R1 and the base of the bipolar transistor Q2;
the other end of the resistor R2 is simultaneously connected to the other end of the resistor R3, the gate of the NMOS transistor NM1, and the gate of the NMOS transistor NM 2; the source end of NM2 of the NMOS transistor is connected with the collector of a bipolar collector transistor Q5;
the other end of the resistor R4 is connected with the emitter of a bipolar collector transistor Q2;
the collector of the bipolar transistor Q2 is connected with the source end of the NMOS transistor NM 1;
the drain terminal of the NMOS transistor NM1 is simultaneously connected to the gate of the PMOS transistor PM2, the drain terminal and the gate of the PMOS transistor PM 1;
the base of the bipolar transistor Q3 is connected with one end of the resistor R5 and one end of the resistor R6 at the same time;
the collector of the bipolar collector transistor Q3 is simultaneously connected with the other end of the resistor R5 and the base of the bipolar collector transistor Q4;
the collector of the bipolar collector transistor Q4 is simultaneously connected with one end of a resistor R8, one end of a capacitor C1 and the base of the bipolar collector transistor Q5; the other end of the capacitor C1 is connected with one end of the resistor R10;
the other end of the resistor R8 is connected with one end of the resistor R9;
the other end of the resistor R9 is simultaneously connected with the other end of the resistor R6, the other end of the resistor R11 and the emitter of the bipolar transistor Q6 and is used as an output port of the band-gap reference voltage VBG;
the base of the bipolar transistor Q6 is connected to the drain of the PMOS transistor PM2, one end of the resistor R10 and the drain of the NMOS transistor NM2 at the same time, and serves as an output port for the external voltage VBIAS. The external voltage VBIAS output port is used for connecting with an external circuit, and the voltage VBIAS is a voltage supplied to the external circuit.
The resistances of the resistors R6 and R9 are equal and matched on the layout.
The resistances of the resistors R5 and R8 are equal and matched on the layout.
The number of the bipolar transistors Q4 in parallel is N times that of the bipolar transistors Q3, N is more than 4, and the bipolar transistors Q3 are arranged in the middle of the N bipolar transistors Q4 to form an array structure.
The working principle is explained below with reference to fig. 2. The utility model discloses in provide a novel band gap reference voltage source, consequently there is not image of the mirror IPTAT electric current and use NPN transistor to be this utility model implementation's key.
In describing the conventional bandgap reference voltage source implementation, a mirror IPTAT current is required, a clamp operational amplifier and a PNP transistor are used, and the deviation of the above structures in the manufacturing engineering will cause the output reference voltage to deviate from the simulation value and be influenced by the temperature. It is not beneficial to guarantee the reference voltage requirements of other high-performance modules.
The novel band-gap reference voltage source provided by fig. 2 solves the problems that the output reference voltage is inaccurate and temperature-dependent due to the structure of the conventional band-gap reference voltage source.
The resistors R6 and R9 have the same resistance and need to be matched on the layout, the resistors R5 and R8 have the same resistance and need to be matched on the layout, the number of the bipolar transistors Q4 connected in parallel is N times that of the bipolar transistors Q3, for example, N is 8, then when the layout is drawn, the transistors Q3 can be placed in the centers of the 8 transistors Q4 individually to form a 3-row 3-column type, and the optimal matching is achieved. The current at the collectors of transistors Q3 and Q4 are exactly equal. Therefore, the expression of the bandgap reference voltage VBG with zero temperature coefficient is:
Figure BDA0003220233470000051
in the formula: vBE_Q4Representing the base-emitter voltage, V, of transistor Q4TRepresenting the thermal voltage of the transistor.
Compared with the traditional band-gap reference voltage source, the IPTAT current and V of the novel band-gap reference voltage sourceBEThe circuit is generated on the same branch, a current mirror link is omitted, the clamping of XY two nodes by the operational amplifier is not needed, the generation of IPTAT current can be realized only by connecting the base electrodes of transistors Q3 and Q4 to two ends of a resistor R5, and the reference voltage deviation caused by imbalance introduced by the input end of the operational amplifier is avoided.
The transistors Q5, NM2, Q6 and the resistors R9, R8 form a negative feedback loop, and the most important role is to suppress power supply fluctuation and improve the power supply rejection ratio, so that the voltage of VBG is more stable in the presence of power supply ripple. A zero setting resistor R10 and a miller compensation capacitor C1 are also used in the loop to adjust the phase margin of the loop.
The transistors Q1 and Q2, the resistors R1, R2, R3 and R4 and the transistors NM1, PM1 and PM2 form a cascode voltage and current bias part with zero temperature coefficient together, so that the interference of power ripple waves can be effectively prevented and the temperature influence can be reduced.
The utility model provides a novel band gap reference voltage source, the voltage of the positive and negative temperature coefficient relevant with the temperature produces in same route, and the power supply rejection ratio that adopts simple reliable negative feedback loop to improve this module has stabilized reference voltage, and this kind of structure also realizes the reference voltage deviation and the temperature drift that highly matched can furthest's reduction manufacturing process brought more easily on the domain.

Claims (4)

1. The band-gap reference voltage source is characterized by comprising resistors R1-R11, bipolar transistors Q1-Q7, NMOS transistors NM 1-NM 2, PMOS transistors PM 1-PM 2 and a capacitor C1;
the power supply VDD is simultaneously connected with one end of the resistor R3, the source end of the PMOS transistor PM1, the source end of the PMOS transistor PM2 and the collector and the base of the bipolar collector transistor Q7; the emitter of the bipolar collector transistor Q7 is connected with one end of a resistor R7, and the other end of the resistor R7 is connected with the collector of the bipolar collector transistor Q6;
the power ground GND is simultaneously connected with the emitters of the bipolar transistors Q1, Q3, Q4 and Q5, one end of the resistor R4 and one end of the resistor R11;
the base of the bipolar transistor Q1 is simultaneously connected with one end of the resistor R1 and one end of the resistor R2;
the collector of the bipolar transistor Q1 is simultaneously connected with the other end of the resistor R1 and the base of the bipolar transistor Q2;
the other end of the resistor R2 is simultaneously connected to the other end of the resistor R3, the gate of the NMOS transistor NM1, and the gate of the NMOS transistor NM 2; the source end of NM2 of the NMOS transistor is connected with the collector of a bipolar collector transistor Q5;
the other end of the resistor R4 is connected with the emitter of a bipolar collector transistor Q2;
the collector of the bipolar transistor Q2 is connected with the source end of the NMOS transistor NM 1;
the drain terminal of the NMOS transistor NM1 is simultaneously connected to the gate of the PMOS transistor PM2, the drain terminal and the gate of the PMOS transistor PM 1;
the base of the bipolar transistor Q3 is connected with one end of the resistor R5 and one end of the resistor R6 at the same time;
the collector of the bipolar collector transistor Q3 is simultaneously connected with the other end of the resistor R5 and the base of the bipolar collector transistor Q4;
the collector of the bipolar collector transistor Q4 is simultaneously connected with one end of a resistor R8, one end of a capacitor C1 and the base of the bipolar collector transistor Q5; the other end of the capacitor C1 is connected with one end of the resistor R10;
the other end of the resistor R8 is connected with one end of the resistor R9;
the other end of the resistor R9 is simultaneously connected with the other end of the resistor R6, the other end of the resistor R11 and the emitter of the bipolar transistor Q6 and is used as an output port of the band-gap reference voltage VBG;
the base of the bipolar transistor Q6 is connected to the drain of the PMOS transistor PM2, one end of the resistor R10 and the drain of the NMOS transistor NM2 at the same time, and serves as an output port for the external voltage VBIAS.
2. The bandgap reference voltage source according to claim 1, wherein the resistances of the resistors R6 and R9 are equal and matched on layout.
3. The bandgap reference voltage source according to claim 1, wherein the resistances of the resistors R5 and R8 are equal and matched on layout.
4. The bandgap reference voltage source according to claim 1, wherein the number of bipolar transistors Q4 in parallel is N times that of bipolar transistors Q3, N >4, and bipolar transistors Q3 are disposed in the middle of N bipolar transistors Q4 to form an array structure.
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