CN217443795U - Band-gap reference circuit with high-temperature compensation function - Google Patents

Abstract

The utility model relates to a band gap reference circuit with high temperature compensation function belongs to the semiconductor integrated circuit field. A band-gap reference circuit with high-temperature compensation function comprises a band-gap reference generating circuit and a high-temperature compensation circuit; the band-gap reference generating circuit is connected with the high-temperature compensation circuit; the band-gap reference generating circuit is used for generating a band-gap reference voltage; the high-temperature compensation circuit is used for compensating the band-gap reference voltage at high temperature. The utility model provides a parasitic diode that NPN triode processing procedure caused reverse saturation leakage current increase under the high temperature, the inaccurate problem of band gap reference voltage who arouses realizes the invariant of band gap reference voltage under the high temperature.

Description

Band-gap reference circuit with high-temperature compensation function

Technical Field

The utility model relates to a semiconductor integrated circuit field especially relates to a band gap reference circuit with high temperature compensation function.

Background

The band-gap reference circuit is used as a reference module in an integrated circuit and is required to have higher stability and insensitivity to temperature, and in the traditional P substrate N well process, the collector current flowing through an NPN used in the band-gap reference circuit is not proportional due to the increase of reverse saturated leakage current of a parasitic PN junction at high temperature, so that the band-gap reference voltage is inaccurate.

For some environments requiring high temperature applications, the following is generally done in the bandgap reference generation circuit:

one is to use PNP as the output of the band-gap reference unit, and the method needs a larger output resistor, so that a plurality of groups of current mirrors need to be superposed and the requirement can not be met when the power supply voltage is lower; or an operational amplifier may be used to increase the impedance, but this increases the complexity of the circuit.

The second is to use NPN as output of the band-gap reference unit, and then superimpose NPN according to the proportion of leakage current to ensure that collector current of the band-gap reference NPN transistor keeps a certain proportion.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a band gap reference circuit with high temperature compensation function to solve parasitic diode that NPN triode processing procedure caused among the prior art reverse saturation leakage current increase under the high temperature, the inaccurate problem of band gap reference voltage who arouses.

In order to achieve the above object, the utility model provides a following scheme:

a band-gap reference circuit with high-temperature compensation function comprises a band-gap reference generating circuit and a high-temperature compensation circuit; the band gap reference generating circuit is connected with the high-temperature compensation circuit; the band-gap reference generating circuit is used for generating a band-gap reference voltage; the high-temperature compensation circuit is used for compensating the band-gap reference voltage at high temperature;

the high-temperature compensation circuit comprises a third NPN triode, a fourth NPN triode, a second current mirror unit and a third current mirror unit;

a collector of the third NPN triode and a collector of the fourth NPN triode are connected with the band-gap reference generating circuit; the base electrode of the third NPN triode is connected with the collector electrode of the third NPN triode; the base electrode of the fourth NPN triode is connected with the collector electrode of the fourth NPN triode; an emitter of the third NPN triode and an emitter of the fourth NPN triode are both connected with one end of the second current mirror unit; one end of the second current mirror unit is connected with one end of the third current mirror unit; the other end of the third current mirror unit is connected with the band-gap reference generating circuit.

Optionally, the bandgap reference generating circuit includes a first current mirror unit, a first NPN transistor, a second NPN transistor, a first resistor, a second resistor, a third resistor, and a first NMOS transistor;

the first current mirror unit is respectively connected with a collector of the first NPN triode, a collector of the second NPN triode, a collector of the third NPN triode and a collector of the fourth NPN triode, and the first current mirror unit is also connected with a grid electrode of the first NMOS tube; the collector of the second NPN triode is also connected with the other end of the third current mirror unit; the base electrode of the first NPN triode, the base electrode of the second NPN triode and the source electrode of the first NMOS tube are sequentially connected, and the source electrode of the first NMOS tube is also connected with one end of the third resistor; the other end of the third resistor is grounded; an emitter of the first NPN triode is connected with one end of the first resistor; the other end of the first resistor is connected with one end of the second resistor and an emitting electrode of the second NPN triode; the other end of the second resistor is grounded; and the drain electrode of the first NMOS tube is connected with a direct-current voltage source.

Optionally, the first current mirror unit is configured to mirror an input current to the second NPN transistor, the third NPN transistor, and the fourth NPN transistor in proportion; the input current is the current obtained by dividing the difference between the voltage between the base electrode and the emitter of the first NPN triode and the voltage between the base electrode and the emitter of the second NPN triode by the resistance value of the first resistor.

Optionally, the second current mirror unit is configured to subtract a collector current of the third NPN transistor from a collector current of the fourth NPN transistor.

Optionally, the third current mirror unit is configured to mirror an output current of the second current mirror unit to a collector of the second NPN transistor in proportion; the output current is a difference value between a collector current of the third NPN triode and a collector current of the fourth NPN triode.

Optionally, the first NMOS transistor is a common-drain amplifier.

Optionally, the first current mirror unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor;

the source electrode of the first PMOS tube, the source electrode of the second PMOS tube, the source electrode of the third PMOS tube and the source electrode of the fourth PMOS tube are all connected with the direct current source; the grid electrode of the first PMOS tube is respectively connected with the grid electrode of the second PMOS tube, the grid electrode of the third PMOS tube and the grid electrode of the fourth PMOS tube; the grid electrode of the first PMOS tube is also connected with the drain electrode of the first PMOS tube; the drain electrode of the first PMOS tube is connected with the collector electrode of the first NPN triode; the drain electrode of the second PMOS tube is connected with the collector electrode of the second NPN triode; the drain electrode of the third PMOS tube is connected with the collector electrode of the third NPN triode; and the drain electrode of the fourth PMOS tube is connected with the collector electrode of the fourth NPN triode.

Optionally, the second current mirror unit includes a second NMOS transistor and a third NMOS transistor;

the drain electrode of the second NMOS tube is connected with the emitter electrode of the third NPN triode; the grid electrode of the second NMOS tube is connected with the grid electrode of the third NMOS tube; the grid electrode of the second NMOS tube is also connected with the drain electrode of the second NMOS tube; the drain electrode of the third NMOS tube is connected with the emitter electrode of the fourth NPN triode; and the source electrode of the second NMOS tube and the source electrode of the third NMOS tube are both grounded.

Optionally, the third current mirror unit includes a fourth NMOS transistor and a fifth NMOS transistor;

the drain electrode of the fourth NMOS tube is connected with the drain electrode of the third NMOS tube; the grid electrode of the fourth NMOS tube is connected with the grid electrode of the fifth NMOS tube; the grid electrode of the fourth NMOS tube is also connected with the drain electrode of the fourth NMOS tube; the drain electrode of the fifth NMOS tube is connected with the collector electrode of the second NPN triode; and the source electrode of the fourth NMOS tube and the source electrode of the fifth NMOS tube are both grounded.

According to the utility model provides a concrete embodiment, the utility model discloses a following technological effect:

the utility model provides a pair of band gap reference circuit with high temperature compensation function causes parasitic diode reverse saturation to leak current increase under the high temperature when NPN triode processing procedure to when leading to band gap reference voltage inaccurate, compensate band gap reference voltage through high temperature compensation circuit, improved band gap reference voltage's stability, realized the invariant of band gap reference voltage under the high temperature.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive labor.

Fig. 1 is a schematic diagram of a bandgap reference circuit with high temperature compensation function provided by the present invention;

fig. 2is a schematic circuit diagram of a preferred embodiment of a bandgap reference circuit with high temperature compensation function according to the present invention;

fig. 3 is a schematic cross-sectional view of a parasitic diode causing leakage at high temperature according to the present invention;

fig. 4 is a schematic diagram of an equivalent circuit of a parasitic diode that causes leakage at high temperature according to the present invention;

FIG. 5 is a band gap reference temperature drift curve without the addition of a high temperature compensation circuit;

fig. 6 is a bandgap reference temperature drift curve incorporating a high temperature compensation circuit.

Description of the symbols: 101-a first current mirror unit; 110-a second current mirror unit; 111-a third current mirror unit; 102-a first NPN transistor; 103-a second NPN transistor; 104-a third NPN transistor; 105-a fourth NPN transistor; 106-first NMOS transistor; 107-first resistance; 108-a second resistance; 109-a third resistance; 301-a first PMOS transistor; 302-a second PMOS transistor; 303-a third PMOS transistor; 304-fourth PMOS transistor; 313-a second NMOS tube; 314-third NMOS transistor; 315-fourth NMOS transistor; 316-fifth NMOS transistor.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

The utility model aims at providing a band gap reference circuit with high temperature compensation function to solve parasitic diode that NPN triode processing procedure caused among the prior art reverse saturation leakage current increase under the high temperature, the inaccurate problem of band gap reference voltage who arouses.

In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, the present invention is described in detail with reference to the accompanying drawings and the following detailed description.

Fig. 1 is a schematic diagram of a bandgap reference circuit with high temperature compensation function according to the present invention, as shown in fig. 1, a bandgap reference circuit with high temperature compensation function includes a bandgap reference generating circuit and a high temperature compensation circuit; the band-gap reference generating circuit is connected with the high-temperature compensation circuit; the band-gap reference generating circuit is used for generating a band-gap reference voltage; the high-temperature compensation circuit is used for compensating the band-gap reference voltage at high temperature.

Further, the bandgap reference generating circuit includes a first current mirror unit 101, a first NPN transistor 102, a second NPN transistor 103, a first resistor 107, a second resistor 108, a third resistor 109, and a first NMOS transistor 106. The first current mirror unit 101 is configured to mirror an input current to the second NPN transistor 103, the third NPN transistor 104, and the fourth NPN transistor 105 in proportion; the input current is the current obtained by dividing the difference between the voltage between the base and the emitter of the first NPN transistor 102 and the voltage between the base and the emitter of the second NPN transistor 103 by the resistance of the first resistor 107.

The high temperature compensation circuit includes a third NPN transistor 104, a fourth NPN transistor 105, a second current mirror unit 110, and a third current mirror unit 111. Wherein the second current mirror unit 110 is configured to subtract the collector current of the third NPN transistor 104 from the collector current of the fourth NPN transistor 105. The third current mirror unit 111 is configured to mirror the output current of the second current mirror unit 110 to the collector of the second NPN transistor 103 in proportion; the output current is the difference between the collector current of the third NPN transistor 104 and the collector current of the fourth NPN transistor 105.

The first current mirror unit 101 is respectively connected to a collector of the first NPN transistor 102, a collector of the second NPN transistor 103, a collector of the third NPN transistor 104, and a collector of the fourth NPN transistor 105, and the first current mirror unit 101 is further connected to a gate of the first NMOS transistor 106; the collector of the second NPN triode 103 is further connected to the other end of the third current mirror unit 111; the base of the first NPN transistor 102, the base of the second NPN transistor 103, and the source of the first NMOS transistor 106 are sequentially connected, and the source of the first NMOS transistor 106 is further connected to one end of the third resistor 109; the other end of the third resistor 109 is grounded; an emitter of the first NPN triode 102 is connected to one end of the first resistor 107; the other end of the first resistor 107 is connected to one end of the second resistor 108 and the emitter of the second NPN transistor 103; the other end of the second resistor 108 is grounded; the drain of the first NMOS transistor 106 is connected to a dc voltage source.

The base of the third NPN triode 104 is connected to the collector of the third NPN triode 104; the base electrode of the fourth NPN triode 105 is connected to the collector electrode of the fourth NPN triode 105; an emitter of the third NPN transistor 104 and an emitter of the fourth NPN transistor 105 are both connected to one end of the second current mirror unit 110; one end of the second current mirror unit 110 is connected to one end of the third current mirror unit 111.

In practical application, the ratio of the first NPN transistor 102, the second NPN transistor 103, the third NPN transistor 104, and the fourth NPN transistor 105 is 2:1:2: 1.

As an alternative embodiment, the first NMOS transistor 106 is a common-drain amplifier.

Fig. 2is a schematic circuit diagram of a preferred embodiment of a bandgap reference circuit with a high temperature compensation function according to the present invention, as shown in fig. 2, the first current mirror unit 101 includes a first PMOS transistor 301, a second PMOS transistor 302, a third PMOS transistor 303, and a fourth PMOS transistor 304. In practical application, the ratio of the first PMOS transistor 301 to the second PMOS transistor 302 to the third PMOS transistor 303 to the fourth PMOS transistor 304 is 1:4:1: 1.

The source electrode of the first PMOS transistor 301, the source electrode of the second PMOS transistor 302, the source electrode of the third PMOS transistor 303, and the source electrode of the fourth PMOS transistor 304 are all connected to the dc current source; the gate of the first PMOS transistor 301 is connected to the gates of the second PMOS transistor 302, the third PMOS transistor 303 and the fourth PMOS transistor 304, respectively, so as to mirror the current in the first PMOS transistor 301. The gate of the first PMOS transistor 301 is further connected to the drain of the first PMOS transistor 301; the drain of the first PMOS transistor 301 is connected to the collector of the first NPN transistor 102; the drain electrode of the second PMOS transistor 302 is connected with the collector electrode of the second NPN triode 103; the drain electrode of the third PMOS transistor 303 is connected to the collector electrode of the third NPN triode 104; the drain of the fourth PMOS transistor 304 is connected to the collector of the fourth NPN transistor 105.

The second current mirror unit 110 includes a second NMOS transistor 313 and a third NMOS transistor 314. In practical applications, the ratio of the second NMOS transistor 313 to the third NMOS transistor 314 is 1: 1.

The drain of the second NMOS transistor 313 is connected to the emitter of the third NPN triode 104; the grid electrode of the second NMOS tube 313 is connected with the grid electrode of the third NMOS tube 314; the grid electrode of the second NMOS tube 313 is also connected with the drain electrode of the second NMOS tube 313; the drain of the third NMOS tube 314 is connected to the emitter of the fourth NPN transistor 105; the source of the second NMOS transistor 313 and the source of the third NMOS transistor 314 are both grounded.

The third current mirror unit 111 includes a fourth NMOS transistor 315 and a fifth NMOS transistor 316. In practical applications, the ratio of the fourth NMOS transistor 315 to the fifth NMOS transistor 316 is 1: 7.

The drain electrode of the fourth NMOS tube 315 is connected to the drain electrode of the third NMOS tube 314; the grid electrode of the fourth NMOS tube 315 is connected with the grid electrode of the fifth NMOS tube 316; the grid electrode of the fourth NMOS tube 315 is also connected with the drain electrode of the fourth NMOS tube 315; the drain of the fifth NMOS transistor 316 is connected to the collector of the second NPN transistor 103; the source of the fourth NMOS transistor 315 and the source of the fifth NMOS transistor 316 are both grounded.

The base voltages of the first NPN triode 102 and the second NPN triode 103 are VBG voltages. The working principle analysis is as follows:

at low temperature or normal temperature, since the leakage current of the NPN transistor is small and negligible with respect to the reference current in the circuit, the reverse saturation leakage current of the parasitic diode flowing through Q1, Q2, Q3, and Q4 is negligible compared to the mirror image current of the current mirror, so the currents flowing through Q3 and Q4 are equal, the current in the fourth NMOS 315 of the third current mirror unit 111 is 0, the Icomp current is 0, the collector currents flowing through Q1 and Q2 are 4 times, and the emitter currents flowing through Q1 and Q2 are 4 times. Q1, Q2, Q3 and Q4 in fig. 2 represent the first NPN transistor, the second NPN transistor, the third NPN transistor and the fourth NPN transistor, respectively, and R1, R2 and R3 represent the first resistance, the second resistance and the third resistance, respectively.

The VBG voltage at this time is calculated as follows:

wherein Vt is thermal voltage of about 26mV, Vbe _ Q2 is the voltage between the base and emitter of Q2, and A1 and A2 are respectivelyEmitter area of Q1, Q2, 5 is the total current multiple through resistor R2, I _Q1c 、I _Q2c For the current flowing through the collectors of Q1 and Q2, an ideal temperature characteristic curve can be obtained by adjusting the ratio of R1 to R2.

In the conventional P-substrate N-well process, an NPN structure is shown in fig. 3, a parasitic diode is present between a collector and a substrate, an equivalent circuit diagram is shown in fig. 4, and under a normal working condition, the parasitic diode is in a reverse bias state, and a reverse saturation leakage current is negligible compared with a collector current at a low temperature, but when the temperature is increased, the current increases exponentially, and under a high temperature state, the current causes a collector current actually flowing through an NPN transistor to be reduced, and the reverse saturation leakage current of the parasitic diode is in direct proportion to the area of the NPN transistor.

If the high temperature condition is small and the reverse saturation leakage current of the parasitic diode is large when Icomp compensation current is not added, the influence of the leakage current cannot be ignored, and the current flowing through the emitter of Q1 is set as I _Q1e Assuming that the leakage current of the parasitic diode per unit area Is, the area of Q1 Is 2 times that of Q2, so that the leakage current of Q1 Is 2Is, and the current in the first PMOS transistor 301 Is I1, the following formula Is given:

I1＝I _Q1e +2Is (2)

after the current is mirrored by the first current mirror unit 101, the current flowing through the second PMOS transistor 302 is I2, and the following formula is given:

I2＝4I _Q1e +8Is (3)

the characteristics of the (2) and (3) and the NPN triode show that:

I _Q1c ＝I _Q1e (4)

I _Q2c ＝4I _Q1c +7Is (5)

the expression of VBG at this time is as follows:

substituting the two formulas (4) and (5) into the formula (6) can obtain:

comparing the formula (7) with the formula (1), it can be seen that when no compensation current Is added, VBG increases at high temperature, as shown in fig. 5, the VBG voltage changes with temperature when no high-temperature compensation circuit Is added, and as the temperature increases, the VBG voltage rises at high temperature, and the magnitude of the rising Is related to the Is current, and as the Is changes exponentially with the temperature, the VBG also increases exponentially at high temperature.

Now consider adding a high temperature compensation circuit, the current flowing through the emitter of Q3 under high temperature conditions is:

I _Q3e ＝I _Q1e (8)

the current flowing through the emitter of Q4 at high temperature was:

I _Q4e ＝I _Q1e +Is (9)

from (8) and (9), it can be known that the Idif current Is exactly the reverse saturation leakage current Is of one parasitic diode under the high temperature condition, Icomp Is equal to 7Is after being mirrored by the third current mirror unit 111, and the current Is introduced into the drain of the second PMOS transistor 302, and then the current actually flowing into the collector of Q2 Is as follows:

I _Q2c ＝4I _Q1c (10)

therefore, the expression of VBG will be continuously maintained as formula (1), which is no longer related to the reverse saturation leakage current of the parasitic diode, and VBG can be kept constant, as shown in fig. 6, and the VBG with temperature variation curve after adding high temperature compensation can also be kept stable in a high temperature state.

The utility model provides a pair of band gap reference circuit with high temperature compensation function has solved parasitic diode that NPN triode processing procedure caused and has leaked the increase of current in reverse saturation under the high temperature, and the inaccurate problem of band gap reference voltage who arouses realizes the invariant of band gap reference voltage under the high temperature.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

The principle and the implementation of the present invention are explained herein by using specific examples, and the above description of the embodiments is only used to help understand the method and the core idea of the present invention; meanwhile, for the general technical personnel in the field, according to the idea of the present invention, there are changes in the concrete implementation and the application scope. In summary, the content of the present specification should not be construed as a limitation of the present invention.

Claims (9)

1. A band-gap reference circuit with high-temperature compensation function is characterized by comprising a band-gap reference generating circuit and a high-temperature compensation circuit; the band-gap reference generating circuit is connected with the high-temperature compensation circuit; the band-gap reference generating circuit is used for generating a band-gap reference voltage; the high-temperature compensation circuit is used for compensating the band-gap reference voltage at high temperature;

the high-temperature compensation circuit comprises a third NPN triode, a fourth NPN triode, a second current mirror unit and a third current mirror unit;

a collector of the third NPN triode and a collector of the fourth NPN triode are connected with the band-gap reference generating circuit; the base electrode of the third NPN triode is connected with the collector electrode of the third NPN triode; the base electrode of the fourth NPN triode is connected with the collector electrode of the fourth NPN triode; an emitter of the third NPN triode and an emitter of the fourth NPN triode are both connected with one end of the second current mirror unit; one end of the second current mirror unit is connected with one end of the third current mirror unit; the other end of the third current mirror unit is connected with the band-gap reference generating circuit.

2. The bandgap reference circuit with high temperature compensation function according to claim 1, wherein the bandgap reference generating circuit comprises a first current mirror unit, a first NPN transistor, a second NPN transistor, a first resistor, a second resistor, a third resistor and a first NMOS transistor;

the first current mirror unit is respectively connected with a collector of the first NPN triode, a collector of the second NPN triode, a collector of the third NPN triode and a collector of the fourth NPN triode, and the first current mirror unit is also connected with a grid electrode of the first NMOS tube; the collector of the second NPN triode is also connected with the other end of the third current mirror unit; the base electrode of the first NPN triode, the base electrode of the second NPN triode and the source electrode of the first NMOS tube are sequentially connected, and the source electrode of the first NMOS tube is also connected with one end of the third resistor; the other end of the third resistor is grounded; an emitter of the first NPN triode is connected with one end of the first resistor; the other end of the first resistor is connected with one end of the second resistor and an emitting electrode of the second NPN triode; the other end of the second resistor is grounded; and the drain electrode of the first NMOS tube is connected with a direct-current voltage source.

3. The bandgap reference circuit with high temperature compensation function according to claim 2, wherein the first current mirror unit is configured to mirror an input current to the second NPN transistor, the third NPN transistor, and the fourth NPN transistor in proportion; the input current is the current obtained by dividing the difference between the voltage between the base electrode and the emitter of the first NPN triode and the voltage between the base electrode and the emitter of the second NPN triode by the resistance value of the first resistor.

4. The bandgap reference circuit with high temperature compensation function according to claim 2, wherein the second current mirror unit is configured to subtract a collector current of the third NPN transistor from a collector current of the fourth NPN transistor.

5. The bandgap reference circuit with the function of high temperature compensation as claimed in claim 4, wherein the third current mirror unit is configured to mirror the output current of the second current mirror unit to the collector of the second NPN transistor in proportion; the output current is a difference value between a collector current of the third NPN triode and a collector current of the fourth NPN triode.

6. The bandgap reference circuit with high temperature compensation function as claimed in claim 2, wherein the first NMOS transistor is a common drain amplifier.

7. The bandgap reference circuit with high temperature compensation function as claimed in claim 2, wherein the first current mirror unit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor;

the source electrode of the first PMOS tube, the source electrode of the second PMOS tube, the source electrode of the third PMOS tube and the source electrode of the fourth PMOS tube are all connected with the direct-current voltage source; the grid electrode of the first PMOS tube is respectively connected with the grid electrode of the second PMOS tube, the grid electrode of the third PMOS tube and the grid electrode of the fourth PMOS tube; the grid electrode of the first PMOS tube is also connected with the drain electrode of the first PMOS tube; the drain electrode of the first PMOS tube is connected with the collector electrode of the first NPN triode; the drain electrode of the second PMOS tube is connected with the collector electrode of the second NPN triode; the drain electrode of the third PMOS tube is connected with the collector electrode of the third NPN triode; and the drain electrode of the fourth PMOS tube is connected with the collector electrode of the fourth NPN triode.

8. The bandgap reference circuit with high temperature compensation function as claimed in claim 7, wherein the second current mirror unit comprises a second NMOS transistor and a third NMOS transistor;

the drain electrode of the second NMOS tube is connected with the emitter electrode of the third NPN triode; the grid electrode of the second NMOS tube is connected with the grid electrode of the third NMOS tube; the grid electrode of the second NMOS tube is also connected with the drain electrode of the second NMOS tube; the drain electrode of the third NMOS tube is connected with the emitter electrode of the fourth NPN triode; and the source electrode of the second NMOS tube and the source electrode of the third NMOS tube are both grounded.

9. The bandgap reference circuit with high temperature compensation function as claimed in claim 8, wherein the third current mirror unit comprises a fourth NMOS transistor and a fifth NMOS transistor;

the drain electrode of the fourth NMOS tube is connected with the drain electrode of the third NMOS tube; the grid electrode of the fourth NMOS tube is connected with the grid electrode of the fifth NMOS tube; the grid electrode of the fourth NMOS tube is also connected with the drain electrode of the fourth NMOS tube; the drain electrode of the fifth NMOS tube is connected with the collector electrode of the second NPN triode; and the source electrode of the fourth NMOS tube and the source electrode of the fifth NMOS tube are both grounded.

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