CN110888485B - Self-biased band gap reference circuit - Google Patents
Self-biased band gap reference circuit Download PDFInfo
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- CN110888485B CN110888485B CN201910954319.0A CN201910954319A CN110888485B CN 110888485 B CN110888485 B CN 110888485B CN 201910954319 A CN201910954319 A CN 201910954319A CN 110888485 B CN110888485 B CN 110888485B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
Abstract
The invention provides a self-biased bandgap reference circuit, which comprises: the drain of the transistor M1 is connected with the drain of M3, and is connected with the gates of M1 and M2; the drain of the M2 is connected with the drain of the M4, and is connected with the gates of the M5, the M6, the M8 and the M11; m3, M4 and M7 are connected with the gates of the transistor groups M12, M13 and M14 which are connected in series; the base electrode of the first transistor Q1 is connected with the collector electrode and grounded, and the emitter electrode of the first transistor Q1 is connected with the source electrode of M1; the base electrode and the collector electrode of the second transistor Q2 are connected and grounded, the emitter electrode of the second transistor Q2 is connected with one end of the R1, the other end of the R1 is connected with the source electrode of the M2, and a current value which is in direct proportion to the temperature coefficient is generated; the base of the third transistor Q3 is connected to the collector and grounded, the emitter of the third transistor Q3 is connected to one end of R2, and the other end of R2 is connected to the drain of M7, generating a voltage value inversely proportional to the temperature coefficient. The invention can obtain a band-gap reference voltage which is insensitive to power supply voltage, has low power consumption and low temperature coefficient and is quick in response.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a self-biased band-gap reference circuit.
Background
The band-gap reference source is widely applied to various integrated circuits such as analog and digital-analog mixed signals, power management and the like, and aims to establish direct current voltage or current independent of power supply voltage, temperature and process. The design quality of the bandgap reference source directly affects the performance of the chip circuit and even the whole system, and circuits such as a data converter, a comparator, an error amplifier and the like all need the bandgap reference source to provide accurate and stable reference voltage and reference current. Therefore, the design of the reference source occupies an important position in the whole circuit system, and the improvement of the performance of the bandgap reference source is helpful for improving the stability and reliability of the operation of the circuit system.
Due to the rapid development of the system on chip and the continuous improvement of the integration level, the system has higher and higher requirements on stability, and thus higher requirements on the performance of the reference source are also provided. In the traditional band-gap reference circuit, the design of a biasing circuit is complex, and the static power consumption of a circuit system is additionally increased. Therefore, an improved self-biased bandgap reference circuit is developed, which has a relatively simple structure, a smaller layout area, a higher integration level and low power consumption, and can realize that the bandgap reference voltage is insensitive to the changes of the power supply voltage, the process parameters and the temperature.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a self-biased bandgap reference source which is insensitive to power supply voltage, has low power consumption and low temperature coefficient and has quick response.
In order to achieve the above purposes, the invention adopts the technical scheme that: a self-biased bandgap reference circuit comprising: a band-gap reference circuit and a starting circuit;
the bandgap reference circuit includes: transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13 and M14, a first transistor Q1, a second transistor Q2, a third transistor Q3, a first resistor R1 and a second resistor R2, a first current mirror composed of transistors M1 and M2, and a second cascode current mirror composed of transistors M3, M4, M5, M6, M7 and M8;
the drain of the transistor M1 is connected with the drain of the transistor M3 and the gates of the transistors M1 and M2, and the gate bias voltage is supplied to the transistors M1 and M2; the drain electrode of the transistor M2 is connected with the drain electrode of the transistor M4 and the gate electrodes of the transistors M5, M6, M8 and M11, and a gate bias voltage is provided for the transistors M5, M6, M8 and M11; the sources of the transistors M5, M6, M8 and M11 are connected in parallel with a power supply; the drain of the transistor M5 is connected to the source of the transistor M3; the drain of the transistor M6 is connected to the source of the transistor M4; the drain of the transistor M8 is connected to the source of the transistor M7; the drain electrode of the transistor M11 is connected with the grid electrode and the drain electrode of the transistor M9; the gate of the transistor M9 is connected with the gate of the mirror transistor M10 to provide bias current for the branch in which the transistor M9 is positioned; the drain of the transistor M10 is connected to the drain of the transistor M12; the source of the transistor M9 and the source of the transistor M10 are connected and grounded; the gates of the transistors M3, M4 and M7 are connected with the gates of the transistor groups M12, M13 and M14 which are connected in series, and gate bias voltages are provided for the transistors M3, M4 and M7; the base electrode of the first transistor Q1 is connected with the collector electrode and grounded, and the emitter electrode of the first transistor Q1 is connected with the source electrode of the transistor M1; the base electrode and the collector electrode of the second transistor Q2 are connected and grounded, the emitter electrode of the second transistor Q2 is connected with one end of a first resistor R1, the other end of the first resistor R1 is connected with the source electrode of a transistor M2, and a current value which is in direct proportion to a temperature coefficient is generated; the base and the collector of the third transistor Q3 are connected and grounded, the emitter of the third transistor Q3 is connected with one end of a second resistor R2, the other end of the second resistor R2 is connected with the drain of a transistor M7, and a voltage value inversely proportional to the temperature coefficient is generated.
Further, the start-up circuit includes transistors M15, M16, M17, M18, M19, M20, and a third resistor R3; the transistors M15 and M16 are mirror images, the drain of the transistor M15 and the gates of the transistors M15 and M16 are connected to one end of a third resistor R3; the other end of the third resistor R3 is connected with the drain of the transistor M17; the sources of the transistors M17, M18, M19 and M20 are respectively connected with a power supply; the gate of transistor M17 is controlled by enable signal ENB; the drains of the transistors M18 and M19 are connected with the gates of M19 and M20; the gate of transistor M18 is connected to the gate of M5, using the same bias voltage VB(ii) a The drain of transistor M20 is connected to the drain of M1.
Further, the M1, M2, M9 and M10 are NMOS transistors.
Further, the M3, M4, M5, M6, M7, M8, M11, M12, M13 and M14 are PMOS transistors.
Further, the first transistor Q1, the second transistor Q2, and the third transistor Q3 are bipolar transistors.
Further, the M17, M18, M19 and M20 are PMOS transistors.
Further, the M15 and M16 are NMOS transistors.
The self-biased bandgap reference circuit has the advantages that the self-biased cascode current mirror structure is adopted, so that more accurate mirror current is obtained, and the power supply rejection ratio of the bandgap reference circuit is improved. The self-bias implementation mode effectively reduces the power consumption and the area of the band-gap reference circuit, thereby obtaining the band-gap reference voltage which is insensitive to the power supply voltage, has low power consumption and low temperature coefficient and is quick in response.
Drawings
Fig. 1 is a schematic diagram of a self-biased bandgap reference circuit according to the present invention.
Detailed Description
In order to make the technical problems solved, the technical solutions adopted, and the technical effects achieved by the present invention clearer, the technical solutions of the embodiments of the present invention will be further described in detail with reference to the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic diagram of a self-biased bandgap reference circuit according to the present invention. The invention provides a self-biased bandgap reference circuit, comprising: a bandgap reference circuit and a start-up circuit.
The band gap reference circuit comprises transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13 and M14, a first transistor Q1, a second transistor Q2, a third transistor Q3, a first resistor R1 and a second resistor R2, a first current mirror formed by transistors M1 and M2, and a second cascode current mirror formed by transistors M3, M4, M5, M6, M7 and M8.
The drain of the transistor M1 is connected with the drain of the transistor M3 and the gates of the transistors M1 and M2, and the gate bias voltage is supplied to the transistors M1 and M2; the drain electrode of the transistor M2 is connected with the drain electrode of the transistor M4 and the gate electrodes of the transistors M5, M6, M8 and M11, and a gate bias voltage is provided for the transistors M5, M6, M8 and M11; the sources of the transistors M5, M6, M8 and M11 are connected in parallel with a power supply; the drain of the transistor M5 is connected to the source of the transistor M3; the drain of the transistor M6 is connected to the source of the transistor M4; the drain of the transistor M8 is connected to the source of the transistor M7; the drain electrode of the transistor M11 is connected with the grid electrode and the drain electrode of the transistor M9; the gate of the transistor M9 is connected with the gate of the mirror transistor M10 to provide bias current for the branch in which the transistor M9 is positioned; the drain of the transistor M10 is connected to the drain of the transistor M12; the source of the transistor M9 and the source of the transistor M10 are connected and grounded; the gates of the transistors M3, M4 and M7 are connected with the gates of the transistor groups M12, M13 and M14 which are connected in series, and gate bias voltages are provided for the transistors M3, M4 and M7; the base electrode of the first transistor Q1 is connected with the collector electrode and grounded, and the emitter electrode of the first transistor Q1 is connected with the source electrode of the transistor M1; the base electrode and the collector electrode of the second transistor Q2 are connected and grounded, the emitter electrode of the second transistor Q2 is connected with one end of a first resistor R1, the other end of the first resistor R1 is connected with the source electrode of a transistor M2, and a current value which is in direct proportion to a temperature coefficient is generated; the base and the collector of the third transistor Q3 are connected and grounded, the emitter of the third transistor Q3 is connected with one end of a second resistor R2, the other end of the second resistor R2 is connected with the drain of a transistor M7, and a voltage value inversely proportional to the temperature coefficient is generated.
The basic operation principle of the bandgap reference circuit is to use the voltage difference Δ V between the base-emitter of the first transistor Q1 and the base-emitter of the second transistor Q2BEGenerating a current value proportional to the temperature coefficient, plus the base-emitter voltage V of the third transistor Q3 having a negative temperature coefficientBE3Thereby obtaining a reference voltage with zero temperature coefficient.
VBE1＝VBE2+I*R1
I＝(VBE1-VBE2)/R1＝△VBE/R1
VBG＝VBE3The expression of the current is introduced into the expression by + I R2
VBG＝VBE3+(R2/R1)*△VBE＝VBE3+(R2/R1)*VT*ln(Q2/Q1)
The transistor Q2 is composed of N parallel transistor cells, and the transistor Q1 is a transistor cell, so Δ VBE＝VT*lnN
Therefore, VBG＝VBE3+(R2/R1)*VT*lnN
In the formula: vBE1Is the base-emitter voltage difference, V, of the first transistor Q1BE2Is the base-emitter voltage difference, V, of the second transistor Q2BE3Is a third transistor Q3 base-emitterThe difference between the emitter voltages, R1 and R2, respectively, represents the corresponding resistance value, VTIs the threshold voltage, V, of the transistorBGThe output reference voltage is Q1, the number of parallel transistor units of the first transistor is Q2, the number of parallel transistor units of the second transistor is Q2, and N is the ratio of the number of parallel transistor units of the second transistor Q1.
Wherein M1, M2, M9 and M10 are NMOS transistors; m3, M4, M5, M6, M7, M8, M11, M12, M13 and M14 are PMOS transistors; the first transistor Q1, the second transistor Q2, and the third transistor Q3 are bipolar transistors.
In order to ensure that the circuit can get rid of degeneracy point when the power supply is powered on, the invention also discloses a starting circuit to ensure the normal operation of the circuit. The starting circuit comprises transistors M15, M16, M17, M18, M19, M20 and a third resistor R3; the transistors M15 and M16 are mirror images, the drain of the transistor M15 and the gates of the transistors M15 and M16 are connected to one end of a third resistor R3; the other end of the third resistor R3 is connected with the drain of the transistor M17; the sources of the transistors M17, M18, M19 and M20 are respectively connected with a power supply; the gate of transistor M17 is controlled by enable signal ENB; the drains of the transistors M18 and M19 are connected with the gates of M19 and M20; the gate of transistor M18 is connected to the gate of M5, using the same bias voltage VB(ii) a The drain of transistor M20 is connected to the drain of M1.
The working principle of the starting circuit is as follows: when the power supply starts to be powered on, the PMOS transistors M19 and M20 and the NMOS transistor M16 start to be in saturated conduction, the drain electrode of the PMOS transistor M20 is connected with the drain electrode of the PMOS transistor M3, so that the voltage of the drain electrode of the PMOS transistor M3 and the voltage of the gate electrode of the NMOS transistor M1 are pulled up, and the self-bias loop is separated from a degenerate point; as the normal state of the loop is gradually established, the gate voltage of the PMOS transistor M18 is pulled low to turn on, so that the drain voltage of M18 is pulled high, and the gate voltages of the transistors M19 and M20 connected with the drain of M18 are raised to turn off M19 and M20, and finally the bandgap reference circuit enters a normal working state.
Wherein, M17, M18, M19 and M20 are PMOS transistors, and M15 and M16 are NMOS transistors.
The band-gap reference circuit comprises a self-biased band-gap reference circuit and a starting circuit, the band-gap reference circuit adopts a self-biased cascode current mirror structure, the power supply rejection ratio of the band-gap reference circuit is improved while more accurate image current is obtained, and the power consumption and the area of the band-gap reference circuit are effectively reduced by a self-biasing implementation mode, so that the band-gap reference circuit which is insensitive to power supply voltage, low in power consumption, low in temperature coefficient and fast in response is obtained.
It will be appreciated by those skilled in the art that the self-biased bandgap reference circuit of the present invention is not limited to the embodiments described in the detailed description, and the above detailed description is for the purpose of illustrating the invention and is not intended to limit the invention. Other embodiments will be apparent to those skilled in the art from the following detailed description, which is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Claims (6)
1. A self-biased bandgap reference circuit, comprising a bandgap reference circuit and a start-up circuit;
the bandgap reference circuit includes: transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13 and M14, a first transistor Q1, a second transistor Q2, a third transistor Q3, a first resistor R1 and a second resistor R2, a first current mirror composed of transistors M1 and M2, and a second cascode current mirror composed of transistors M3, M4, M5, M6, M7 and M8;
the drain of the transistor M1 is connected with the drain of the transistor M3 and the gates of the transistors M1 and M2, and the gate bias voltage is supplied to the transistors M1 and M2; the drain electrode of the transistor M2 is connected with the drain electrode of the transistor M4 and the gate electrodes of the transistors M5, M6, M8 and M11, and a gate bias voltage is provided for the transistors M5, M6, M8 and M11; the sources of the transistors M5, M6, M8 and M11 are connected in parallel with a power supply; the drain of the transistor M5 is connected to the source of the transistor M3; the drain of the transistor M6 is connected to the source of the transistor M4; the drain of the transistor M8The source of the transistor M7 is connected; the drain electrode of the transistor M11 is connected with the grid electrode and the drain electrode of the transistor M9; the gate of the transistor M9 is connected with the gate of the mirror transistor M10 to provide bias current for the branch in which the transistor M9 is positioned; the drain of the transistor M10 is connected to the drain of the transistor M12; the source of the transistor M9 and the source of the transistor M10 are connected and grounded; the gates of the transistors M3, M4 and M7 are connected with the gates of the transistor groups M12, M13 and M14 which are connected in series, and gate bias voltages are provided for the transistors M3, M4 and M7; the base electrode of the first transistor Q1 is connected with the collector electrode and grounded, and the emitter electrode of the first transistor Q1 is connected with the source electrode of the transistor M1; the base electrode and the collector electrode of the second transistor Q2 are connected and grounded, the emitter electrode of the second transistor Q2 is connected with one end of a first resistor R1, the other end of the first resistor R1 is connected with the source electrode of a transistor M2, and a current value which is in direct proportion to a temperature coefficient is generated; the base electrode and the collector electrode of the third transistor Q3 are connected and grounded, the emitter electrode of the third transistor Q3 is connected with one end of a second resistor R2, the other end of a second resistor R2 is connected with the drain electrode of a transistor M7, a voltage value inversely proportional to a temperature coefficient is generated, and the starting circuit comprises transistors M15, M16, M17, M18, M19, M20 and a third resistor R3; the transistors M15 and M16 are mirror images, the drain of the transistor M15 and the gates of the transistors M15 and M16 are connected to one end of a third resistor R3; the other end of the third resistor R3 is connected with the drain of the transistor M17; the sources of the transistors M17, M18, M19 and M20 are respectively connected with a power supply; the gate of transistor M17 is controlled by enable signal ENB; the drains of the transistors M18 and M19 are connected with the gates of M19 and M20; the gate of transistor M18 is connected to the gate of M5, using the same bias voltage VB(ii) a The drain of transistor M20 is connected to the drain of M1.
2. The self-biased bandgap reference circuit of claim 1, wherein the M1, M2, M9 and M10 are NMOS transistors.
3. The self-biased bandgap reference circuit of claim 1, wherein the M3, M4, M5, M6, M7, M8, M11, M12, M13 and M14 are PMOS transistors.
4. The self-biased bandgap reference circuit of claim 1, wherein the first transistor Q1, the second transistor Q2 and the third transistor Q3 are bipolar transistors.
5. The self-biased bandgap reference circuit according to claim 1, wherein the M17, M18, M19 and M20 are PMOS transistors.
6. The self-biased bandgap reference circuit according to claim 1, wherein the M15 and M16 are NMOS transistors.
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| CN112230703A (en) * | 2020-10-30 | 2021-01-15 | 电子科技大学 | High-precision band-gap reference current source based on clamping technology |
| CN112486240A (en) * | 2020-12-09 | 2021-03-12 | 北方工业大学 | Band-gap reference circuit controlled by common-source amplifier |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101819449A (en) * | 2010-04-16 | 2010-09-01 | 上海理工大学 | Subthreshold MOSFET band-gap reference source |
| CN102012715A (en) * | 2010-11-24 | 2011-04-13 | 天津泛海科技有限公司 | Band-gap reference voltage source compensated by using high-order curvature |
| CN102073333A (en) * | 2009-11-24 | 2011-05-25 | 上海华虹Nec电子有限公司 | Voltage reference circuit with switch control characteristic |
| CN203838588U (en) * | 2014-03-18 | 2014-09-17 | 苏州市职业大学 | Self-biasing band-gap reference source |
| CN105022441A (en) * | 2014-04-30 | 2015-11-04 | 中国科学院声学研究所 | Temperature-independent current reference |
| CN105425891A (en) * | 2015-11-19 | 2016-03-23 | 苏州市职业大学 | Zero-temperature coefficient adjustable voltage reference source |
| CN107967020A (en) * | 2017-12-29 | 2018-04-27 | 成都信息工程大学 | A kind of low voltage reference circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2498162B1 (en) * | 2011-03-07 | 2014-04-30 | Dialog Semiconductor GmbH | Startup circuit for low voltage cascode beta multiplier current generator |
-
2019
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Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102073333A (en) * | 2009-11-24 | 2011-05-25 | 上海华虹Nec电子有限公司 | Voltage reference circuit with switch control characteristic |
| CN101819449A (en) * | 2010-04-16 | 2010-09-01 | 上海理工大学 | Subthreshold MOSFET band-gap reference source |
| CN102012715A (en) * | 2010-11-24 | 2011-04-13 | 天津泛海科技有限公司 | Band-gap reference voltage source compensated by using high-order curvature |
| CN203838588U (en) * | 2014-03-18 | 2014-09-17 | 苏州市职业大学 | Self-biasing band-gap reference source |
| CN105022441A (en) * | 2014-04-30 | 2015-11-04 | 中国科学院声学研究所 | Temperature-independent current reference |
| CN105425891A (en) * | 2015-11-19 | 2016-03-23 | 苏州市职业大学 | Zero-temperature coefficient adjustable voltage reference source |
| CN107967020A (en) * | 2017-12-29 | 2018-04-27 | 成都信息工程大学 | A kind of low voltage reference circuit |
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