CN112217500B - High-precision low-power-consumption power-on reset circuit - Google Patents
High-precision low-power-consumption power-on reset circuit Download PDFInfo
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- CN112217500B CN112217500B CN202011395122.7A CN202011395122A CN112217500B CN 112217500 B CN112217500 B CN 112217500B CN 202011395122 A CN202011395122 A CN 202011395122A CN 112217500 B CN112217500 B CN 112217500B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
Abstract
The invention discloses a high-precision low-power-consumption power-on reset circuit, which comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first field-effect tube, a second field-effect tube, a third field-effect tube, a triode group and a second triode, wherein the triode group and the second triode are formed by connecting 8 same first triodes in parallel; the power-on reset circuit is simple in structure and consumes less power.
Description
Technical Field
The invention relates to the technical field of portable wearable and other low-power-consumption application, in particular to a high-precision low-power-consumption power-on reset circuit.
Background
The power-on reset circuit is a common circuit and is used for determining the initial state of the circuit when power supply voltage drops below working voltage and resetting the state of the circuit so as to ensure that the state is not wrong. If a conventional reset circuit needs to ensure certain precision, a reference circuit and a comparator are generally needed to realize the conventional reset circuit, and certain power consumption needs to be consumed. In the current portable products mainly including lithium batteries, it is important to reduce power consumption and improve precision, but the current power-on reset circuit has less consumption.
Disclosure of Invention
Based on the defects of the prior art, the invention provides the power-on reset circuit with high precision and low power consumption, the reference circuit and the comparator which are required by the power-on reset circuit are integrated into one circuit, the circuit structure is simple, the area and the power consumption are saved, an independent reference circuit is not required, the problem that the reset circuit generates error signals because no power-on reference is well established is solved, and the circuit is more reliable.
The technical scheme of the invention is as follows:
the utility model provides a power-on reset circuit of high accuracy low-power consumption which characterized in that: the circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first field-effect tube MP1, a second field-effect tube MP2, a third field-effect tube MP3, a triode group formed by connecting 8 identical first triodes Q1 in parallel and a second triode Q2; the first end of the first resistor R1 is connected with the second end of the second resistor R2, the second end of the first resistor R1 is grounded VSS, the first end of the second resistor R2 is connected with a power supply voltage VDD, the source and the substrate of the first field effect transistor MP1, the source and the substrate of the second field effect transistor MP2, and the source and the substrate of the third field effect transistor MP3 are all connected with the power supply voltage VDD, the gate of the first field effect transistor MP1 is connected with the gate of the second field effect transistor MP2, the drain of the second field effect transistor MP2 is connected with the gate of the third field effect transistor MP3, the gate of the first field effect transistor MP1 is also connected with the drain thereof, the drain of the first field effect transistor is also respectively connected with the collectors of the 8 first triodes Q1, the emitters of the 8 parallel first triodes Q1 are respectively connected with the first end of the third resistor R3, the second end of the third resistor R3 is connected with the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is grounded, the bases of 8 parallel first triodes Q1 are respectively connected with the base of the second triode Q2 and also connected with the second end of the second resistor R2, the drain of the second field effect transistor MP2 is connected with the collector of the second triode Q2, the emitter of the second triode Q2 is connected with the second end of the third resistor R3, the drain of the third field effect transistor MP3 is connected with the first end of the fifth resistor R5, the second end of the fifth resistor R5 is grounded VSS, and the voltage of the drain of the third field effect transistor MP3 is used as the output end of the reset voltage RSTB.
Further, the first fet MP1, the second fet MP2, and the third fet MP3 are all P-type fets.
Further, each of the first transistors Q1 in the transistor group is an NPN transistor.
Further, the second transistor Q2 is an NPN transistor.
The invention has the beneficial effects that: the power-on reset circuit has a simple structure, consumes less power consumption, can achieve higher detection voltage precision, and can ensure the reliability of power-on reset signal generation.
Drawings
FIG. 1 is a schematic circuit diagram of the present invention;
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the features of the following embodiments and examples may be combined with each other without conflict.
As shown in fig. 1, a high-precision low-power-consumption power-on reset circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first fet MP1, a second fet MP2, a third fet MP3, a triode group formed by connecting 8 identical first triodes Q1 in parallel, and a second triode Q2; the first end of the first resistor R1 is connected with the second end of the second resistor R2, the second end of the first resistor R1 is grounded VSS, the first end of the second resistor R2 is connected with a power supply voltage VDD, the source and the substrate of the first field effect transistor MP1, the source and the substrate of the second field effect transistor MP2, and the source and the substrate of the third field effect transistor MP3 are all connected with the power supply voltage VDD, the gate of the first field effect transistor MP1 is connected with the gate of the second field effect transistor MP2, the drain of the second field effect transistor MP2 is connected with the gate of the third field effect transistor MP3, the gate of the first field effect transistor MP1 is also connected with the drain thereof, the drain of the first field effect transistor is also respectively connected with the collectors of the 8 first triodes Q1, the emitters of the 8 parallel first triodes Q1 are respectively connected with the first end of the third resistor R3, the second end of the third resistor R3 is connected with the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is grounded, the bases of 8 parallel first triodes Q1 are respectively connected with the base of the second triode Q2 and also connected with the second end of the second resistor R2, the drain of the second field effect transistor MP2 is connected with the collector of the second triode Q2, the emitter of the second triode Q2 is connected with the second end of the third resistor R3, the drain of the third field effect transistor MP3 is connected with the first end of the fifth resistor R5, the second end of the fifth resistor R5 is grounded VSS, and the voltage of the drain of the third field effect transistor MP3 is used as the output end of the reset voltage RSTB.
It should be noted that, P-type fets are adopted as the first fet MP1, the second fet MP2, and the third fet MP3, an NPN-type transistor is adopted as each first transistor Q1 in the triode group, and an NPN-type transistor is also adopted as the second transistor Q2.
The working principle is as follows:
the detected power voltage VDD is divided by a first resistor R1 and a second resistor R2 to obtain a voltage VDIV, a reference circuit is formed by 8 first triodes Q1, a second triode Q2, a third resistor R3, a fourth resistor R4, a first field effect tube MP1 and a second field effect tube MP2 which are connected in parallel, the traditional reference circuit is self-biased and finally generates a band gap reference voltage, the voltage VDIV is divided into partial voltage VDIV bias, the VDIV is connected to the base electrode of a reference core triode formed by a triode group formed by 8 first triodes Q1 and a second triode Q2, and the proportion of the reference core triode group to the second triode is 8: 1, MP1 and MP2 are load tubes and can be of the same size.
When the power supply voltage VDD rises, the divided voltage VDIV also rises, the current increase of Q2 is greater than the current of Q1, the current of Q1 is mirrored to MP2 through MP1, and when the current of Q2 is greater than the current of MP2, the gate of the third fet MP3 is pulled low, the current of MP3 is increased, and is greater than the current of the fifth resistor R5, thereby triggering the next stage circuit formed by the third fet MP3 and the fifth resistor R5 to flip, and the output RSTB goes high. Wherein, the formula of the turning point is derived as follows:
VDD is subjected to voltage division through R2 and R1 to obtain VDIV,
the VDIV voltage is determined by the difference between the base and emitter of the second transistor Q2 and the voltage drop across the fourth resistor R4.
VBE2 is the difference between the base and emitter of the second transistor Q2, IR4 is the current flowing through R4, and R4 is the resistance of R4.
Since the two branches at the turning point are equal in current, the current at R4 is twice the current at R3.
The R3 current is the difference between the VBE2 of the second transistor Q2 and the VBE1 of the 8 parallel first transistors Q1 divided by the R3 resistance.
As a result of this, it is possible to,
icq2 and Icq1, which are the collector currents of the second transistor Q2 and the first transistor Q1, respectively, are equal, i.e., Icq1= Icq 2. Ln is a natural logarithmic sign, and the triode group is formed by connecting 8 first triodes Q1 in parallel, so that the saturation current is
Therefore, the temperature of the molten steel is controlled,
substituting the VDIV expression yields:
the final trip point voltage translated to VDD is:
VBE2 is a negative temperature coefficient voltage, Vt is a positive temperature coefficient voltage, specifically Vt = KT/q, zero temperature coefficient voltage can be obtained by adjusting the ratio of R4 to R3, a required power-on reset voltage can be obtained by adjusting the resistance ratio of R1 to R2, and high precision of the flipping voltage can be achieved.
As mentioned above, when the voltage VDD increases, the current of the transistor Q2 is greater than the current of Q1, the current of Q1 is mirrored to MP2 through MP1, the current of Q2 is greater than the current of MP2, so that the gate voltage of the third fet MP3 is pulled low, the current of MP3 increases, the current flowing through the third fet MP3 is greater than the current flowing through R5, the output RSTB changes from low to high, and the state inversion is completed. R5 uses a resistor to ensure that RSTB is pulled low when the power-on voltage is low, ensuring that RSTB is in the reset state.
The structure does not specially generate a reference voltage to be compared with the divided voltage VDIV, and has three advantages:
the expense of the comparator is saved, and the power consumption and the area are saved;
offset voltage can be introduced into the comparator, the error of reset voltage is increased, and the structure is better in precision.
And no special reference voltage signal exists, so that the interference of overshoot and the like caused by the reference voltage along with the fluctuation of the power supply is not needed to be worried, the misoperation of the reset circuit is caused, and the reset circuit is more reliable.
The above embodiments are merely representative of the centralized embodiments of the present invention, and the description thereof is specific and detailed, but it should not be understood as the limitation of the scope of the present invention, and it should be noted that those skilled in the art can make various changes and modifications without departing from the spirit of the present invention, and these changes and modifications all fall into the protection scope of the present invention. Therefore, the protection scope of the present patent should be subject to the appended claims.
Claims (4)
1. The utility model provides a power-on reset circuit of high accuracy low-power consumption which characterized in that: the circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first field-effect tube MP1, a second field-effect tube MP2, a third field-effect tube MP3, a triode group formed by connecting 8 identical first triodes Q1 in parallel and a second triode Q2; the first end of the first resistor R1 is connected with the second end of the second resistor R2, the second end of the first resistor R1 is grounded VSS, the first end of the second resistor R2 is connected with a power supply voltage VDD, the source and the substrate of the first field effect transistor MP1, the source and the substrate of the second field effect transistor MP2, and the source and the substrate of the third field effect transistor MP3 are all connected with the power supply voltage VDD, the gate of the first field effect transistor MP1 is connected with the gate of the second field effect transistor MP2, the drain of the second field effect transistor MP2 is connected with the gate of the third field effect transistor MP3, the gate of the first field effect transistor MP1 is also connected with the drain thereof, the drain of the first field effect transistor is also respectively connected with the collectors of the 8 first triodes Q1, the emitters of the 8 parallel first triodes Q1 are respectively connected with the first end of the third resistor R3, the second end of the third resistor R3 is connected with the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is grounded, the bases of 8 parallel first triodes Q1 are respectively connected with the base of the second triode Q2 and also connected with the second end of the second resistor R2, the drain of the second field effect transistor MP2 is connected with the collector of the second triode Q2, the emitter of the second triode Q2 is connected with the second end of the third resistor R3, the drain of the third field effect transistor MP3 is connected with the first end of the fifth resistor R5, the second end of the fifth resistor R5 is grounded VSS, and the voltage of the drain of the third field effect transistor MP3 is used as the output end of the reset voltage RSTB.
2. The high accuracy low power consumption power-on-reset circuit of claim 1, wherein: the first field effect transistor MP1, the second field effect transistor MP2 and the third field effect transistor MP3 are P-type field effect transistors.
3. The high accuracy low power consumption power-on-reset circuit of claim 1, wherein: each of the first transistors Q1 in the transistor group is an NPN transistor.
4. The high accuracy low power consumption power-on-reset circuit of claim 1, wherein: the second triode Q2 adopts an NPN type triode.
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| CN202011395122.7A CN112217500B (en) | 2020-12-03 | 2020-12-03 | High-precision low-power-consumption power-on reset circuit |
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| CN112217500B true CN112217500B (en) | 2021-03-26 |
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| US6879194B1 (en) * | 2003-08-25 | 2005-04-12 | National Semiconductor Corporation | Apparatus and method for an active power-on reset current comparator circuit |
| US6933769B2 (en) * | 2003-08-26 | 2005-08-23 | Micron Technology, Inc. | Bandgap reference circuit |
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Address after: Room 3104, block a, building 8, Shenzhen International Innovation Valley, Dashi 1st Road, Xili community, Nanshan District, Shenzhen, Guangdong 518000 Patentee after: Shenzhen yingjixin Technology Co.,Ltd. Address before: Room 3104, block a, building 8, Shenzhen International Innovation Valley, Dashi 1st Road, Xili community, Nanshan District, Shenzhen, Guangdong 518000 Patentee before: SHENZHEN INJOINIC TECHNOLOGY Co.,Ltd. |
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