CN112684239A

CN112684239A - Low-temperature-drift power supply voltage detection circuit

Info

Publication number: CN112684239A
Application number: CN202110084048.5A
Authority: CN
Inventors: 谭在超; 张胜; 涂才根; 丁国华; 罗寅
Original assignee: Suzhou Covette Semiconductor Co ltd
Current assignee: Suzhou Covette Semiconductor Co ltd
Priority date: 2021-01-21
Filing date: 2021-01-21
Publication date: 2021-04-20

Abstract

The invention discloses a low temperature drift power supply voltage detection circuit, sources of a first PMOS tube P1, a second PMOS tube P2 and a third PMOS tube P3 of the circuit are connected with a power supply voltage VCC, a drain electrode and a grid electrode of the first PMOS tube P1 and a grid electrode of the second PMOS tube P2 are connected together, a drain electrode of the second PMOS tube P2 is connected with a grid electrode of the third PMOS tube P3, a drain electrode of the third PMOS tube 737P 6 is connected with a fifth resistor R5, a connection point of the first resistor R1 and the second resistor R2 is connected with a base electrode of a first NPN type triode Q1, a collector electrode of the first NPN type triode Q1 is connected with a drain electrode of the first NPN tube P1, an emitter electrode of the first NPN type triode Q1 is connected with a third resistor R3, a base electrode of the first NPN type triode Q5 is connected with a base electrode of the second NPN type triode Q2, a collector electrode of the second NPN type triode Q2 is connected with a fourth emitter electrode of the second NPN type PMOS tube P2 and a collector electrode 599, the chip area is saved, the power consumption current is reduced, and the application cost is greatly reduced.

Description

Low-temperature-drift power supply voltage detection circuit

Technical Field

The invention relates to the technical field of analog integrated circuit design, in particular to a low-temperature-drift power supply voltage detection circuit.

Background

In the design process of an analog integrated circuit, a circuit has certain requirements on the voltage of a power supply, the circuit cannot be normally started and operated if the power supply voltage is too low, and the circuit is possibly damaged if the power supply voltage is too high, so the voltage of the power supply generally needs to be detected, the circuit is started only when the power supply voltage meets the requirements, the detection on the power supply voltage cannot be influenced by temperature change, a common low-temperature-drift power supply voltage detection circuit is shown in fig. 1, resistors Rf1 and Rf2 in the diagram divide and sample the power supply voltage VCC to obtain the voltage VP:

VP=VCC*Rf2/(Rf1+Rf2)

the Bandgap reference block (Bandgap) generates a Bandgap reference voltage Vref which varies only negligibly with temperature, the voltages Vref and VP are connected to the non-inverting and inverting inputs of a comparator COMP, respectively, OUT is connected to the output of the comparator COMP, when VP > Vref, i.e.:

VCC>Vref*(Rf1+Rf2)/Rf2

OUT outputs a low level, indicating that the supply voltage VCC is above the set threshold,

when VP < Vref, i.e.:

VCC<Vref*(Rf1+Rf2)/Rf2

OUT outputs a high level, indicating that the supply voltage VCC is below the set threshold,

the circuit structure in fig. 1 needs to use an independent Bandgap reference module (Bandgap) and a comparator module (COMP), the circuit structure is complex, the power consumption current is large, the chip area is large, the application cost is high, and based on the above reasons, the circuit of the present invention combines the Bandgap reference module and the comparator module together well, thereby improving the defects of the original detection circuit.

Disclosure of Invention

In order to solve the above technical problem, the present invention provides a low temperature drift power supply voltage detection circuit, which includes a power supply Voltage (VCC), a first PMOS transistor (P1), a second PMOS transistor (P2), a third PMOS transistor (P3), a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), a fifth resistor (R5), a first NPN type triode (Q1), a second NPN type triode (Q2), sources of the first PMOS transistor (P1), the second PMOS transistor (P2), and the third PMOS transistor (P3) are connected to the power supply Voltage (VCC), a drain and a gate of the first PMOS transistor (P1) and a gate of the second PMOS transistor (P2) are connected together, a drain of the second PMOS transistor (P2) is connected to a gate of the third PMOS transistor (P3), a drain of the third PMOS transistor (P3) is connected to the first resistor (R1), and a drain of the third PMOS transistor (P5) is connected to the third resistor (R1), the collector of the first NPN type triode (Q1) is connected with the drain of a first PMOS (P1), the emitter of the first NPN type triode (Q1) is connected with a third resistor (R3), the base of the first NPN type triode (Q1) is connected with the base of a second NPN type triode (Q2), the collector of the second NPN type triode (Q2) is connected with the drain of a second PMOS (P2), the emitter of the second NPN type triode (Q2), a third resistor (R3) and a fourth resistor (R4) are connected, and the connection position of the third PMOS (P3) and the fifth resistor (R5) is connected with an OUT output end.

As a modification of the invention, a first resistor (R1) and a second resistor (R2) divide and sample the power supply Voltage (VCC) to form a divided and sampled voltage VA, and a voltage VB is formed between a first PMOS tube (P1) and a second PMOS tube (P2).

As an improvement of the invention, the supply Voltage (VCC) rises, the voltage VB outputs a low level, and the OUT output terminal outputs a high level.

As an improvement of the invention, the supply Voltage (VCC) is reduced, the voltage VB outputs a high level, and the OUT output terminal outputs a low level.

As a modification of the present invention, the first resistor (R1) and the second resistor (R2) are resistors made of the same material.

As a modification of the invention, the width-to-length ratio W/L values of the first PMOS tube (P1) and the second PMOS tube (P2) are equal.

As an improvement of the present invention, the emitter area ratio of the first NPN type triode (Q1) and the second NPN type triode (Q2) is N:1, and the emitters of the first NPN type triode (Q1) and the second NPN type triode (Q2) form currents I1 and I2.

The invention has the beneficial effects that: the low-temperature-drift power supply voltage detection circuit provided by the invention has a simple structure, realizes low-temperature drift of power supply voltage detection, saves the chip area by more than 50% because a special band gap reference module and a comparator module are omitted, reduces the power consumption current by more than 60%, greatly reduces the application cost, and simultaneously realizes the purpose of environmental protection and energy conservation.

Drawings

Fig. 1 is a schematic diagram of a detection circuit according to the background art.

Fig. 2 is a schematic structural diagram of a detection circuit according to an embodiment.

FIG. 3 is a diagram illustrating the variation of the comparison threshold voltage when the VB voltage is flipped at different temperatures according to the embodiment.

Detailed Description

The present invention will be further illustrated with reference to the accompanying fig. 1 to 3 and the following detailed description, which should be understood as merely illustrative and not limitative of the scope of the present invention.

Example (b): according to fig. 2, the circuit includes a power supply voltage VCC, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first NPN type triode Q1, and a second NPN type triode Q2, sources of the first PMOS transistor P1, the second PMOS transistor P2, and the third PMOS transistor P3 are connected to the power supply voltage VCC, a drain and a gate of the first PMOS transistor P1 and a gate of the second PMOS transistor P582 are connected together, a drain of the second PMOS transistor P56 is connected to a gate of the third PMOS transistor P3, a drain of the third PMOS transistor P3 is connected to the fifth resistor R5, a connection point of the first resistor R1 and the second resistor R2 is connected to a base of the first NPN type triode Q1, a collector of the first NPN type triode P1 is connected to the emitter of the third PMOS transistor P1, and a collector of the NPN type triode Q1, the base of the first NPN type triode Q1 is connected with the base of a second NPN type triode Q2, the collector of the second NPN type triode Q2 is connected with the drain of a second PMOS tube P2, the emitter of the second NPN type triode Q2 and a third resistor R3 are connected with a fourth resistor R4, and the joint of the third PMOS tube P3 and a fifth resistor R5 is connected with an OUT output end.

The first resistor R1 and the second resistor R2 divide and sample the power supply voltage VCC to form a divided and sampled voltage VA, and a voltage VB is formed between the first PMOS transistor P1 and the second PMOS transistor P2, wherein:

VA = VCC R2/(R1+ R2) -formula 1;

the width-to-length ratio W/L values of the first PMOS tube P1 and the second PMOS tube P2 are equal, the emitter area ratio of the first NPN type triode Q1 to the second NPN type triode Q2 is N:1, and the emitters of the first NPN type triode Q1 and the second NPN type triode Q2 form currents I1 and I2, wherein:

i1= (Vbe 2-Vbe 1)/R3 — formula 2;

vbe1 and Vbe2 are voltage values of emitters of the first NPN type triode Q1 and the second NPN type triode Q2, respectively, and are reverse saturation currents of the diodes according to Vbe1= VT × ln [ I1/(N × Is) ], Vbe2= VT × ln (I2/Is), Is,

substituting into formula 2 to obtain:

I1=（Vbe2-Vbe1）/R3

={ VT*ln（I2/Is）- VT*ln[I1/(N*Is)]}/R3

= VT × ln (N × I2/I1)/R3 — formula 3;

according to fig. 2, the current flowing through the fourth resistor R4 is:

i1+ I2= (VA-Vbe2)/R4 — formula 4;

when I1 equals I2, I1+ I2=2 × I1 — equation 5;

by combining equation 3, equation 4, and equation 5, the voltage value of VA when I1= I2 is set to VA 0:

(VA0-Vbe2)/R4=2I1=2 VT ln (N × I2/I1)/R3 — formula 6;

VA0 can be obtained with values:

VA0= Vbe2+2 VT ln (N × I2/I1) × R4/R3 — formula 7;

VA0= Vbe2+2 VT ln (n) R4/R3 — formula 8;

the temperature coefficient of Vbe2 is about-1.5 mV/K at room temperature, the temperature coefficient of VT is about 0.087mV/K,

as long as the condition is satisfied: 2 x ln (n) R4/R3 x 0.087mV-1.5mV =0,

namely: 2 x ln (n) R4/R3=17.2

According to equation 8, a threshold voltage VA0 that is approximately independent of temperature is obtained, and VA0 is the common bandgap reference voltage:

VA0= Vbe2+ VT 17.2 ≈ 1.17V — equation 9;

if the voltage of the power supply voltage VCC rises so that the voltage of the divided sampling voltage VA is greater than VA0, according to equation 7, the value of I2/I1 becomes large, at which time I1 is no longer equal to I2, i.e.: i2> I1, because the width-to-length ratio W/L values of the first PMOS tube P1 and the second PMOS tube P2 are equal, the current flowing through the second PMOS tube P2 can only be equal to the current flowing through the first PMOS tube P1 at most, so the base current of the second NPN type triode Q2 will become larger, the second NPN type triode Q2 enters a saturation region, namely VB outputs low level, and OUT outputs high level.

If the voltage of the power supply voltage VCC is lowered so that the voltage of the divided sampling voltage VA is less than VA0, the value of I2/I1 becomes smaller according to equation 7, at which time I1 is no longer equal to I2, i.e.: i2< I1, since the width-to-length ratio W/L values of the first PMOS transistor P1 and the second PMOS transistor P2 are equal, the first PMOS transistor P1 enters a linear region, namely VB outputs a high level and OUT outputs a low level.

The first resistor R1 and the second resistor R2 are resistors made of the same material, a divided sampling voltage VA obtained by dividing the power supply voltage VCC by the resistors is not influenced by temperature, and the comparison threshold voltage VA0 is not influenced by temperature, so the detection threshold value of the invention for the power supply voltage VCC is not influenced by temperature, FIG. 3 shows the comparison threshold voltage of VA0 when the VB voltage is inverted at 25 ℃, 40 ℃ and 125 ℃, respectively, the abscissa in FIG. 3 is the comparison threshold value of VA0, and the ordinate is the voltage value of VB, and it can be seen that the threshold voltage is not influenced by temperature change basically.

In the description of the present invention, it should be noted that the indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings only for the convenience of describing the present invention and simplifying the description, but do not indicate or imply that the indicated devices or elements must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention, and further, unless otherwise explicitly stated or limited, the terms "mounted," "connected" and "connected" should be construed broadly, e.g., as being fixedly connected, detachably connected, or integrally connected; the two components can be connected mechanically, electrically, directly or indirectly through an intermediate medium, and the two components can be communicated with each other, and the specific meaning of the above terms in the present invention can be understood by those skilled in the art.

Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that various modifications can be made to the embodiments described in the foregoing embodiments, or some or all of the technical features of the embodiments can be equivalently replaced, and the modifications or the replacements do not make the essence of the corresponding technical solutions depart from the scope of the embodiments of the present invention.

Claims

1. The low-temperature drift power supply voltage detection circuit is characterized by comprising a power supply Voltage (VCC), a first PMOS tube (P1), a second PMOS tube (P2), a third PMOS tube (P3), a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), a fifth resistor (R5), a first NPN type triode (Q1) and a second NPN type triode (Q2), wherein the sources of the first PMOS tube (P1), the second PMOS tube (P2) and the third PMOS tube (P3) are connected with the power supply Voltage (VCC), the drain and the gate of the first PMOS tube (P1) and the gate of the second PMOS tube (P6384) are connected together, the drain of the second PMOS tube (P1) is connected with the gate of the third PMOS tube (P3), the drain of the third PMOS tube (P3) is connected with the gate of the fifth PMOS tube (R3748), and the base of the third PMOS tube (R1) is connected with the resistor (R1), the collector of the first NPN type triode (Q1) is connected with the drain of a first PMOS (P1), the emitter of the first NPN type triode (Q1) is connected with a third resistor (R3), the base of the first NPN type triode (Q1) is connected with the base of a second NPN type triode (Q2), the collector of the second NPN type triode (Q2) is connected with the drain of a second PMOS (P2), the emitter of the second NPN type triode (Q2), a third resistor (R3) and a fourth resistor (R4) are connected, and the connection position of the third PMOS (P3) and the fifth resistor (R5) is connected with an OUT output end.

2. The power supply voltage detection circuit with low temperature drift according to claim 1, wherein the first resistor (R1) and the second resistor (R2) divide and sample the power supply Voltage (VCC) to form a divided and sampled voltage VA, a voltage VB is formed between the first PMOS transistor (P1) and the second PMOS transistor (P2), and when the divided and sampled voltage VA reaches a certain threshold, the voltage of the voltage VB is inverted.

3. The low temperature drift power supply voltage detecting circuit according to claim 2, wherein said power supply Voltage (VCC) is increased, voltage VB is outputted at a low level, and an OUT output terminal is outputted at a high level.

4. The low temperature drift power supply voltage detection circuit according to claim 3, wherein said power supply Voltage (VCC) is reduced, voltage VB outputs a high level, and an OUT output terminal outputs a low level.

5. The low-temperature-drift power supply voltage detection circuit according to claim 1, wherein the first resistor (R1) and the second resistor (R2) are resistors made of the same material.

6. The low-temperature-drift power supply voltage detection circuit according to claim 1, wherein the width-to-length ratio W/L values of the first PMOS transistor (P1) and the second PMOS transistor (P2) are equal.

7. The low-temperature-drift power supply voltage detection circuit according to claim 1, wherein an emitter area ratio of the first NPN type triode (Q1) and the second NPN type triode (Q2) is N:1, and emitters of the first NPN type triode (Q1) and the second NPN type triode (Q2) form currents I1 and I2.