CN214896358U

CN214896358U - Adjustable temperature coefficient reference voltage generator circuit structure

Info

Publication number: CN214896358U
Application number: CN202121663562.6U
Authority: CN
Inventors: 王国瑞; 张福泉; 汪金铭; 王圣礼
Original assignee: Shanghai Minsen Electronic Technology Co ltd
Current assignee: Shanghai Minsen Electronic Technology Co ltd
Priority date: 2021-07-21
Filing date: 2021-07-21
Publication date: 2021-11-26
Anticipated expiration: 2031-07-21

Abstract

The utility model discloses an adjustable temperature coefficient reference voltage generator circuit structure, including first bipolar transistor and second bipolar transistor, first bipolar transistor and second bipolar transistor's base is equallyd divide and is do not linked to each other with self collecting electrode, and is connected to public ground potential, first bipolar transistor and second bipolar transistor's input is equipped with first operational amplifier, first operational amplifier's input is equipped with first MOS transistor and second MOS transistor, just first MOS transistor and second MOS transistor all with first operational amplifier electric connection. The utility model discloses circuit structure can export the reference level of a customization adjustable temperature coefficient, and its temperature coefficient absolute value is undulant less along with factors such as technology, mains voltage, satisfies the requirement of most high accuracy analog chip to the reference level of specific temperature coefficient.

Description

Adjustable temperature coefficient reference voltage generator circuit structure

Technical Field

The utility model relates to a simulation chip technical field, more specifically say, the utility model relates to an adjustable temperature coefficient reference voltage generator circuit structure.

Background

High performance analog chips often require a customized specific temperature coefficient reference potential for achieving specific temperature performance of the entire circuit system, generally using a bandgap reference voltage (or a negative temperature coefficient PN junction potential difference with a certain absolute value) with an approximately zero temperature coefficient applied across a resistor with a suitable temperature coefficient, and leaving the resulting current through a resistor type with another temperature coefficient to obtain a specific temperature coefficient reference voltage that is close to the demand.

The prior art has the following defects: the absolute value of the temperature coefficient of the reference voltage obtained in the prior art is limited by the type of the resistor in the selected process, accurate matching with a demand side is difficult to realize, and the absolute value of the temperature coefficient of the reference voltage fluctuates greatly along with the process due to certain differences of the resistance values and the temperature coefficients of different types of resistors along with the fluctuation range of process angles.

SUMMERY OF THE UTILITY MODEL

In order to overcome the above-mentioned defect of prior art, the embodiment of the utility model provides an adjustable temperature coefficient reference voltage generator circuit structure, the reference level of the adjustable temperature coefficient of output customization, and its temperature coefficient absolute value is undulant little along with factors such as technology, mains voltage, can satisfy the requirement of high accuracy analog chip to the reference level of specific temperature coefficient to solve the problem that proposes in the above-mentioned background art.

In order to achieve the above object, the utility model provides a following technical scheme: including first bipolar transistor and second bipolar transistor, the base of first bipolar transistor and second bipolar transistor is equallyd divide and is linked to each other with self collector, and is connected to public ground potential, the input of first bipolar transistor and second bipolar transistor is equipped with first operational amplifier, the input of first operational amplifier is equipped with first MOS transistor and second MOS transistor, just first MOS transistor and second MOS transistor all with first operational amplifier electric connection.

In a preferred embodiment, the output terminal of the second MOS transistor is provided with a third MOS transistor and a fourth MOS transistor, and the third MOS transistor and the fourth MOS transistor are both electrically connected to the second MOS transistor.

In a preferred embodiment, a fifth MOS transistor, a sixth MOS transistor and a seventh MOS transistor are respectively disposed at an output terminal of the third MOS transistor, and the fifth MOS transistor, the sixth MOS transistor and the seventh MOS transistor are electrically connected to the third MOS transistor.

In a preferred embodiment, the output terminals of the third MOS transistor and the fourth MOS transistor are respectively provided with a first switch and a second switch, the output terminals of the sixth MOS transistor and the seventh MOS transistor are respectively provided with a third switch and a fourth switch, the output terminals of the first switch and the second switch are connected, and the output terminals of the third switch and the fourth switch are connected.

In a preferred embodiment, a first resistor is disposed at an input terminal of the second bipolar transistor, and an input terminal of the first resistor is electrically connected to the first operational amplifier.

In a preferred embodiment, a second operational amplifier is disposed at an output end of the fifth MOS transistor, a second resistor is disposed at an output end of the second operational amplifier, the second resistor is electrically connected to the second operational amplifier, the second operational amplifier is electrically connected to the fifth MOS transistor, and an output end of the second resistor is grounded.

In a preferred embodiment, the output terminals of the first switch and the second switch are provided with a third resistor, the input terminals of the first switch and the second switch are electrically connected with the third switch and the fourth switch, and the output terminal of the third resistor is grounded.

The utility model discloses a technological effect and advantage:

the utility model discloses circuit structure can export the reference level of a customization adjustable temperature coefficient, and its temperature coefficient absolute value is undulant less along with factors such as technology, mains voltage, satisfies the requirement of most high accuracy analog chip to the reference level of specific temperature coefficient.

Drawings

Fig. 1 is a circuit block diagram of the present invention.

Fig. 2 is a schematic circuit diagram of the present invention.

The reference signs are: 1. a first bipolar transistor; 2. a second bipolar transistor; 3. a first operational amplifier; 4. a first MOS transistor; 5. a second MOS transistor; 6. a third MOS transistor; 7. a fourth MOS transistor; 8. a fifth MOS transistor; 9. a sixth MOS transistor; 10. a seventh MOS transistor; 11. a second operational amplifier; 12. a first switch; 13. a second switch; 14. a third switch; 15. a fourth switch; 16. a first resistor; 17. a second resistor; 18. and a third resistor.

Schematic circuit diagram symbol:

q0: a first bipolar transistor

Q1: second bipolar transistor

OP 1: a first operational amplifier

OP 2: a second operational amplifier

M0: a first MOS transistor

M1: second MOS transistor

M2_ M: third MOS transistor

M2_ 1: fourth MOS transistor

M3: fifth MOS transistor

M4_ M: sixth MOS transistor

M4_ 1: seventh MOS transistor

Sm _ PTAT: first switch

S1_ PTAT: second switch

Sm _ CTAT: third switch

S1_ CTAT: the fourth switch

R0: a first resistor

R1: second resistance

R2: third resistance

VDD: power supply

GND: ground connection

VREF: output voltage

VBE0/VBE 1: emitter node

VSEL _ PTAT < m:0 >: bit signal

VSEL _ CTAT < m:0 >: bit control signal

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1-2 of the specification, an adjustable temperature coefficient reference voltage generator circuit structure according to an embodiment of the present invention includes a first bipolar transistor 1 and a second bipolar transistor 2, bases of the first bipolar transistor 1 and the second bipolar transistor 2 are connected to their collectors respectively and are connected to a common ground potential, an input end of the first bipolar transistor 1 and the second bipolar transistor 2 is provided with a first operational amplifier 3, an input end of the first operational amplifier 3 is provided with a first MOS transistor 4 and a second MOS transistor 5, the first MOS transistor 4 and the second MOS transistor 5 are electrically connected to the first operational amplifier 3, an output end of the second MOS transistor 5 is provided with a third MOS transistor 6 and a fourth MOS transistor 7 respectively, and the third MOS transistor 6 and the fourth MOS transistor 7 are electrically connected to the second MOS transistor 5, the emitter area ratio of the first bipolar transistor 1 to the second bipolar transistor 2 is 1: n, the quiescent currents flowing through the first bipolar transistor 1 and the second bipolar transistor 2 are equal, the non-inverting input terminal of the first operational amplifier 3 is connected to the upper end of the first resistor 16, and the inverting input terminal of the first operational amplifier 3 is connected to the emitter of the first bipolar transistor 1.

Further, the output end of the third MOS transistor 6 is provided with a fifth MOS transistor 8, a sixth MOS transistor 9 and a seventh MOS transistor 10, and the fifth MOS transistor 8, the sixth MOS transistor 9 and the seventh MOS transistor 10 are all electrically connected to the third MOS transistor 6, the output ends of the third MOS transistor 6 and the fourth MOS transistor 7 are provided with a first switch 12 and a second switch 13, respectively, the output ends of the sixth MOS transistor 9 and the seventh MOS transistor 10 are provided with a third switch 14 and a fourth switch 15, respectively, and the output ends of the first switch 12 and the second switch 13 are connected, the output ends of the third switch 14 and the fourth switch 15 are connected, the lower end of the first resistor 16 is connected to the emitter of the second bipolar transistor 2, the bases of the first bipolar transistor 1 and the second bipolar transistor 2 are connected to their collectors and to a common ground potential, the output end of the first operational amplifier 3 is connected with the gates of the first MOS transistor 4 and the second MOS transistor 5, and the drain ends of the first MOS transistor 4 and the second MOS transistor 5 are respectively connected with the inverting input end and the forward input end of the first operational amplifier 3.

Further, the input end of the second bipolar transistor 2 is provided with a first resistor 16, the input end of the first resistor 16 is electrically connected to the first operational amplifier 3, the output end of the fifth MOS transistor 8 is provided with a second operational amplifier 11, the output end of the second operational amplifier 11 is provided with a second resistor 17, the second resistor 17 is electrically connected to the second operational amplifier 11, the second operational amplifier 11 is electrically connected to the fifth MOS transistor 8, the output end of the second resistor 17 is grounded, the output ends of the first switch 12 and the second switch 13 are provided with a third resistor 18, the input ends of the first switch 12 and the second switch 13 are electrically connected to the third switch 14 and the fourth switch 15, the output end of the third resistor 18 is grounded, and the third MOS transistor 6, the fourth MOS transistor 7, the fifth MOS transistor 8, the second resistor 17, the third resistor 17, the fourth resistor 18, the fourth resistor 13, the fourth resistor, the third resistor, and the fourth resistor 18, The gates of the sixth MOS transistor 9 and the seventh MOS transistor 10 are connected to the output terminal of the first operational amplifier 3, the drain terminals thereof are connected to the upper ends of the first switch 12 and the second switch 13, respectively, the lower ends of the first switch 12 and the second switch 13 are connected to the output voltage VREF, two ends of the third resistor 18 are connected to the output voltage VREF and the common ground, respectively, the non-inverting input terminal of the second operational amplifier 11 is connected to the emitter node VBE1 of the second bipolar transistor 2, the inverting input terminal thereof is connected to the upper end of the first resistor 16 and the drain terminal of the fifth MOS transistor 8, the lower end of the second resistor 16 is connected to the common ground, the output terminal of the second operational amplifier 11 is connected to the gates of the fifth MOS transistor 8, the sixth MOS transistor 9 and the seventh MOS transistor 10, the drain terminals of the transistors of the sixth MOS transistor 9 and the seventh MOS transistor 10 are connected to the upper ends of the third switch 14 and the fourth switch 15, respectively, the lower ends of the third switch 14 and the fourth switch 15 are connected to the output voltage VREF.

The specific implementation mode is as follows: the expression for the output reference level VREF is:

as can be seen from the expression, the output reference level VREF is independent of the fluctuation of the resistance values of the first resistor 16, the second resistor 17 and the third resistor 18 of the same type, and is only related to the ratio of the third resistor 18/the first resistor 16 and the third resistor 18/the second resistor 17, and the ratio of the resistance values of the resistors of the same type is insensitive to the process fluctuation, so that the output reference level VREF and the absolute value of the temperature coefficient thereof are insensitive to the process fluctuation;

the on-off states of the switches can be arbitrarily combined according to requirements to obtain reference levels VREF with different absolute values of positive and negative temperature coefficients, and the on-off states of the switches Sm _ PTAT, Sm-1_ PTAT, … … S1_ PTAT, Sm _ 1_ CTAT and … … S1_ CTAT are respectively controlled by changing the high and low levels of the (m +1) bit signal VSEL _ PTAT < m:0> and the (m +1) bit control signal VSEL _ CTAT < m:0 >.

The points to be finally explained are: first, in the description of the present application, it should be noted that, unless otherwise specified and limited, the terms "mounted," "connected," and "connected" should be understood broadly, and may be a mechanical connection or an electrical connection, or a communication between two elements, and may be a direct connection, and "upper," "lower," "left," and "right" are only used to indicate a relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship may be changed;

secondly, the method comprises the following steps: in the drawings of the disclosed embodiments of the present invention, only the structures related to the disclosed embodiments are referred to, and other structures can refer to the common design, and under the condition of no conflict, the same embodiment and different embodiments of the present invention can be combined with each other;

and finally: the above description is only for the preferred embodiment of the present invention and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An adjustable temperature coefficient reference voltage generator circuit structure, comprising a first bipolar transistor (1) and a second bipolar transistor (2), wherein bases of the first bipolar transistor (1) and the second bipolar transistor (2) are respectively connected with a collector thereof and connected to a common ground potential, and input ends of the first bipolar transistor (1) and the second bipolar transistor (2) are provided with a first operational amplifier (3), characterized in that: the input end of the first operational amplifier (3) is provided with a first MOS transistor (4) and a second MOS transistor (5), and the first MOS transistor (4) and the second MOS transistor (5) are electrically connected with the first operational amplifier (3).

2. The adjustable temperature coefficient reference voltage generator circuit structure of claim 1, wherein: the output end of the second MOS transistor (5) is respectively provided with a third MOS transistor (6) and a fourth MOS transistor (7), and the third MOS transistor (6) and the fourth MOS transistor (7) are electrically connected with the second MOS transistor (5).

3. The adjustable temperature coefficient reference voltage generator circuit structure of claim 2, wherein: the output end of the third MOS transistor (6) is respectively provided with a fifth MOS transistor (8), a sixth MOS transistor (9) and a seventh MOS transistor (10), and the fifth MOS transistor (8), the sixth MOS transistor (9) and the seventh MOS transistor (10) are electrically connected with the third MOS transistor (6).

4. The adjustable temperature coefficient reference voltage generator circuit structure of claim 3, wherein: the output ends of the third MOS transistor (6) and the fourth MOS transistor (7) are respectively provided with a first switch (12) and a second switch (13), the output ends of the sixth MOS transistor (9) and the seventh MOS transistor (10) are respectively provided with a third switch (14) and a fourth switch (15), the output ends of the first switch (12) and the second switch (13) are connected, and the output ends of the third switch (14) and the fourth switch (15) are connected.

5. The adjustable temperature coefficient reference voltage generator circuit structure of claim 1, wherein: the input end of the second bipolar transistor (2) is provided with a first resistor (16), and the input end of the first resistor (16) is electrically connected with the first operational amplifier (3).

6. The adjustable temperature coefficient reference voltage generator circuit structure of claim 3, wherein: the output end of the fifth MOS transistor (8) is provided with a second operational amplifier (11), the output end of the second operational amplifier (11) is provided with a second resistor (17), the second resistor (17) is electrically connected with the second operational amplifier (11), the second operational amplifier (11) is electrically connected with the fifth MOS transistor (8), and the output end of the second resistor (17) is grounded.

7. The adjustable temperature coefficient reference voltage generator circuit structure of claim 4, wherein: the output ends of the first switch (12) and the second switch (13) are provided with a third resistor (18), the input ends of the first switch (12) and the second switch (13) are electrically connected with the third switch (14) and the fourth switch (15), and the output end of the third resistor (18) is grounded.