CN102609027B - Band-gap reference voltage source circuit - Google Patents

Band-gap reference voltage source circuit Download PDF

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CN102609027B
CN102609027B CN 201210088717 CN201210088717A CN102609027B CN 102609027 B CN102609027 B CN 102609027B CN 201210088717 CN201210088717 CN 201210088717 CN 201210088717 A CN201210088717 A CN 201210088717A CN 102609027 B CN102609027 B CN 102609027B
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band
gap
reference
voltage
source
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CN 201210088717
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CN102609027A (en )
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贾晓伟
邓龙利
王帅旗
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北京经纬恒润科技有限公司
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Abstract

本发明实施例公开了一种带隙基准电压源电路,包括第一PMOS管、第二PMOS管、第三PMOS管、第四PMOS管、第一NPN型三极管、第二NPN型三极管、第一电阻和第二电阻。 Example discloses a bandgap voltage reference circuit comprising a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, the fourth PMOS transistor, a first NPN transistor, a second NPN transistor of the present invention, a first and second resistors. 本发明公开的带隙基准电压源电路中没有用到误差放大器,因此省去了误差放大器自身的失调电压及噪声对系统的影响,并且节省了功耗和面积;另外,基准电压Vref的输出支路并未采用一个支路单独产生,也在一定程度上避免了电流镜像失陪引起的失调电压的影响,并且节省了面积和功耗。 Bandgap reference voltage source circuit of the present invention disclosed in the error amplifier is not used, thereby eliminating the influence of the error amplifier offset voltage and the noise itself to the system, and the power savings and area; Further, the reference voltage Vref output branch generating a branch road does not use separate, also to avoid the influence of the offset voltage caused by the current mirror excuse to some extent, and saves area and power consumption.

Description

一种带隙基准电压源电路 A tape-gap reference voltage source circuit

技术领域 FIELD

[0001] 本发明属于集成电路供电技术领域,尤其涉及一种带隙基准电压源电路。 [0001] The present invention belongs to the technical field of power integrated circuits, and particularly to a band gap reference voltage source circuit.

背景技术 Background technique

[0002] 在模拟集成电路或混合信号设计领域,基准电压源是一很重要的模块,为系统提供电压基准和电流基准。 [0002] In the analog integrated circuit or mixed signal design, a reference voltage source is a very important module, a voltage reference and current reference system. 随着电路集成度的提高,基准电压源也越来越多的集成到芯片内部,以降低系统成本。 With increased integration of circuits, a reference voltage source more and more integrated into the chip, to reduce system cost.

[0003] 传统的基准电压源通常依靠带隙基准电压源电路产生,如图1所示,该带隙基准电压源电路包含误差放大器、PMOS镜像电流源、PNP管及电阻,而基准电压通常由包含PMOS管PM3的镜像电流源、电阻R2及PNP管Q3的单独一条支路(在图1中以虚线标出)生成。 [0003] The conventional reference voltage source often rely on a bandgap reference voltage source generating circuit shown in Figure 1, the band gap reference voltage source circuit comprises an error amplifier, the PMOS current mirror, and the PNP tube resistance, and generally by a reference voltage mirror current source comprises PMOS transistor PM3, the resistor R2 and a PNP transistor Q3 is a single branch (indicated in phantom in FIG. 1) generated.

[0004] 但是,上述带隙基准电压源电路具有多种缺陷:因其包含误差放大器及相应的偏置电路,因此存在面积较大的问题;误差放大器自身的失调电压及噪声也会加到基准电压输出端Vref,而且,由于基准电压由一支路单独生成,因此,该带隙基准电压源电路中PM3、PMl和PM2镜像电流源间的镜像失配也会加大基准电压的失调电压。 [0004] However, in the band gap reference voltage source circuit has several drawbacks: includes an error amplifier and its corresponding bias circuit, there is a larger area problems; its error amplifier offset voltage and noise will be added to the reference voltage output Vref, and, since the reference voltage is generated solely by a road, and therefore, the voltage reference circuit with mirrored between PM3, PMl and PM2 current mirror mismatch also increases the offset voltage of the reference voltage.

发明内容 SUMMARY

[0005] 有鉴于此,本发明的目的在于提供一种带隙基准电压源电路,以解决现有技术中存在的面积大、失调电压大的问题。 [0005] In view of this, an object of the present invention is to provide a bandgap reference voltage source circuit, to solve the prior art a large area, a large offset voltage problem.

[0006] 为实现上述目的,本发明提供如下技术方案: [0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] 一种带隙基准电压源电路,包括第一PMOS管、第二PMOS管、第三PMOS管、第四PMOS管、第一NPN型三极管、第二NPN型三极管、第一电阻和第二电阻;其中: [0007] A bandgap voltage reference circuit comprising a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, the fourth PMOS transistor, a first NPN transistor, a second NPN transistor, and a first resistor second resistor; wherein:

[0008] 所述第一PMOS管和第二PMOS管的源极和衬底接入电源电压; [0008] The source and substrate of said first PMOS transistor and a second PMOS transistor access the power source voltage;

[0009] 所述第一PMOS管的栅极和第二PMOS管的栅极同时连接至所述第四PMOS管的源极及所述第二PMOS管的漏极; [0009] The gate of the first PMOS transistor and a second PMOS transistor while the fourth PMOS transistor is connected to the source and drain of the second PMOS transistor;

[0010] 所述第一PMOS管的漏极连接至所述第三PMOS管的源极; The drain [0010] The first PMOS transistor is connected to the source of the third PMOS transistor;

[0011] 所述第三PMOS管的衬底和第四PMOS管的衬底接入电源电压; [0011] The substrate and the fourth substrate, a third PMOS transistor PMOS transistor access the power source voltage;

[0012] 所述第三PMOS管的栅极和第四PMOS管的栅极同时连接至所述第二NPN型三极管的集电极及所述第四PMOS管的漏极; [0012] The gate of the third PMOS transistor and a fourth PMOS transistor while the drain is connected to the collector of the second NPN transistor and the fourth PMOS transistor;

[0013] 所述第三PMOS管的漏极通过所述第二电阻连接至所述第一NPN三极管的集电极; The drain [0013] The third PMOS transistor is connected to the collector of the first NPN transistor through the second resistor;

[0014] 所述第一NPN型三极管的基极和第二NPN型三极管的基极连接至所述第一NPN型三极管的集电极; [0014] The first NPN transistor and a base of the second NPN transistor base connected to the collector of the first NPN transistor;

[0015] 所述第一NPN型三极管的发射极接地; [0015] The first NPN transistor emitter is grounded;

[0016] 所述第二NPN型三极管的发射极通过所述第一电阻接地; [0016] The emitter electrode of the second NPN transistor is grounded via said first resistor;

[0017] 所述第三PMOS管的漏极作为基准电压输出端。 The drain [0017] The third PMOS transistor as a reference voltage output terminal.

[0018] 优选的,所述第一PMOS管和第二PMOS管的器件参数相同;所述第三PMOS管和第四PMOS管的器件参数相同;所述第一NPN型三极管和第二NPN三极管的发射极面积比为η: [0018] Preferably, the same device parameters of the first PMOS transistor and the second PMOS transistor; the same device parameters of the third PMOS transistor and a fourth PMOS transistor; the first NPN transistor and second NPN transistor the emitter area ratio of η:

Figure CN102609027BD00041

表示求导数,Vbel表示第一NPN型H极管的基极_发射 Represents the derivative, Vbel group represents a first NPN-type transistor is H _ emitter electrode

极结电压,T表示绝对温度,q表示电子电荷量,K表示波尔兹曼常数,R2表示第二电阻的电阻值,Rl表不第一电阻的电阻值。 Junction voltage, T is the absolute temperature, q an electron charge quantity, K represents the Boltzmann constant group, R2 represents the resistance value of the second resistor, Rl is not the first sheet resistance value of the resistor.

[0019] 由此可见,本发明的有益效果为:本发明公开的带隙基准电压源电路中没有用到误差放大器,因此省去了误差放大器自身的失调电压及噪声对系统的影响,并且节省了功耗和面积;另外,基准电压Vref的输出支路并未采用一个支路单独产生,也在一定程度上避免了电流镜像失陪引起的失调电压的影响,并且节省了面积和功耗。 [0019] Thus, the beneficial effects of the present invention are: a bandgap reference voltage source circuit of the present invention disclosed in the error amplifier is not used, thereby eliminating the influence of the error amplifier offset voltage and the noise itself to the system, and saves the power consumption and area; Further, the reference voltage Vref output branch does not use a separate branch generation, but also to avoid the influence of the offset voltage caused by the current mirror excuse to some extent, and saves area and power consumption.

附图说明 BRIEF DESCRIPTION

[0020] 为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。 [0020] In order to more clearly illustrate the technical solutions in the embodiments or the prior art embodiment of the present invention, briefly introduced hereinafter, embodiments are described below in the accompanying drawings or described in the prior art needed to be used in describing the embodiments figures some embodiments of the present invention, those of ordinary skill in the art is concerned, without creative efforts, can derive from these drawings other drawings.

[0021] 图1为现有的带隙基准电压源电路的结构图; [0021] FIG. 1 is a configuration diagram of a conventional bandgap reference voltage source circuit;

[0022] 图2为本发明公开的一种带隙基准电压源电路的结构图; [0022] FIG 2 is a configuration diagram of a bandgap reference discloses a voltage source circuit of the present invention;

[0023] 图3为图2所示带隙基准电压源电路的基准电压Vref随温度变化的Tcm曲线图。 Tcm graph [0023] FIG. 3 is a bandgap reference voltage source circuit shown in FIG. 2 the reference voltage Vref varies with temperature.

具体实施方式 detailed description

[0024] 为了引用和清楚起见,下文中使用的技术名词的说明、简写或缩写总结如下: [0024] For reference and clarity, the description of the technical terms used hereinafter, abbreviations or acronyms are summarized as follows:

[0025] PMOS, positive channel Metal Oxide Semiconductor, PMOS 管指n 型衬底、p 沟道,靠空穴的流动运送电流的MOS管。 [0025] PMOS, positive channel Metal Oxide Semiconductor, PMOS tube means n-type substrate, p-channel, MOS tube by the flow of the hole current transport.

[0026] 本发明公开了一种带隙基准电压源电路,用以解决现有技术中存在的面积大、失调电压大的问题。 [0026] The present invention discloses a bandgap voltage reference circuit for a tape to solve the prior art a large area, a large offset voltage problem. 其基本思路为:利用处于放大区的NPN管间基极-发射极电压差的正温度系数、基极-发射极电压的负温度系数,设计出一种低功耗、低面积、低失调电压、低噪声、结构简洁的带隙基准电压源电路。 The basic idea is: the use of an enlarged region in the NPN transistor between the base - emitter voltage difference between the positive temperature coefficient, the base - emitter voltage of negative temperature coefficient, the design of a low-power, low-area, low offset voltage , low noise, simple structure of the bandgap reference voltage source circuit.

[0027] 为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。 [0027] In order that the invention object, technical solutions, and advantages of the embodiments more clearly, the following the present invention in the accompanying drawings, technical solutions of embodiments of the present invention are clearly and completely described, obviously, the described the embodiment is an embodiment of the present invention is a part, but not all embodiments. 基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。 Based on the embodiments of the present invention, all other embodiments of ordinary skill in the art without any creative effort shall fall within the scope of the present invention.

[0028] 参见图2,图2为本发明公开的一种带隙基准电压源电路的结构图。 [0028] Referring to Figure 2, a structural diagram of FIG. 2 discloses a bandgap reference circuit of the present invention. 包括第一PMOS管PM1、第二PMOS管PM2、第三PMOS管PM3、第四PMOS管PM4、第一NPN型三极管Q1、第二NPN型三极管Q2、第一电阻Rl和第二电阻R2。 Comprising a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a first NPN transistor Q1, the second NPN transistor Q2, a first resistor Rl and the second resistor R2. 其中: among them:

[0029] 第一PMOS管PMl和第二PMOS管PM2的源极和衬底接入电源电压VDDA。 [0029] The first PMOS transistor and a second PMOS transistor PMl PM2 of the access source and substrate supply voltage VDDA. 第一PMOS管PMl的栅极和第二PMOS管PM2的栅极同时连接至第四PMOS管PM4的源极及第二PMOS管PM2的漏极。 Gate of the first PMOS transistor and a second PMOS transistor PMl PM2 while a source connected to a drain of the fourth PMOS transistor PM4 and PM2 of the second PMOS transistor. 第一PMOS管PMl的漏极连接至第三PMOS管PM3的源极。 Drain of the first PMOS transistor PMl is connected to a third source of PMOS transistor PM3. 第三PMOS管PM3的衬底和第四PMOS管PM4的衬底接入电源电压VDDA。 A third PMOS transistor PM3 substrate and a fourth substrate access PMOS transistor PM4 supply voltage VDDA. 第三PMOS管PM3的栅极和第四PMOS管PM4的栅极同时连接至第二NPN型三极管Q2的集电极及第四PMOS管PM4的漏极。 A third PMOS transistor gate of the fourth PMOS transistor PM3 and PM4 is simultaneously connected to the second NPN transistor Q2 and the collector of the drain of the fourth PMOS transistor PM4. 第三PMOS管PM3的漏极通过第二电阻R2连接至第一NPN三极管Ql的集电极。 Drain of the third PMOS transistor PM3 is connected to the collector of the first NPN transistor Ql via a second resistor R2. 第一NPN型三极管Ql的基极和第二NPN型三极管Q2的基极连接至第一NPN型三极管Ql的集电极。 A first NPN transistor Ql base and a second NPN transistor Q2 are connected to the collector of a first NPN transistor Ql. The first

一 NPN型三极管Ql的发射极接地。 Transmitting a NPN transistor Ql is grounded. 第二NPN型三极管Q2的发射极通过第一电阻Rl接地。 Transmitting a second NPN transistor Q2 is grounded electrode through a first resistor Rl. 第三PMOS管PM3的漏极作为基准电压Vref输出端。 The drain of the third PMOS transistor PM3 output terminal as the reference voltage Vref.

[0030] 在实施过程中,可通过设计使第一PMOS管PMl和第二PMOS管PM2的器件参数相同,使第三PMOS管PM3和第四PMOS管PM4的器件参数相同,并令第一NPN三极管Ql和第 [0030] In the process embodiment, may be designed so that the device parameters via the first PMOS transistor and a second PMOS transistor PMl PM2 is the same, so the same device parameter of the third PMOS transistor PM3 and PM4 of the fourth PMOS transistor, and so that the first NPN and the first transistor Ql

二 NPN三极管Q2的发射极面积比为η:1。 Two emitter area ratio of NPN transistor Q2 η: 1.

[0031] 上述带隙基准电压源电路的工作原理如下: [0031] The band gap reference voltage source circuit works as follows:

[0032] 当带隙基准电压源电路正常工作时,所有PMOS管、NPN型三极管处于饱和区及放大区,ΡΜ1、ΡΜ2及ΡΜ3、ΡΜ4组成共源共栅镜像电流源。 [0032] When the band gap reference voltage source circuit is working properly, all the PMOS transistor, the NPN type transistor in the saturation region and the enlarged area, ΡΜ1, ΡΜ2 and ΡΜ3, ΡΜ4 composition cascode cascode current mirror.

[0033] 由于电流镜像的作用,PMl所在支路的支路电流Idl与ΡΜ2所在支路的支路电流Id2相等,且Idl=Id2=Id,其中,Id为PMl及PM3的沟道电流。 [0033] Since the current mirror action, the branch current Idl ΡΜ2 PMl branch where the branch where the branch is equal to current Id2 and Idl = Id2 = Id, wherein, Id is the current channel PML and PM3. 由于Ql和Q2的电流放大倍数β ( β =Ic/Ib)较大,因此流过Ql的集电极电流Icl和流过Q2的集电极电流Ic2近似相等,Icl ^ Ic2=Id。 Since Ql and Q2 of the current amplification factor β (β = Ic / Ib) large, the collector current flowing through Ql Icl and collector current Ic2 flowing through Q2 are approximately equal, Icl ^ Ic2 = Id.

[0034] 因此,Q2、Ql的基极-发射极电压差dVbe为: [0034] Therefore, Q2, Ql base - emitter voltage difference is dVbe:

[0035] dVbe=Vbe2-Vbel= (KT/q)*ln (Ic2/Is2)- (KT/q)*ln (Icl/Isl) [0035] dVbe = Vbe2-Vbel = (KT / q) * ln (Ic2 / Is2) - (KT / q) * ln (Icl / Isl)

[0036] =(KT/q)*ln(Isl/Is2) (公式I) [0036] = (KT / q) * ln (Isl / Is2) (Formula I)

[0037] 其中,Vbel为Ql的基极-发射极结电压,Vbe2为Q2的基极-发射极结电压,K表示波尔兹曼常数,T为绝对温度,q表示电子电荷量,Isl为Ql的反向饱和电流,Is2为Q2的反向饱和电流,Icl为Ql的集电极电流,Ic2为Q2的集电极电流。 [0037] wherein, Vbel Ql is a base - emitter junction voltage, Vbe2 of Q2 to the base - emitter junction voltage, K represents the Boltzmann constant, T is the absolute temperature, q an electron charge quantity, Isl of Ql reverse saturation current, Is2 of the reverse saturation current of Q2, Icl is the collector current of Ql, Ic2 is the collector current of Q2.

[0038] 由于Q1、Q2的发射极面积比为η:1,所以Isl/Is2=n/1,故公式I可简化为: [0038] Since Q1, Q2 emitter area ratio η: 1, so Isl / Is2 = n / 1, it can be simplified as Equation I:

[0039] dVbe=Vbe2-Vbel= (KT/q)*1η(η) (公式2) [0039] dVbe = Vbe2-Vbel = (KT / q) * 1η (η) (Equation 2)

[0040] 上述dVbe即为电阻Rl的电压差,因此流过电阻Rl的电流IRl满足下述公式: [0040] dVbe is the voltage of the resistor Rl is poor, so a current flowing through the resistor Rl IRl satisfy the following equation:

[0041] IRl=IQl=IQ2=Id=(KT/q)*ln(n)/Rl (公式3) [0041] IRl = IQl = IQ2 = Id = (KT / q) * ln (n) / Rl (Equation 3)

[0042] 因此电阻R2两端的电压差VR2满足下述公式: [0042] Thus the difference between the voltage VR2 across the resistor R2 satisfy the following equation:

[0043] VR2=Id*R2=(KT/q)*ln(n)*R2/Rl (公式4) [0043] VR2 = Id * R2 = (KT / q) * ln (n) * R2 / Rl (Equation 4)

[0044] 基准电压源Vref满足下述公式: [0044] The reference voltage source Vref satisfy the following equation:

[0045] Vref=Vbel+VR2=Vbel+ (KT/q)*ln(n)*R2/R1 (公式5) [0045] Vref = Vbel + VR2 = Vbel + (KT / q) * ln (n) * R2 / R1 (Formula 5)

[0046] 对公式5对温度T求导数,为: [0046] Equation 5 for the derivative of the temperature T, is:

[0047] [0047]

Figure CN102609027BD00051

[0048] 因为上述r) VbeO/3 T为正温度系数,(κ/q)为负温度系数,因此根据公式6适当设置η的数值以及电阻Rl、R2的电阻值,可使Vref在常温时令公式6为零,从而保证在工作温度范围内具有最小的基准电压变化率。 [0048] Since the above r) VbeO / 3 T is a positive temperature coefficient, (κ / q) is a negative temperature coefficient, and a resistor value according to the formula Rl η 6 appropriately provided, the resistance value R2, the season can Vref at room temperature equation 6 is zero, and thus has a minimum guaranteed rate of change of the reference voltage within the operating temperature range.

[0049] 在电阻Rl和电阻R2的阻值一定时。 [0049] In certain resistance of the resistor Rl and resistor R2.

Figure CN102609027BD00052

,从而使公式6为零。 So that Equation 6 is zero.

[0050] 图2所示带隙基准电压源电路本身具有单级误差放大器的功能。 [0050] The band gap reference voltage source circuit shown in FIG. 2 itself has a function of a single stage of the error amplifier. 因为PM4结成二极管形式,因此可以认为PM4的源极和漏极为误差放大输出端,将PM4的源极与PM1、PM2的栅极相连,同时将PM4的漏极与PM3、PM4的栅极相连,以形成负反馈环路,将误差放大的电压信号转化为电流信号,从而维持公式(5)和公式(6)的成立。 Because diode PM4 form, it can be considered PM4 source and drain is the output of the error amplifier, a source electrode connected to the PM4 PMl, PM2, the gate while the drain connected to the gate PM4 and PM3, PM4 of , to form a negative feedback loop, the error amplified voltage signal into a current signal, thereby maintaining the equation (5) and (6) is satisfied.

[0051] 综上,在图2所示带隙基准电压源电路中没有用到误差放大器,因此省去了误差放大器自身的失调电压及噪声对系统的影响,并且节省了功耗和面积;另外,基准电压Vref的输出支路并未如图1所示,由一个支路(PM3支路)单独产生,也在一定程度上避免了电流镜像失陪引起的失调电压的影响,并且节省了面积和功耗。 [0051] In summary, the error amplifier is not used in the bandgap reference voltage source circuit shown in FIG. 2, thereby eliminating the influence of the error amplifier offset voltage and the noise itself to the system, and the power savings and area; Further , the reference voltage Vref output branch is not shown in Figure 1, is generated by a branch (PM3 branch) alone, but also to avoid the influence of the offset voltage caused by the current mirror excuse to some extent, and saves area and power consumption.

[0052] 图2所示带隙基准电压源电路的基准电压Vref随温度变化的Tcm曲线可参见图 [0052] As shown in FIG. 2 the reference voltage Vref bandgap reference voltage source circuit versus temperature curve can be see FIG Tcm

3。 3. 可见,在一般情况下,本发明基准电压Vref的电源电压抑制比、温度系数Tcm和图1所示采用误差放大器及PMOS镜像电流源的常规带隙基准源相近。 Seen, in general, the reference voltage Vref PSRR present invention, a conventional bandgap reference and an error amplifier uses PMOS current mirror shown in FIG. 1 and similar temperature coefficient of Tcm.

[0053] 本说明书中各个实施例采用递进的方式描述,每个实施例重点说明的都是与其他实施例的不同之处,各个实施例之间相同相似部分互相参见即可。 [0053] In the present specification, the various embodiments described in a progressive manner, differences from the embodiment and the other embodiments each of which emphasizes embodiment, the same or similar portions between the various embodiments refer to each other. 对于实施例公开的装置而言,由于其与实施例公开的方法相对应,所以描述的比较简单,相关之处参见方法部分说明即可。 For the disclosed embodiment of the apparatus embodiment, since it corresponds to the method disclosed embodiments, the description is relatively simple, see Methods of the correlation can be described.

[0054] 对所公开的实施例的上述说明,使本领域专业技术人员能够实现或使用本发明。 [0054] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. 对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的,本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下,在其它实施例中实现。 Various modifications to these professionals skilled in the art of the present embodiments will be apparent, and the generic principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. 因此,本发明将不会被限制于本文所示的这些实施例,而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。 Accordingly, the present invention will not be limited to the embodiments shown herein but is to be accorded herein consistent with the principles and novel features disclosed widest scope.

Claims (2)

  1. 1.一种带隙基准电压源电路,其特征在于,包括第一PMOS管、第二PMOS管、第三PMOS管、第四PMOS管、第一NPN型三极管、第二NPN型三极管、第一电阻和第二电阻;其中: 所述第一PMOS管和第二PMOS管的源极和衬底接入电源电压; 所述第一PMOS管的栅极和第二PMOS管的栅极同时连接至所述第四PMOS管的源极及所述第二PMOS管的漏极; 所述第一PMOS管的漏极连接至所述第三PMOS管的源极; 所述第三PMOS管的衬底和第四PMOS管的衬底接入电源电压; 所述第三PMOS管的栅极和第四PMOS管的栅极同时连接至所述第二NPN型三极管的集电极及所述第四PMOS管的漏极; 所述第三PMOS管的漏极通过所述第二电阻连接至所述第一NPN三极管的集电极; 所述第一NPN型三极管的基极和第二NPN型三极管的基极连接至所述第一NPN型三极管的集电极; 所述第一NPN型三极管的发射极接地; 所述第二NPN型三极 A bandgap voltage reference circuit comprising a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, the fourth PMOS transistor, a first NPN transistor, a second NPN transistor, the first and second resistors; wherein: said source and substrate of the first PMOS transistor and a second PMOS transistor access power supply voltage; a gate of the first PMOS transistor and a second PMOS transistor connected to both the drain-source of the fourth PMOS transistor and the second PMOS transistor; drain of the first PMOS transistor is connected to the source of the third PMOS transistor; the third PMOS transistor substrate a fourth power supply voltage and the substrate access PMOS transistor; the gate of the third PMOS transistor and the fourth PMOS transistor is connected to both the collector of the second NPN transistor and the fourth PMOS transistor a drain; the drain of the third PMOS transistor is connected to the collector of the first NPN transistor through the second resistor; the first NPN transistor and a base of the second NPN transistor base connected to the collector of the first NPN transistor; transmitting the first NPN transistor is grounded; the second NPN triode 的发射极通过所述第一电阻接地; 所述第三PMOS管的漏极作为基准电压输出端。 The emitter is grounded through a first resistor; drain of the third PMOS transistor as a reference voltage output terminal.
  2. 2.根据权利要求1所述的电路,其特征在于:所述第一 PMOS管和第二PMOS管的器件参数相同;所述第三PMOS管和第四PMOS管的器件参数相同;所述第一NPN型三极管和第二NPN三极管的发射极面积比为 The circuit according to claim 1, wherein: the same device parameters of the first PMOS transistor and the second PMOS transistor; the same device parameters of the third PMOS transistor and a fourth PMOS transistor; the first emitter area of ​​NPN transistor and a second NPN transistor ratio
    Figure CN102609027BC00021
    其中,^表示求导数,Vbel表不第一NPN型三极管的基极-发射极结电压,T表不绝对温度,q表不电子电荷量,K表不波尔兹曼常数,R2表示所述第二电阻的电阻值,Rl表示所述第一电阻的电阻值。 Wherein ^ represents the derivative, Vbel table is not a first NPN transistor base - emitter junction voltage, T the absolute temperature of the table is not, q the electron charge table does not amount, K table is not the Boltzmann constant group, R2 represents a resistance of the second resistor, Rl represents the resistance value of the first resistor.
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US5083079A (en) 1989-05-09 1992-01-21 Advanced Micro Devices, Inc. Current regulator, threshold voltage generator
US5155394A (en) 1991-02-12 1992-10-13 National Semiconductor Corporation Bias distribution circuit and method using FET and bipolar
CN102033564A (en) 2009-09-25 2011-04-27 精工电子有限公司 Reference voltage circuit
CN102200797A (en) 2010-03-23 2011-09-28 精工电子有限公司 Reference voltage circuit
CN202502430U (en) 2012-03-29 2012-10-24 北京经纬恒润科技有限公司 Bandgap reference voltage source circuit

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5083079A (en) 1989-05-09 1992-01-21 Advanced Micro Devices, Inc. Current regulator, threshold voltage generator
US5155394A (en) 1991-02-12 1992-10-13 National Semiconductor Corporation Bias distribution circuit and method using FET and bipolar
CN102033564A (en) 2009-09-25 2011-04-27 精工电子有限公司 Reference voltage circuit
CN102200797A (en) 2010-03-23 2011-09-28 精工电子有限公司 Reference voltage circuit
CN202502430U (en) 2012-03-29 2012-10-24 北京经纬恒润科技有限公司 Bandgap reference voltage source circuit

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