CN203838588U - Self-biasing band-gap reference source - Google Patents
Self-biasing band-gap reference source Download PDFInfo
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- CN203838588U CN203838588U CN201420123319.9U CN201420123319U CN203838588U CN 203838588 U CN203838588 U CN 203838588U CN 201420123319 U CN201420123319 U CN 201420123319U CN 203838588 U CN203838588 U CN 203838588U
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Abstract
The utility model relates to a self-biasing band-gap reference source. A resistor R3 is connected in series in a current channel of an NMOS transistor M1, one end of the resistor R3 is connected with a drain electrode of an NMOS transistor M3 and a grid electrode of the NMOS transistor M1 and a grid electrode of an NMOS transistor M2, and the other end of the resistor R3 is connected with a drain electrode of a PMOS transistor M5 and a grid electrode of the NMOS transistor M3 and a grid electrode of an NMOS transistor M4. A resistor R4 is connected in series in a current channel of the NMOS transistor M2, one end of the resistor R4 is connected with a drain electrode of the NMOS transistor M4 and a grid electrode of a PMOS transistor M5 and a grid electrode of a PMOS transistor M6. The other end of the resistor R4 is connected with a drain electrode of the OMOS transistor M6 and connected with a grid electrode of a PMOS transistor M7 and a grid electrode of a PMOS transistor M8. The self-biasing band-gap reference source is insensitive to power supply voltage, high in starting speed and low in power consumption and temperature coefficient and has a high power supply rejection ratio.
Description
Technical field
The utility model relates to a kind of improvement of band gap reference, refers in particular to that a kind of, toggle speed insensitive to supply voltage is fast, low-power consumption low-temperature coefficient and have the automatic biasing band gap reference of high PSRR.
Background technology
Band gap reference is widely used in the integrated circuit such as various simulations, digital-to-analogue mixed signal and power management, and along with the development of integrated circuit industry, SOC (system on a chip) will become the main flow of integrated circuit (IC) design from now on.A typical SOC (system on a chip) comprises the multiple Digital and analog module of application processor module, digital signal processor module, memory cell module, modulus and D/A converter module, voltage reference source module and Peripheral Interface module etc., and chip internal adopts multiple feed to lower power consumption.For traditional band-gap reference source circuit, under low supply voltage, have two obvious factors restricting the realization of circuit: the one, the output of band gap reference is approximately 1.2V, has exceeded the scope of supply voltage; Another is that the input common-mode range of the operational amplifier used in reference source circuit is restricted.These two restraining factors can be respectively method by current-mode and electric resistance partial pressure solve.But what these reference source circuits were used is Bipolar or BiCMOS technique, cost is higher.For this reason, we researched and developed that a kind of, toggle speed insensitive to supply voltage is fast, low-power consumption low-temperature coefficient and there is the automatic biasing band gap reference of high PSRR.
Utility model content
The utility model object be in order to overcome the deficiencies in the prior art, provide that a kind of, toggle speed insensitive to supply voltage is fast, low-power consumption low-temperature coefficient and there is the automatic biasing band gap reference of high PSRR.
For achieving the above object, the technical solution adopted in the utility model is: automatic biasing band gap reference, comprises reference circuit; Described reference circuit, comprises the first common-source common-gate current mirror being comprised of nmos pass transistor M1, M2, M3, M4 and comprises the second common-source common-gate current mirror being comprised of PMOS transistor M5, M6, M7, M8; Resistance in series R3 in the current channel of described nmos pass transistor M1, one end of described resistance R 3 is connected with the drain electrode of nmos pass transistor M3, and be connected with the grid of nmos pass transistor M1, M2, gate bias voltage is provided to nmos pass transistor M1, M2, the other end of resistance R 3 is connected with the drain electrode of PMOS transistor M5, and be connected with the grid of nmos pass transistor M3, M4, gate bias voltage be provided to nmos pass transistor M3, M4; Resistance in series R4 in the current channel of nmos pass transistor M2, one end of described resistance R 4 is connected with the drain electrode of nmos pass transistor M4, and be connected with the grid of PMOS transistor M5, M6, gate bias voltage is provided to PMOS transistor M5, M6, the other end of resistance R 4 is connected with the drain electrode of PMOS transistor M6, and be connected with the grid of PMOS transistor M7, M8, gate bias voltage be provided to PMOS transistor M7, M8.
Preferably, described automatic biasing band gap reference, also comprises start-up circuit, and described start-up circuit comprises transistor M11-M17; Described transistor M11, M12 are in parallel; Described transistor M11, M16 series connection; Described transistor M13, M14, M15, M17 series connection, and in parallel with transistor M11; The grid of described transistor M13, M14 is connected, and is connected with the drain electrode of transistor M13, M14; The grid of described transistor M15, M16 is connected, and is connected with the drain electrode of transistor M15, M17; The grid of described transistor M11, M12 is connected, and is connected with the drain electrode of transistor M11, M16; A drain electrode of described transistor M12 is connected with the grid of resistance R 3 and transistor M3, meets supply voltage Vdd together with another drain electrode draining with transistor M11, M12; The drain electrode of described transistor M16, M17 is ground connection respectively; The grid of described transistor M17 is connected with output voltage V REF end.
Due to the utilization of technique scheme, the utility model compared with prior art has following advantages:
Automatic biasing band gap reference described in the utility model, the common-source common-gate current mirror structure of use automatic biasing, can avoid causing due to the channel length modulation of MOS device the decline of Power Supply Rejection Ratio.The utility model has adopted low-voltage common-source common-gate current mirror, the first common-source common-gate current mirror being formed by nmos pass transistor M1, M2, M3, M4 respectively and the second common-source common-gate current mirror being formed by PMOS transistor M5, M6, M7, M8, grid voltage for fear of nmos pass transistor M3, M4 and PMOS transistor M5, M6 is used extra bias voltage, in circuit, series connection enters resistance R 3, R4 for it provides offset gate voltage, maintains all MOS transistor and is all operated in saturated mode; The utility model is insensitive to supply voltage, toggle speed is fast, low-power consumption low-temperature coefficient and have high PSRR.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, technical solutions of the utility model are described further:
Accompanying drawing 1 is the circuit theory diagrams of automatic biasing band gap reference described in the utility model.
Embodiment
Below in conjunction with drawings and the specific embodiments, the utility model is described in further detail.
Accompanying drawing 1 is automatic biasing band gap reference described in the utility model, comprises reference circuit; Described reference circuit, comprises the first common-source common-gate current mirror, the second common-source common-gate current mirror; Described the first common-source common-gate current mirror, comprises nmos pass transistor M1, nmos pass transistor M2, nmos pass transistor M3, nmos pass transistor M4; Described the second common-source common-gate current mirror, comprises PMOS transistor M5, PMOS transistor M6, PMOS transistor M7, PMOS transistor M8; Resistance in series R3 in the current channel of described nmos pass transistor M1, one end of described resistance R 3 is connected with the drain electrode of nmos pass transistor M3, and be connected with the grid of nmos pass transistor M1, nmos pass transistor M2, gate bias voltage is provided to nmos pass transistor M1, nmos pass transistor M2, the other end of resistance R 3 is connected with the drain electrode of PMOS transistor M5, and be connected with the grid of nmos pass transistor M3, nmos pass transistor M4, gate bias voltage be provided to nmos pass transistor M3, nmos pass transistor M4; Resistance in series R4 in the current channel of nmos pass transistor M2, one end of described resistance R 4 is connected with the drain electrode of nmos pass transistor M4, and be connected with the grid of PMOS transistor M5, PMOS transistor M6, gate bias voltage is provided to PMOS transistor M5, PMOS transistor M6, the other end of resistance R 4 is connected with the drain electrode of PMOS transistor M6, and be connected with the grid of PMOS transistor M7, PMOS transistor M8, gate bias voltage be provided to PMOS transistor M7, PMOS transistor M8.
As shown in Figure 1, in order to obtain the reference source of a zero-temperature coefficient, bipolar transistor Q1, Q2, Q3 are arranged side by side; The base stage of bipolar transistor Q1, collector be ground connection respectively, and emitter connects the drain electrode of nmos pass transistor M1; The base stage of bipolar transistor Q2, collector be ground connection respectively, and emitter connects the drain electrode of nmos pass transistor M1 by resistance R 1; The base stage of bipolar transistor Q3, collector be ground connection respectively, and emitter connects the drain electrode of PMOS transistor M10 by resistance R 2; Described PMOS transistor M10 connects with M11, and PMOS transistor M11 meets supply voltage Vdd; PMOS transistor M10 is connected with the two ends of resistance R 4 respectively with the grid of M11; Bipolar transistor Q2, Q3 are measure-alike, and transistor M1-M8 connects by cascade, and the electric current that flows through bipolar transistor Q1, Q2 is equated.The emitter area of bipolar transistor Q2 is K times of bipolar transistor Q1, and K is greater than 1.The voltage at bipolar transistor Q1 two ends must equal the voltage sum at bipolar transistor Q2 and resistance R 1 two ends, therefore has:
.The resistance of the resistance R 2 of connecting with bipolar transistor Q3 be the resistance R 1 of connecting with bipolar transistor Q2 resistance L doubly, have
.Output voltage is:
, in the time of can making temperature coefficient be zero, now
.For circuit, can break away from degeneracy bias point when the power supply electrifying, add a start-up circuit to guarantee that circuit can normally work.Start-up circuit in accompanying drawing 1, comprises transistor M11-M17, and described transistor M11, M12 are in parallel; Described transistor M11, M16 series connection; Described transistor M13, M14, M15, M17 series connection, and in parallel with transistor M11; The grid of described transistor M13, M14 is connected, and is connected with the drain electrode of transistor M13, M14; The grid of described transistor M15, M16 is connected, and is connected with the drain electrode of transistor M15, M17; The grid of described transistor M11, M12 is connected, and is connected with the drain electrode of transistor M11, M16; A drain electrode of described transistor M12 is connected with the grid of resistance R 3 and transistor M3, meets supply voltage Vdd together with another drain electrode draining with transistor M11, M12; The drain electrode of described transistor M16, M17 is ground connection respectively; The grid of described transistor M17 is connected with output voltage V REF end.The course of work of start-up circuit is summarized as follows: when power supply electrifying starts, PMOS transistor M11, M12 and nmos pass transistor M16 start saturation conduction, PMOS transistor M12 drain electrode is connected with the drain electrode of the PMOS transistor M5 of cascade auto bias circuit, make the drain voltage of PMOS transistor M5 start to rise, make automatic biasing loop depart from degeneracy point; Rising along with the voltage of PMOS transistor M12 drain electrode, after time delay a period of time, output voltage V REF is also rising, output terminal VREF is connected with the grid of nmos pass transistor M17, the grid leak utmost point short circuit of PMOS transistor M13, M14, M15 becomes active pull-up, make so the grid voltage of nmos pass transistor M17 increase, until while being greater than its threshold voltage, nmos pass transistor M17 saturation conduction, nmos pass transistor M16 grid voltage by drop-down be zero level, nmos pass transistor M16 cut-off.Meanwhile, PMOS transistor M11, M12 also depart from duty, and final reference generating circuit enters normal duty.Therefore start-up circuit just just works at first powering on, inoperative when reference circuit is normally worked.
Due to the utilization of technique scheme, the utility model compared with prior art has following advantages:
Automatic biasing band gap reference described in the utility model, the common-source common-gate current mirror structure of use automatic biasing, can avoid causing due to the channel length modulation of MOS device the decline of Power Supply Rejection Ratio.The utility model has adopted low-voltage common-source common-gate current mirror, the first common-source common-gate current mirror being formed by nmos pass transistor M1, M2, M3, M4 respectively and the second common-source common-gate current mirror being formed by PMOS transistor M5, M6, M7, M8, grid voltage for fear of nmos pass transistor M3, M4 and PMOS transistor M5, M6 is used extra bias voltage, in circuit, series connection enters resistance R 3, R4 for it provides offset gate voltage, maintains all MOS transistor and is all operated in saturated mode; The utility model is insensitive to supply voltage, toggle speed is fast, low-power consumption low-temperature coefficient and have high PSRR.
Below be only concrete exemplary applications of the present utility model, protection domain of the present utility model is not constituted any limitation.All employing equivalents or equivalence are replaced and the technical scheme of formation, within all dropping on the utility model rights protection scope.
Claims (2)
1. automatic biasing band gap reference, comprises reference circuit; It is characterized in that: described reference circuit, comprises the first common-source common-gate current mirror being comprised of nmos pass transistor M1, M2, M3, M4 and comprise the second common-source common-gate current mirror being comprised of PMOS transistor M5, M6, M7, M8; Resistance in series R3 in the current channel of described nmos pass transistor M1, one end of described resistance R 3 is connected with the drain electrode of nmos pass transistor M3, and be connected with the grid of nmos pass transistor M1, M2, gate bias voltage is provided to nmos pass transistor M1, M2, the other end of resistance R 3 is connected with the drain electrode of PMOS transistor M5, and be connected with the grid of nmos pass transistor M3, M4, gate bias voltage be provided to nmos pass transistor M3, M4; Resistance in series R4 in the current channel of nmos pass transistor M2, one end of described resistance R 4 is connected with the drain electrode of nmos pass transistor M4, and be connected with the grid of PMOS transistor M5, M6, gate bias voltage is provided to PMOS transistor M5, M6, the other end of resistance R 4 is connected with the drain electrode of PMOS transistor M6, and be connected with the grid of PMOS transistor M7, M8, gate bias voltage be provided to PMOS transistor M7, M8.
2. automatic biasing band gap reference according to claim 1, is characterized in that: also comprise start-up circuit, described start-up circuit, comprises transistor M11-M17; Described transistor M11, M12 are in parallel; Described transistor M11, M16 series connection; Described transistor M13, M14, M15, M17 series connection, and in parallel with transistor M11; The grid of described transistor M13, M14 is connected, and is connected with the drain electrode of transistor M13, M14; The grid of described transistor M15, M16 is connected, and is connected with the drain electrode of transistor M15, M17; The grid of described transistor M11, M12 is connected, and is connected with the drain electrode of transistor M11, M16; A drain electrode of described transistor M12 is connected with the grid of resistance R 3 and transistor M3, meets supply voltage Vdd together with another drain electrode draining with transistor M11, M12; The drain electrode of described transistor M16, M17 is ground connection respectively; The grid of described transistor M17 is connected with output voltage V REF end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420123319.9U CN203838588U (en) | 2014-03-18 | 2014-03-18 | Self-biasing band-gap reference source |
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|---|---|---|---|
| CN201420123319.9U CN203838588U (en) | 2014-03-18 | 2014-03-18 | Self-biasing band-gap reference source |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103901935A (en) * | 2014-03-18 | 2014-07-02 | 苏州市职业大学 | Automatic biasing band-gap reference source |
| CN104820460A (en) * | 2015-04-03 | 2015-08-05 | 深圳市芯联电子科技有限公司 | Bandgap voltage reference source circuit |
| CN105955389A (en) * | 2016-06-23 | 2016-09-21 | 电子科技大学 | Voltage reference source |
| CN107066015A (en) * | 2017-04-19 | 2017-08-18 | 桂林电子科技大学 | A kind of full cascade reference voltage source |
| CN107992158A (en) * | 2017-12-27 | 2018-05-04 | 湖南国科微电子股份有限公司 | A kind of reference current source of second compensation Low Drift Temperature |
| CN108445951A (en) * | 2018-05-15 | 2018-08-24 | 杜泽勇 | A kind of reference voltage generating circuit of high stability |
| CN109634346A (en) * | 2018-12-20 | 2019-04-16 | 上海贝岭股份有限公司 | Band-gap reference voltage circuit |
| CN110888485A (en) * | 2019-10-09 | 2020-03-17 | 芯创智（北京）微电子有限公司 | Self-biased band gap reference circuit |
| CN110932722A (en) * | 2019-12-04 | 2020-03-27 | 芯创智（北京）微电子有限公司 | Capacitance multiplication circuit applied to phase-locked loop filter |
| CN112882524A (en) * | 2019-11-29 | 2021-06-01 | 意法半导体股份有限公司 | Bandgap reference circuit, corresponding device and method |
| CN115357085A (en) * | 2022-08-30 | 2022-11-18 | 广东工业大学 | Self-biased CMOS voltage reference source and method for determining linear sensitivity and power supply rejection ratio |
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2014
- 2014-03-18 CN CN201420123319.9U patent/CN203838588U/en not_active Expired - Fee Related
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103901935A (en) * | 2014-03-18 | 2014-07-02 | 苏州市职业大学 | Automatic biasing band-gap reference source |
| CN104820460B (en) * | 2015-04-03 | 2019-10-01 | 深圳市芯联电子科技有限公司 | A kind of band gap reference voltage source circuit |
| CN104820460A (en) * | 2015-04-03 | 2015-08-05 | 深圳市芯联电子科技有限公司 | Bandgap voltage reference source circuit |
| CN105955389A (en) * | 2016-06-23 | 2016-09-21 | 电子科技大学 | Voltage reference source |
| CN105955389B (en) * | 2016-06-23 | 2017-05-03 | 电子科技大学 | Voltage reference source |
| CN107066015A (en) * | 2017-04-19 | 2017-08-18 | 桂林电子科技大学 | A kind of full cascade reference voltage source |
| CN107992158A (en) * | 2017-12-27 | 2018-05-04 | 湖南国科微电子股份有限公司 | A kind of reference current source of second compensation Low Drift Temperature |
| CN108445951A (en) * | 2018-05-15 | 2018-08-24 | 杜泽勇 | A kind of reference voltage generating circuit of high stability |
| CN109634346A (en) * | 2018-12-20 | 2019-04-16 | 上海贝岭股份有限公司 | Band-gap reference voltage circuit |
| CN110888485A (en) * | 2019-10-09 | 2020-03-17 | 芯创智（北京）微电子有限公司 | Self-biased band gap reference circuit |
| CN110888485B (en) * | 2019-10-09 | 2022-01-18 | 芯创智（北京）微电子有限公司 | Self-biased band gap reference circuit |
| CN112882524A (en) * | 2019-11-29 | 2021-06-01 | 意法半导体股份有限公司 | Bandgap reference circuit, corresponding device and method |
| US11531365B2 (en) | 2019-11-29 | 2022-12-20 | Stmicroelectronics S.R.L. | Bandgap reference circuit, corresponding device and method |
| CN110932722A (en) * | 2019-12-04 | 2020-03-27 | 芯创智（北京）微电子有限公司 | Capacitance multiplication circuit applied to phase-locked loop filter |
| CN115357085A (en) * | 2022-08-30 | 2022-11-18 | 广东工业大学 | Self-biased CMOS voltage reference source and method for determining linear sensitivity and power supply rejection ratio |
| CN115357085B (en) * | 2022-08-30 | 2023-08-08 | 广东工业大学 | Self-bias CMOS voltage reference source and method for determining linear sensitivity and power supply rejection ratio |
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