CN110932722A - Capacitance multiplication circuit applied to phase-locked loop filter - Google Patents
Capacitance multiplication circuit applied to phase-locked loop filter Download PDFInfo
- Publication number
- CN110932722A CN110932722A CN201911226084.XA CN201911226084A CN110932722A CN 110932722 A CN110932722 A CN 110932722A CN 201911226084 A CN201911226084 A CN 201911226084A CN 110932722 A CN110932722 A CN 110932722A
- Authority
- CN
- China
- Prior art keywords
- transistor
- capacitance
- phase
- circuit
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 54
- 230000005669 field effect Effects 0.000 claims abstract description 13
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 8
- 230000003321 amplification Effects 0.000 abstract description 3
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 3
- 230000009467 reduction Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
Abstract
The invention provides a capacitance multiplication circuit applied to a phase-locked loop filter, which comprises a capacitor C1, an N-type field effect tube current mirror circuit, a P-type field effect tube current mirror circuit and a bias circuit, wherein the N-type field effect tube current mirror circuit is connected with the bias circuit; the circuit can obtain equivalent capacitance characteristics which are several times larger than those of small capacitors by only needing small on-chip capacitors and matching with a certain circuit structure, the capacitance multiplication technology adopts a current mirror geometric amplification technology to realize a capacitance-reactance characteristic curve of the equivalent capacitors, and although the capacitance-reactance characteristic curve has some deviation with ideal large capacitors at low-frequency and high-frequency ends, the capacitance-reactance characteristic curve does not influence the frequency range concerned by a phase-locked loop in the design of a phase-locked loop filter, and the capacitance-reactance characteristic of the phase-locked loop is completely consistent with that of the ideal capacitors. The phase-locked loop circuit applying the capacitance multiplication technology has basically no difference with a phase-locked loop circuit adopting an ideal capacitor in function and performance, but brings about the large-range reduction of the area of a loop filter chip, the area can be reduced by more than 80% under the limit condition, and the chip cost is greatly reduced.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a capacitance multiplying circuit applied to a phase-locked loop filter.
Background
A Phase Lock Loop (PLL) is an automatic Phase control system, and is a basic component widely used in modern electronic systems. The basic function of the method is to generate an oscillating signal in a loop, the frequency of the oscillating signal is controlled by the action of a controlled voltage, when the loop is locked, the output frequency of the oscillating signal is completely equal to the frequency of an input signal, the phase difference of the two signals is kept constant, and the signal tracking without frequency error is realized. The phase-locked loop has wide application, can be used for frequency tracking and phase tracking, and can also generate various high-frequency clock signals to drive a system to work.
The phase-locked loop is generally composed of a Phase Detector (PD), a filter (LPF), a Voltage Controlled Oscillator (VCO) and a feedback frequency Divider (Divider)4, as shown in fig. 1, with the continuous development of integrated circuit manufacturing process and design technology, more and more systems are applied to integrate a phase-locked loop on a chip to replace a phase-locked system constructed by board-level discrete devices, which not only greatly saves the board-level space of the system, but also reduces the production cost. Although the on-chip integrated pll saves space for the board-level system, the chip area is inevitably increased, especially for the loop filter of the pll system, the conventional second-order loop filter is shown in fig. 2, and the integral capacitor C1 is typically several hundred pF or larger, and the occupied area is considerable, which increases the manufacturing cost of the chip.
Disclosure of Invention
In view of the drawbacks of the prior art, an object of the present invention is to provide a capacitance multiplier circuit applied to a phase-locked loop filter, which can effectively reduce the chip area of the loop filter while ensuring a relatively large capacitance characteristic.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a capacitance multiplication circuit applied to a phase-locked loop filter comprises a capacitor C1, an N-type field effect transistor current mirror circuit, a P-type field effect transistor current mirror circuit and a bias circuit, wherein the N-type field effect transistor current mirror circuit comprises NMOS transistors M1, M2, M3 and M4, the drain electrode of the M2 transistor is connected with one end of a capacitor C1 to form a connection node VB, the source electrode of the M2 transistor is connected with the drain electrode of the M1 transistor, the gate electrode of the M2 transistor is connected with the gate electrode of the M4 transistor, the gate electrode of the M1 transistor is connected with one end of the capacitor C1, the source electrode of the M1 transistor is connected with the source electrode of the M3 transistor, the drain electrode of the M3 transistor is connected with the source electrode of the M4 transistor, and the drain electrode of the M4 transistor is connected with the other end of a capacitor C1 to form a connection node VA; the P-type field effect transistor current mirror circuit comprises PMOS transistors P1, P2, P3 and P4, wherein the drain electrode of the P1 transistor is connected with a connection node VB, the source electrode of the P1 transistor is connected with the drain electrode of the P2 transistor, the source electrode of the P2 transistor is connected with the source electrode of the P4 transistor, the drain electrode of the P4 transistor is connected with the source electrode of the P3 transistor, the drain electrode of the P3 transistor is connected with a connection node VA, and the grid electrodes of the P1 transistor, the P2 transistor, the P3 transistor and the P4 transistor are connected with the bias circuit to obtain a current source provided by the bias circuit.
Further, the bias circuit comprises a PMOS tube P5, a P6, a resistor R1 and a current source I1, wherein a source of the P6 is connected with a source of the P4, a drain of the P6 is connected with a source of the P5, a gate of the P6 is connected with one end of the resistor R1, one end of the P5 is connected with one end of the resistor R1, gates of the P1, the P3 and the P5 are connected with the other end of the resistor R1, and the resistor R1 is connected with the current source I1 in series.
Further, the capacitance multiplication circuit further comprises capacitors CP1 and CP2, wherein one end of the capacitor CP1 is connected to the connection node VB, and the other end thereof is grounded; the capacitor CP2 has one end connected to the connection node VA and the other end grounded.
Further, the capacitor C1 is a metal-stacked MOM capacitor structure or a MOS capacitor structure integrated on a chip.
Further, the gate of the M2 tube is connected to an externally supplied bias voltage VBN.
Compared with the traditional technical scheme, the technical scheme has the beneficial effects that: the capacitance multiplication technology adopts the current mirror geometric magnification technology to realize the capacitance reactance characteristic curve of the equivalent capacitor, although the capacitance multiplication technology has some deviation with the ideal large capacitor at the low frequency end and the high frequency end, the frequency range concerned by the phase-locked loop is not influenced, and the capacitance reactance characteristic is completely consistent with the ideal capacitor; the phase-locked loop circuit applying the capacitance multiplication technology has basically no difference with a phase-locked loop circuit adopting an ideal capacitor in function and performance, but brings about the large-range reduction of the area of a loop filter chip, the area can be reduced by more than 80% under the limit condition, and the chip cost is greatly reduced.
Drawings
Fig. 1 is a schematic diagram of a conventional pll circuit.
Fig. 2 is a schematic diagram of a conventional pll filter circuit.
Fig. 3 is a schematic diagram of a capacitance multiplier circuit applied to a loop filter according to the present invention.
Fig. 4 is a schematic diagram of the operation principle of the capacitance multiplying circuit in the present invention.
FIG. 5 is a diagram illustrating a comparison between the characteristics of the capacitance multiplier circuit and the ideal capacitance.
Detailed Description
The invention is described in further detail below with reference to the drawings and the detailed description.
The invention aims at the problems that the occupied area of a capacitor on a loop filter of a traditional phase-locked loop system is quite large and the manufacturing cost of a chip is increased, and further provides a capacitor multiplying circuit applied to the phase-locked loop filter.
Referring to fig. 3 to 4, the present embodiment provides a capacitance multiplier circuit applied to a phase-locked loop filter, the capacitance multiplier circuit includes a capacitor C1, an N-type fet current mirror circuit, a P-type fet current mirror circuit, and a bias circuit, wherein the N-type fet current mirror circuit includes an NMOS transistor M1, M2, M3, and M4, a drain of the M2 transistor is connected to one end of a capacitor C1 and forms a connection node VB, a source of the M2 transistor is connected to a drain of the M1 transistor, a gate of the M2 transistor is connected to a gate of the M4 transistor, a gate of the M1 transistor is connected to one end of the capacitor C1, a source of the M1 transistor is connected to a source of the M3 transistor, a drain of the M3 transistor is connected to a source of the M4, and a drain of the M4 transistor is connected to the other end of the capacitor C1 and forms a connection node VA; the P-type field effect transistor current mirror circuit comprises PMOS transistors P1, P2, P3 and P4, wherein the drain electrode of a P1 transistor is connected with a connection node VB, the source electrode of a P1 transistor is connected with the drain electrode of a P2 transistor, the source electrode of a P2 transistor is connected with the source electrode of a P4 transistor, the drain electrode of a P4 transistor is connected with the source electrode of a P3 transistor, the drain electrode of a P3 transistor is connected with a connection node VA, and the grid electrodes of the P1 transistor, the P2 transistor, the P3 transistor and the P4 transistor are connected with a bias circuit to obtain a current source provided by the bias circuit.
The bias circuit comprises a PMOS (P-channel metal oxide semiconductor) tube P5, a P6 tube, a resistor R1 and a current source I1, wherein the source electrode of the P6 tube is connected with the source electrode of the P4 tube, the drain electrode of the P6 tube is connected with the source electrode of the P5 tube, the grid electrode of the P6 tube is connected with one end of a resistor R1, one end of the P5 tube is connected with one end of a resistor R1, the grid electrodes of the P1 tube, the P3 tube and the P5 tube are connected with the other end of a resistor R1, and the resistor R1 is connected with the current source I1 in.
The capacitance multiplying circuit further comprises capacitors CP1 and CP2, wherein one end of the capacitor CP1 is connected to the connection node VB, and the other end thereof is grounded; capacitor CP2 is connected to connection node VA at one end and to ground at the other end.
The capacitor CI can be a metal laminated MOM capacitor integrated on a chip or an MOS capacitor, the capacitance value is generally small, generally about dozens of pF, the capacitor does not occupy too much chip area, one end of the capacitor is connected with the VA, and the other end of the capacitor is connected with the input VB of the N-type field effect transistor current mirror circuit. The gate of the N-type fet M1 is connected to VB, and forms a cascode current mirror main stage with the M2 tube, the gate of M2 needs an external bias to provide a bias voltage VBN, M3, M4 is a mirror current source of M1, M2, and the current mirror ratio is 1: n, wherein N is an integer greater than 1.
A bias circuit composed of P5, P6, R1 and I1 provides bias for the whole capacitor configuration circuit, a self-biased cascode current mirror is composed of P5, P6 and R1, accurate current sources are provided for two branches of the capacitor multiplication circuit, the current ratios of the two branches are respectively P2 and P1 branches and P4 and P3 branches, and the current ratios of the two branches are the same as those of M1, M2, M3 and M4. The cascode current mirror circuit can provide high-precision current matching, and can also provide high impedance points at nodes VA and VB, so that the adverse effect of the nonideal effect of the current mirror on capacitance multiplication is reduced.
The capacitors CP1 and CP2 are parasitic capacitors introduced by the capacitance multiplier circuit on VA and VB, and theoretically, CP2 is far smaller than CP1, and CP1 is far smaller than CI. As shown in fig. 4, an ideal voltage source can be equivalent to the capacitance input node VA, an admittance calculation expression corresponding to the node can be obtained by performing operation reasoning through a small signal model, and after certain simplification, the admittance calculation expression basically consists of three parts, namely VA point admittance, N +1 times CI admittance, and CP2 admittance, wherein the N +1 times CI admittance is consistent with the ideal N +1 times capacitance admittance for amplification, and the capacitance amplification effect is realized.
The capacitive reactance response characteristic curve is shown in fig. 5, the characteristic curve completely coincides with the characteristic curve of an ideal capacitor in a middle frequency range, low-frequency impedance is introduced by the output impedance of a current source in a low frequency range, and a zero point pair is formed at a high frequency by non-ideal parasitic capacitors of CP2 and CP1, so that the characteristic curve has a certain offset, but the application of the capacitance multiplying circuit in a phase-locked loop filter is not influenced. For example, under the conditions of CI 10pF and N11, the equivalent capacitance is 120pF, and the multiplied capacitance is substituted into the phase-locked loop to perform loop analysis, so that the loop characteristic parameter almost the same as that of the ideal capacitance 120pF can be obtained without affecting the stability of the phase-locked loop.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such modifications and variations.
Claims (5)
1. A capacitance multiplying circuit applied to a phase-locked loop filter is characterized in that: the capacitance multiplication circuit comprises a capacitor C1, an N-type field effect transistor current mirror circuit, a P-type field effect transistor current mirror circuit and a bias circuit, wherein the N-type field effect transistor current mirror circuit comprises NMOS transistors M1, M2, M3 and M4, the drain of the M2 transistor is connected with one end of a capacitor C1 to form a connection node VB, the source of the M2 transistor is connected with the drain of the M1 transistor, the gate of the M2 transistor is connected with the gate of the M4 transistor, the gate of the M1 transistor is connected with one end of the capacitor C1, the source of the M1 transistor is connected with the source of the M3, the drain of the M3 transistor is connected with the source of the M4 transistor, and the drain of the M4 transistor is connected with the other end of the capacitor C1 to form a connection node VA; the P-type field effect transistor current mirror circuit comprises PMOS transistors P1, P2, P3 and P4, wherein the drain electrode of the P1 transistor is connected with a connection node VB, the source electrode of the P1 transistor is connected with the drain electrode of the P2 transistor, the source electrode of the P2 transistor is connected with the source electrode of the P4 transistor, the drain electrode of the P4 transistor is connected with the source electrode of the P3 transistor, the drain electrode of the P3 transistor is connected with a connection node VA, and the grid electrodes of the P1 transistor, the P2 transistor, the P3 transistor and the P4 transistor are connected with the bias circuit to obtain a current source provided by the bias circuit.
2. The capacitance multiplying circuit applied to the phase-locked loop filter as claimed in claim 1, wherein: the bias circuit comprises a PMOS (P-channel metal oxide semiconductor) tube P5, a P6, a resistor R1 and a current source I1, wherein the source of the P6 is connected with the source of the P4, the drain of the P6 is connected with the source of the P5, the gate of the P6 is connected with one end of the resistor R1, one end of the P5 is connected with one end of the resistor R1, the gates of the P1, the P3 and the P5 are connected with the other end of the resistor R1, and the resistor R1 is connected with the current source I1 in series.
3. A capacitance multiplying circuit applied to a phase-locked loop filter according to claim 1 or 2, wherein: the capacitance multiplying circuit further comprises capacitors CP1 and CP2, wherein one end of the capacitor CP1 is connected with the connection node VB, and the other end of the capacitor CP1 is grounded; the capacitor CP2 has one end connected to the connection node VA and the other end grounded.
4. The capacitance multiplying circuit applied to the phase-locked loop filter as claimed in claim 1, wherein: the capacitor C1 is a metal-stacked MOM capacitor structure or a MOS capacitor structure integrated on a chip.
5. A capacitance multiplying circuit applied to a phase-locked loop filter according to claim 1 or 2, wherein: the gate of the M2 transistor is connected to an externally supplied bias voltage VBN.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911226084.XA CN110932722A (en) | 2019-12-04 | 2019-12-04 | Capacitance multiplication circuit applied to phase-locked loop filter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911226084.XA CN110932722A (en) | 2019-12-04 | 2019-12-04 | Capacitance multiplication circuit applied to phase-locked loop filter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110932722A true CN110932722A (en) | 2020-03-27 |
Family
ID=69857750
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911226084.XA Pending CN110932722A (en) | 2019-12-04 | 2019-12-04 | Capacitance multiplication circuit applied to phase-locked loop filter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110932722A (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1607726A (en) * | 2003-09-15 | 2005-04-20 | 三星电子株式会社 | Capacitance multiplier |
| CN1988378A (en) * | 2005-12-20 | 2007-06-27 | Bcd半导体制造有限公司 | Method and its circuit for realizing multiplication capacitor |
| CN101326721A (en) * | 2005-12-12 | 2008-12-17 | 吉林克斯公司 | Method and apparatus for capacitance multiplication within a phase locked loop |
| CN202306379U (en) * | 2011-11-02 | 2012-07-04 | 国民技术股份有限公司 | Current mirroring circuit |
| CN202535312U (en) * | 2011-12-31 | 2012-11-14 | 彩优微电子(昆山)有限公司 | Small signal capacitance amplifying circuit device |
| CN103580636A (en) * | 2012-08-06 | 2014-02-12 | 美国博通公司 | Common mode termination with C-multiplier circuit |
| CN203838588U (en) * | 2014-03-18 | 2014-09-17 | 苏州市职业大学 | Self-biasing band-gap reference source |
| CN107565928A (en) * | 2017-08-10 | 2018-01-09 | 宁波大学 | A kind of capacity multiplier of high multiplication constant |
| CN107863945A (en) * | 2017-09-30 | 2018-03-30 | 苏州威发半导体有限公司 | A kind of capacitance multiplication RC network |
-
2019
- 2019-12-04 CN CN201911226084.XA patent/CN110932722A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1607726A (en) * | 2003-09-15 | 2005-04-20 | 三星电子株式会社 | Capacitance multiplier |
| CN101326721A (en) * | 2005-12-12 | 2008-12-17 | 吉林克斯公司 | Method and apparatus for capacitance multiplication within a phase locked loop |
| CN1988378A (en) * | 2005-12-20 | 2007-06-27 | Bcd半导体制造有限公司 | Method and its circuit for realizing multiplication capacitor |
| CN202306379U (en) * | 2011-11-02 | 2012-07-04 | 国民技术股份有限公司 | Current mirroring circuit |
| CN202535312U (en) * | 2011-12-31 | 2012-11-14 | 彩优微电子(昆山)有限公司 | Small signal capacitance amplifying circuit device |
| CN103580636A (en) * | 2012-08-06 | 2014-02-12 | 美国博通公司 | Common mode termination with C-multiplier circuit |
| CN203838588U (en) * | 2014-03-18 | 2014-09-17 | 苏州市职业大学 | Self-biasing band-gap reference source |
| CN107565928A (en) * | 2017-08-10 | 2018-01-09 | 宁波大学 | A kind of capacity multiplier of high multiplication constant |
| CN107863945A (en) * | 2017-09-30 | 2018-03-30 | 苏州威发半导体有限公司 | A kind of capacitance multiplication RC network |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7400183B1 (en) | Voltage controlled oscillator delay cell and method | |
| US8179175B2 (en) | Reliable charge pump circuit | |
| JPH04348614A (en) | Electrically controllable oscillation circuit | |
| US9070510B2 (en) | Frequency tuning and step control of a digitally controlled oscillator | |
| CN108199687B (en) | Transconductance linearization broadband LC type voltage-controlled oscillator and adjustable capacitor array circuit | |
| US10396806B1 (en) | Voltage regulator based loop filter for loop circuit and loop filtering method | |
| CN109995363B (en) | Annular voltage-controlled oscillator with self-bias structure | |
| CN103346784A (en) | Matching type charge pump circuit for phase-locked loop | |
| CN106505948B (en) | High-resolution digital controlled oscillator based on tail capacitor tuning structure | |
| CN109921633B (en) | Charge pump circuit with wide dynamic range and low mismatch characteristic | |
| US9287825B2 (en) | Inductive-capacitive (LC) voltage controlled oscillator (VCO) having tuning range controlled by a digital-to-analog converter (DAC) with programmable tail current | |
| CN112242841A (en) | Phase-locked loop circuit with high power supply noise rejection ratio | |
| KR20190062116A (en) | A type of ultra low voltage two stage ring voltage controlled oscillator for chip circuits | |
| CN110932722A (en) | Capacitance multiplication circuit applied to phase-locked loop filter | |
| CN112953396B (en) | Variable-capacitance voltage-controlled oscillator and integrated circuit | |
| CN116317954A (en) | Voltage controlled oscillator with wide tuning range and low phase noise | |
| US11528022B2 (en) | Leakage-current compensation | |
| CN109936362B (en) | Charge pump applied to frequency synthesizer | |
| CN107800387B (en) | Amplitude control circuit and inductance-capacitance voltage-controlled oscillator circuit | |
| CN114301452A (en) | Phase-locked loop circuit, control method, charge pump and chip | |
| US8493155B2 (en) | Multiband voltage controlled oscillator without switched capacitor | |
| CN113395042A (en) | High-frequency low-power-consumption low-jitter voltage-controlled oscillator | |
| Hao et al. | A Low-Noise High-Robust LC-VCO Based on 22nm FD-SOI Process | |
| CN108390647B (en) | LC-VCO circuit and variable capacitance circuit | |
| US20190020330A1 (en) | Variable capacitance circuit, oscillator circuit, and method of controlling variable capacitance circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200327 |
|
| RJ01 | Rejection of invention patent application after publication |