CN109936362B

CN109936362B - Charge pump applied to frequency synthesizer

Info

Publication number: CN109936362B
Application number: CN201910145084.0A
Authority: CN
Inventors: 吴建辉; 何凯; 陈超; 李红
Original assignee: Southeast University
Current assignee: Southeast University
Priority date: 2019-02-27
Filing date: 2019-02-27
Publication date: 2023-01-17
Anticipated expiration: 2039-02-27
Also published as: CN109936362A

Abstract

The invention discloses a charge pump applied to a frequency synthesizer, which comprises a charge-discharge current branch circuit and an output impedance multiplication circuit, wherein the charge-discharge current branch circuit is connected with the output impedance multiplication circuit; the charging and discharging current branch circuit consists of a complementary CMOS switch, a unit negative feedback loop consisting of a rail-to-rail input and output amplifier and a current source and is used for charging and discharging an output node and eliminating a clock feed-through effect and a charge sharing effect; the output impedance multiplication circuit is formed by a folding type cascade structure and is used for improving the output impedance of the charge pump. The output impedance multiplication circuit comprises a reference current source, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a sixteenth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a ninth PMOS tube, a tenth PMOS tube and a fifteenth PMOS tube; the invention is suitable for the drain switch charge pump with good matching characteristic under low voltage, improves the matching degree of charge and discharge current, improves the phase noise of the frequency synthesizer and improves the output impedance of the charge pump.

Description

Charge pump applied to frequency synthesizer

Technical Field

The invention relates to a charge pump applied to a frequency synthesizer, and belongs to the technical field of phase-locked loops.

Background

The frequency synthesizer is a technology for realizing frequency and phase synchronization by using a feedback control principle, and generally comprises five components, namely a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator and a frequency divider, wherein the charge pump is used as an important component of the frequency synthesizer and is a popular subject of analog integrated circuit research. The performance of the conventional charge pump shown in fig. 1 is affected by non-ideal factors such as current mismatch, charge sharing, and clock feedthrough, and the current mismatch of the charge pump may cause the output of the frequency synthesizer to generate spurious, thereby restricting the noise characteristics of the frequency synthesizer.

The charge pump is actually a switching current source, and the switching signal from the phase frequency detector controls the charge pump to charge or discharge a loop filter at the subsequent stage, so that the control voltage of the oscillator is changed, the frequency of the output signal of the oscillator is changed, the frequency and the phase of the reference signal and the output signal of the frequency synthesizer are synchronized, and the locked state is achieved. The drain-side switch charge pump generally adopts a current source formed by a single MOS transistor and is connected in series with a single PMOS transistor switch or NMOS transistor switch. Although the output impedance of the current source can be increased by cascading MOS transistors, this approach is not practical due to supply voltage limitations and output swing requirements. In addition, a single MOS tube is used as a switch, so that threshold loss and large direct current on-resistance exist, and a serious clock feed-through effect can be generated at an output end, so that output current fluctuates. The MOS tube switch is changed from closed to conductive, which also causes the charge distribution problem between the output node and the current source drain terminal, resulting in the change of the output voltage, namely the charge sharing effect.

Disclosure of Invention

The invention aims to overcome the defects of the prior art, provides a charge pump applied to a frequency synthesizer, and solves the problem that when the output voltage of the charge pump is changed greatly, the linearity of the charge pump is reduced due to the mismatching of currents caused by overlarge change of charging and discharging currents, and the stray performance of the frequency synthesizer is poor.

The invention specifically adopts the following technical scheme to solve the technical problems:

a charge pump applied to a frequency synthesizer comprises a charge-discharge current branch circuit and an output impedance multiplication circuit; the charge-discharge current branch circuit consists of a complementary CMOS switch, a unit negative feedback loop consisting of a rail-to-rail input and output amplifier and a current source and is used for charging and discharging an output node and eliminating a clock feed-through effect and a charge sharing effect; the output impedance multiplication circuit is formed by a folding type cascade structure and is used for improving the output impedance of the charge pump.

Further, as a preferred technical solution of the present invention: the charge-discharge current branch circuit comprises a first rail-to-rail input-output amplifier, a sixth NMOS transistor, a ninth NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a fifth PMOS transistor, an eighth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor and a fourteenth PMOS transistor; the high-level signal UP is respectively connected with the grids of an eleventh PMOS tube and a fifteenth NMOS tube, the low-level signal NUP is respectively connected with the grids of a twelfth PMOS tube and a fourteenth NMOS tube, the high-level signal DOWN is respectively connected with the grids of a thirteenth PMOS tube and a thirteenth NMOS tube, and the low-level signal NDOWN is connected with the grids of the fourteenth PMOS tube and the twelfth NMOS tube; a source electrode of the eleventh PMOS tube is connected with a source electrode of the fourteenth NMOS tube and then is connected to a drain electrode of the eighth PMOS tube, and a drain electrode of the eleventh PMOS tube is connected with a drain electrode of the fourteenth NMOS tube and then is connected to an output end of the first rail-to-rail input/output amplifier; the source electrode of the twelfth PMOS tube is connected with the source electrode of the fifteenth NMOS tube and then connected to the drain electrode of the eighth PMOS tube, and the drain electrode of the twelfth PMOS tube is connected with the drain electrode of the fifteenth NMOS tube and then connected to the positive input end of the first rail-to-rail input-output amplifier; the source electrode of the thirteenth PMOS tube is connected with the source electrode of the twelfth NMOS tube and then connected to the output end of the first rail-to-rail input/output amplifier, and the drain electrode of the thirteenth PMOS tube is connected with the drain electrode of the twelfth NMOS tube and then connected to the drain electrode of the ninth NMOS tube; a source electrode of the fourteenth PMOS tube is connected with a source electrode of the thirteenth NMOS tube and then connected to the positive input end of the first rail-to-rail input/output amplifier, and a drain electrode of the fourteenth PMOS tube is connected with a drain electrode of the thirteenth NMOS tube and then connected to a drain electrode of the ninth NMOS tube; the output end of the first rail-to-rail input/output amplifier is connected with the negative input end of the first rail-to-rail input/output amplifier, and the positive input end of the first rail-to-rail input/output amplifier is connected with the output end OUT of the charge pump; the grid electrode of the ninth NMOS tube is connected with the output impedance multiplication circuit, and the source electrode of the ninth NMOS tube is connected with the drain electrode of the sixth NMOS tube; the grid electrode of the sixth NMOS tube is connected with the output impedance multiplication circuit, and the source electrode of the sixth NMOS tube is grounded; the grid electrode of the eighth PMOS tube is connected with the output impedance multiplication circuit, and the source electrode of the eighth PMOS tube is connected with the drain electrode of the fifth PMOS tube; the grid electrode of the fifth PMOS tube is connected with the output impedance multiplication circuit, and the source electrode of the fifth PMOS tube is connected with the power supply.

Further, as a preferred technical solution of the present invention: the output impedance multiplication circuit comprises a reference current, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a sixteenth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor and a fifteenth PMOS transistor; the reference current is connected with the drain electrode of the first NMOS tube, the drain electrode of the first NMOS tube is connected with the grid electrode of the first NMOS tube, and the source electrodes of the first NMOS tube, the second NMOS tube and the fifth NMOS tube are grounded after the grid electrodes of the first NMOS tube, the second NMOS tube and the fifth NMOS tube are connected; the source electrode of the seventh NMOS tube is grounded, the grid electrode of the seventh NMOS tube is connected with the grid electrode of the eighth NMOS tube and the grid electrode of the tenth NMOS tube respectively, and the drain electrode of the seventh NMOS tube is connected with the source electrode of the tenth NMOS tube; the drain electrode of the eighth NMOS tube is connected with the charge-discharge current branch circuit, and the source electrode of the eighth NMOS tube is connected with the drain electrode of the fourth NMOS tube; the source electrode of the fifteenth PMOS tube is connected with a power supply, the drain electrode of the fifteenth PMOS tube is connected with the source electrode of the eighth NMOS tube, and the grid electrode of the fifteenth PMOS tube is connected with the charge-discharge current branch circuit; the grid electrode of the tenth NMOS tube is connected with the drain electrode of the tenth NMOS tube, and the grid electrode of the tenth NMOS tube is connected with the grid electrode of the eleventh NMOS tube; a source electrode of the eleventh NMOS tube is connected with a drain electrode of the fifth NMOS tube, and a drain electrode of the eleventh NMOS tube is respectively connected with a drain electrode of the seventh PMOS tube and the charge-discharge current branch circuit; the grid electrodes of the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube and the tenth NMOS tube are connected, and the source electrodes of the first PMOS tube, the second PMOS tube and the fourth PMOS tube are connected with a power supply; the drain electrode of the second PMOS tube is respectively connected with the grid electrode of the second PMOS tube and the drain electrode of the third NMOS tube; the drain electrode of the third PMOS tube is connected with the drain electrode of the tenth NMOS tube, and the drain electrode of the fourth PMOS tube is respectively connected with the source electrode of the seventh PMOS tube and the drain electrode of the sixteenth NMOS tube; the source electrode of the sixth PMOS tube is connected with the power supply, the drain electrode of the sixth PMOS tube is connected with the source electrode of the ninth PMOS tube, and the grid electrode of the sixth PMOS tube is respectively connected with the grid electrode of the seventh PMOS tube and the grid electrode of the ninth PMOS tube; the drain electrode of the seventh PMOS tube is connected with the drain electrode of the eleventh NMOS tube, and the source electrode of the eleventh NMOS tube is connected with the drain electrode of the fifth NMOS tube; the grid electrode of the ninth PMOS tube is respectively connected with the drain electrode of the ninth PMOS tube and the grid electrode of the tenth PMOS tube, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the second NMOS tube; and the source electrode of the tenth PMOS tube is connected with the drain electrode of the third NMOS tube, and the drain electrode of the tenth PMOS tube is connected with the drain electrode of the eighth NMOS tube.

By adopting the technical scheme, the invention can produce the following technical effects:

compared with the prior art, the charge pump applied to the frequency synthesizer comprises a charge-discharge current branch circuit and an output impedance multiplication circuit, and has the following effects:

1. the invention utilizes the folding cascade structure to form the output impedance multiplication circuit 2 to replace the cascade of a plurality of layers of MOS (metal oxide semiconductor) tubes, improves the output impedance of the charge pump, reduces the mismatching of an upper current source and a lower current source caused by the change of the output voltage, reduces the influence of the change of the output current of the charge pump on the change of the output voltage, improves the matching degree of charge and discharge current and improves the phase noise of the frequency synthesizer.

2. The invention uses a complementary CMOS switch and a rail-to-rail input and output stage operational amplifier to form a unit negative feedback loop, and a sixth NMOS tube and a ninth NMOS tube to form a charging current source, a fifth PMOS tube and an eighth PMOS tube to form a discharging current source, and a charging and discharging current branch circuit is formed to reduce the influence of a clock feed-through effect, an improved drain switch charge pump structure is adopted to charge and discharge an output node, the complementary CMOS switch is used for replacing a common single-tube MOS tube switch to eliminate the clock feed-through effect, and a unit gain amplifier A1 formed by the rail-to-rail operational amplifier is used for eliminating a charge sharing effect; the parasitic capacitance of the current source and the current drain and the charge redistribution on the output node capacitance can be effectively inhibited, and the transient fluctuation of the output node potential can be prevented.

From the above therefore, the following steps are carried out: the invention is suitable for a drain-end switch charge pump with good matching characteristics under low voltage, the charge pump improves the matching degree of charge and discharge current, improves the phase noise of a frequency synthesizer, and solves the problem that the linearity of the charge pump is reduced and the stray performance of the frequency synthesizer is poor due to the fact that the current is not matched caused by overlarge charge and discharge current change under the condition of large output voltage change by improving the output impedance of the charge pump under the condition of low power supply voltage.

Drawings

Fig. 1 is a circuit diagram of a conventional charge pump.

Fig. 2 is a circuit diagram of a charge pump applied to a frequency synthesizer according to the present invention.

FIG. 3 is a graph of output scan characteristics of a charge pump according to the present invention.

Detailed Description

The following describes embodiments of the present invention with reference to the drawings.

As shown in fig. 2, the present invention designs a charge pump applied to a frequency synthesizer, which includes a charging and discharging current branch 1 and an output impedance multiplying circuit 2; the charging and discharging current branch circuit 1 is composed of a complementary CMOS switch, a unit negative feedback loop composed of a rail-to-rail input and output amplifier and a current source, an improved drain end switch charge pump structure is adopted to charge and discharge an output node, a clock feed-through effect is eliminated by using the complementary CMOS switch to replace a common single-tube MOS tube switch, a unit gain amplifier A1 composed of a rail-to-rail operational amplifier is used to eliminate a charge sharing effect, the influence of the clock feed-through effect is reduced, the parasitic capacitance of a drain electrode of the current source and the charge redistribution on the output node capacitance are inhibited, and the transient fluctuation of the output node potential is prevented. The output impedance multiplying circuit 2 is formed by a folding type cascode structure and is used for improving the output impedance of the charge pump, the output impedance of the charge pump is improved by adopting a type cascode structure, mismatching of an upper current source and a lower current source caused by output voltage change is reduced, the linearity of the charge pump is improved, and stray in output signals of a phase-locked loop is reduced.

Specifically, as shown in fig. 2, the charge-discharge current branch 1 includes a first rail-to-rail input/output amplifier A1, a sixth NMOS transistor MN6, a ninth NMOS transistor MN9, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a fifteenth NMOS transistor MN15, a fifth PMOS transistor MP5, an eighth PMOS transistor MP8, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, and a fourteenth PMOS transistor MP14; the high-level signal UP is respectively connected with the grids of an eleventh PMOS transistor MP11 and a fifteenth NMOS transistor MN15, the low-level signal NUP is respectively connected with the grids of a twelfth PMOS transistor MP12 and a fourteenth NMOS transistor MN14, the high-level signal DOWN is respectively connected with the grids of a thirteenth PMOS transistor MP13 and a thirteenth NMOS transistor MN13, and the low-level signal NDOWN is connected with the grids of the fourteenth PMOS transistor MP14 and the twelfth NMOS transistor MN 12; a source electrode of the eleventh PMOS transistor MP11 is connected to a source electrode of the fourteenth NMOS transistor MN14 and then connected to a drain electrode of the eighth PMOS transistor MP8, and a drain electrode of the eleventh PMOS transistor MP11 is connected to a drain electrode of the fourteenth NMOS transistor MN14 and then connected to an output terminal of the first rail-to-rail input/output amplifier A1; a source electrode of the twelfth PMOS transistor MP12 is connected to a source electrode of the fifteenth NMOS transistor MN15 and then connected to a drain electrode of the eighth PMOS transistor MP8, and a drain electrode of the twelfth PMOS transistor MP12 is connected to a drain electrode of the fifteenth NMOS transistor MN15 and then connected to the positive input end of the first rail-to-rail input/output amplifier A1; the source electrode of the thirteenth PMOS tube MP13 is connected with the source electrode of the twelfth NMOS tube MN12 and then connected to the output end of the first rail-to-rail input/output amplifier A1, and the drain electrode of the thirteenth PMOS tube MP13 is connected with the drain electrode of the twelfth NMOS tube MN12 and then connected to the drain electrode of the ninth NMOS tube MN 9; a source electrode of the fourteenth PMOS transistor MP14 is connected to a source electrode of the thirteenth NMOS transistor MN13 and then connected to the positive input end of the first rail-to-rail input/output amplifier A1, and a drain electrode of the fourteenth PMOS transistor MP14 is connected to a drain electrode of the thirteenth NMOS transistor MN13 and then connected to a drain electrode of the ninth NMOS transistor MN 9; the output end of the first rail-to-rail input/output amplifier A1 is connected with the negative input end thereof, and the positive input end of the first rail-to-rail input/output amplifier A1 is connected with the output end OUT of the charge pump; the grid electrode of the ninth NMOS tube MN9 is connected with the drain electrode of an eighth NMOS tube MN8 in the output impedance multiplication circuit, and the source electrode of the ninth NMOS tube MN9 is connected with the drain electrode of a sixth NMOS tube MN 6; the grid electrode of the sixth NMOS tube MN6 is connected with the output impedance multiplication circuit, and the source electrode of the sixth NMOS tube MN6 is grounded; the MP8 grid electrode of the eighth PMOS tube is connected with the drain electrode of an eleventh NMOS tube NM11 in the output impedance multiplication circuit, and the MP8 source electrode of the eighth PMOS tube is connected with the drain electrode of a fifth PMOS tube; the grid electrode of the fifth PMOS tube MP5 is connected with the grid electrodes of the MP1, the MP2, the MP3 and the MP4 in the output impedance multiplication circuit, and the source electrode of the fifth PMOS tube MP5 is connected with the power supply.

Specifically, as shown in fig. 2, the output impedance multiplication circuit 2 includes a reference current, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a sixteenth NMOS transistor MN16, and a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, and a fifteenth PMOS transistor MP15; the reference current is connected with the drain electrode of the first NMOS tube MN1, the drain electrode of the first NMOS tube MN1 is connected with the grid electrode of the first NMOS tube MN1, the grid electrodes of the first to fifth NMOS tubes are connected and then connected with the grid electrode of the sixth NMOS tube MN6, and then the source electrodes of the first to fifth NMOS tubes are grounded; the source electrode of the seventh NMOS transistor MN7 is grounded, and the grid electrode of the seventh NMOS transistor MN7 is connected with the grid electrode of the eighth NMOS transistor MN8 and the grid electrode of the tenth NMOS transistor MN10 respectively, and the drain electrode of the seventh NMOS transistor MN7 is connected with the source electrode of the tenth NMOS transistor MN 10; the drain electrode of the eighth NMOS tube MN8 is connected with the grid electrode of a ninth NMOS tube MN9 in the charge-discharge current branch circuit, and the source electrode of the eighth NMOS tube MN8 is connected with the drain electrode of a fourth NMOS tube MN 4; the source electrode of the fifteenth PMOS tube MP15 is connected with the power supply, the drain electrode of the fifteenth PMOS tube MP15 is connected with the source electrode of the eighth NMOS tube MN8, and the grid electrode of the fifteenth PMOS tube MP15 is connected with the source electrode of the ninth NMOS tube MN9 in the charge-discharge current branch circuit; the grid electrode of the tenth NMOS tube MN10 is connected with the drain electrode thereof, and the grid electrode of the tenth NMOS tube MN10 is connected with the grid electrode of the eleventh NMOS tube; the source electrode of the eleventh NMOS transistor MN11 is connected with the drain electrode of the fifth NMOS transistor MN5, and the drain electrode of the eleventh NMOS transistor MN11 is respectively connected with the drain electrode of the seventh PMOS transistor MP7 and the gate electrode of the eighth PMOS transistor MP8 in the charge-discharge current branch circuit; the grids of the first to fourth PMOS tubes are connected, the sources of the first to fourth PMOS tubes are connected with a power supply, and the drain of the first PMOS tube MP1 is connected with the drain of the tenth NMOS tube MN 10; the drain electrode of the second PMOS tube MP2 is respectively connected with the grid electrode thereof and the drain electrode of the third NMOS tube MN 3; the drain electrode of the third PMOS transistor MP3 is connected to the drain electrode of the tenth NMOS transistor MN10, and the drain electrode of the fourth PMOS transistor MP4 is connected to the source electrode of the seventh PMOS transistor MP7 and the drain electrode of the sixteenth NMOS transistor MN16, respectively; the source electrode of the sixth PMOS transistor MP6 is connected to the power supply, the drain electrode of the sixth PMOS transistor MP6 is connected to the source electrode of the ninth PMOS transistor MP9, and the gate electrode of the sixth PMOS transistor MP6 is connected to the gate electrode of the seventh PMOS transistor MP7 and the gate electrode of the ninth PMOS transistor MP9, respectively; the drain electrode of the seventh PMOS tube MP7 is connected with the drain electrode of an eleventh NMOS tube MN11, and the source electrode of the eleventh NMOS tube MN11 is connected with the drain electrode of a fifth NMOS tube MN 5; the grid electrode of the ninth PMOS tube MP9 is respectively connected with the drain electrode thereof and the grid electrode of the tenth PMOS tube MP10, and the drain electrode of the ninth PMOS tube MP9 is connected with the drain electrode of the second NMOS tube MN 2; the source electrode of the tenth PMOS transistor MP10 is connected to the drain electrode of the third NMOS transistor MN3, and the drain electrode of the tenth PMOS transistor MP10 is connected to the drain electrode of the eighth NMOS transistor MN 8.

The invention is applied to the drain terminal switch charge pump of the frequency synthesizer, utilize the folding cascade structure to form the output impedance multiplication circuit 2 and replace the cascade of the multilayer MOS tube, improve the output impedance of the charge pump, can know its output impedance R from the ninth NMOS tube MN9 drain-source resistance _out Comprises the following steps:

R _out ＝g _m9 {[g _m8 r _o8 (r _o4 ||r _o15 )]||(g _m10 r _o10 r _o3 )}

wherein, g _m8 ，g _m9 ，g _m10 Respectively show transconductance of the eighth NMOS transistor, transconductance of the ninth NMOS transistor and transconductance of the tenth NMOS transistor, and transconductance r of the tenth NMOS transistor _o3 ，r _o4 ，r _o8 ，r _o10 ，r _o15 Respectively showing the output impedance of the third, fourth, eighth, tenth and fifteenth NMOS tubes.

It can be seen from the eighth PMOS transistor MP8 that the output impedance is approximately equal to the output impedance, and both of them are equivalent to the output impedance of the four-layer cascode structure. Due to the increase of the output impedance of the charge pump, the influence of the change of the output current of the charge pump on the change of the output voltage is reduced, the matching degree of the charge and discharge current is improved, and the phase noise of the frequency synthesizer is improved.

In order to suppress the effect of clock feed-through, complementary CMOS switches are introduced, such as the eleventh PMOS transistor MP11 and the fourteenth NMOS transistor MN14, the twelfth PMOS transistor MP12 and the fifteenth NMOS transistor MN15, the thirteenth PMOS transistor MP13 and the twelfth NMOS transistor MN12, and the fourteenth PMOS transistor MP14 and the thirteenth NMOS transistor MN13 in fig. 2. The grid of the complementary switch is connected with the inverted switch signal, and as the clock feed-through is connected to the drain end to inject or extract current, the parallel pipe can extract or inject current to the output node, the clock feed-through effect can be well inhibited, and the burr in the amplitude of the output current is small.

A charging current source is formed by a sixth NMOS tube MN6 and a ninth NMOS tube MN9, a discharging current source is formed by a fifth PMOS tube MP5 and an eighth PMOS tube MP8, and a unit negative feedback loop formed by rail-to-rail input and output stage operational amplifier is used for forming a charging and discharging current branch 1 to inhibit the parasitic capacitance of a current source and a current drain and the charge redistribution on an output node capacitor, so that the transient fluctuation of the output node potential caused by charge sharing is prevented.

Therefore, when the charge pump works in the frequency synthesizer, the phase difference of the front-stage phase frequency detector is converted into a current signal to be charged and discharged to the rear-stage loop filter, so that the control voltage of the voltage-controlled oscillator is formed, and the stable output frequency is obtained through the feedback loop. An output impedance multiplication circuit 2 formed by a folding type cascode structure replaces a multilayer MOS tube cascade connection, the output impedance of the charge pump is improved, the output impedance seen from the drain electrode of the ninth NMOS tube is approximately equal to the output impedance from the eighth PMOS tube, and the output impedance is equivalent to the output impedance of a four-layer cascode structure. Due to the increase of the output impedance of the charge pump, the influence of the change of the output current of the charge pump on the change of the output voltage is reduced, the matching degree of the charge and discharge current is improved, and the phase noise of the frequency synthesizer is improved. Keep the switch in normally open state, through at charge pump output end voltage source to set up voltage variable, carry out the direct current scanning to this voltage, select the test node: the current-voltage characteristic curve of fig. 3 can be obtained by the drain terminal of the PMOS current source, the drain terminal of the NMOS current source, and the output node, and it can be seen from the simulation curve that the currents of the PMOS current source and the NMOS current source are approximately equal, and the output current is approximately zero, which means that the current source matching degree is higher in the scanning range from 0 to VDD.

In conclusion, the invention is suitable for the drain terminal switch charge pump with good matching characteristics under low voltage, the charge pump improves the matching degree of charge and discharge current, and improves the phase noise of the frequency synthesizer; the problem that the stray performance of a frequency synthesizer is poor due to the fact that the linearity of a charge pump is reduced due to the fact that currents are not matched caused by overlarge charging and discharging current changes when output voltage changes greatly is solved by improving the output impedance of the charge pump under the condition of low power supply voltage.

The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.

Claims

1. A charge pump applied to a frequency synthesizer is characterized by comprising a charging and discharging current branch circuit and an output impedance multiplication circuit; the charge-discharge current branch circuit consists of a complementary CMOS switch, a unit negative feedback loop consisting of a rail-to-rail input and output amplifier and a current source and is used for charging and discharging an output node and eliminating a clock feed-through effect and a charge sharing effect; the output impedance multiplication circuit is formed by a folding cascade structure and is used for improving the output impedance of the charge pump;

the charge-discharge current branch circuit comprises a first rail-to-rail input-output amplifier, a sixth NMOS transistor, a ninth NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a fifth PMOS transistor, an eighth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor and a fourteenth PMOS transistor; the high-level signal UP is respectively connected with the grids of an eleventh PMOS tube and a fifteenth NMOS tube, the low-level signal NUP is respectively connected with the grids of a twelfth PMOS tube and a fourteenth NMOS tube, the high-level signal DOWN is respectively connected with the grids of a thirteenth PMOS tube and a thirteenth NMOS tube, and the low-level signal NDOWN is connected with the grids of the fourteenth PMOS tube and the twelfth NMOS tube; a source electrode of the eleventh PMOS tube is connected with a source electrode of the fourteenth NMOS tube and then is connected to a drain electrode of the eighth PMOS tube, and a drain electrode of the eleventh PMOS tube is connected with a drain electrode of the fourteenth NMOS tube and then is connected to an output end of the first rail-to-rail input/output amplifier; the source electrode of the twelfth PMOS tube is connected with the source electrode of the fifteenth NMOS tube and then connected to the drain electrode of the eighth PMOS tube, and the drain electrode of the twelfth PMOS tube is connected with the drain electrode of the fifteenth NMOS tube and then connected to the positive input end of the first rail-to-rail input-output amplifier; the source electrode of the thirteenth PMOS tube is connected with the source electrode of the twelfth NMOS tube and then connected to the output end of the first rail-to-rail input/output amplifier, and the drain electrode of the thirteenth PMOS tube is connected with the drain electrode of the twelfth NMOS tube and then connected to the drain electrode of the ninth NMOS tube; a source electrode of the fourteenth PMOS tube is connected with a source electrode of the thirteenth NMOS tube and then connected to the positive input end of the first rail-to-rail input/output amplifier, and a drain electrode of the fourteenth PMOS tube is connected with a drain electrode of the thirteenth NMOS tube and then connected to a drain electrode of the ninth NMOS tube; the output end of the first rail-to-rail input/output amplifier is connected with the negative input end of the first rail-to-rail input/output amplifier, and the positive input end of the first rail-to-rail input/output amplifier is connected with the output end OUT of the charge pump; the grid electrode of the ninth NMOS tube is connected with the output impedance multiplication circuit, and the source electrode of the ninth NMOS tube is connected with the drain electrode of the sixth NMOS tube; the grid electrode of the sixth NMOS tube is connected with the output impedance multiplication circuit, and the source electrode of the sixth NMOS tube is grounded; the grid electrode of the eighth PMOS tube is connected with the output impedance multiplication circuit, and the source electrode of the eighth PMOS tube is connected with the drain electrode of the fifth PMOS tube; the grid electrode of the fifth PMOS tube is connected with the output impedance multiplication circuit, and the source electrode of the fifth PMOS tube is connected with the power supply;

the output impedance multiplication circuit comprises a reference current, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a sixteenth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor and a fifteenth PMOS transistor; the reference current is connected with the drain electrode of the first NMOS tube, the drain electrode of the first NMOS tube is connected with the grid electrode of the first NMOS tube, and the source electrodes of the first NMOS tube, the second NMOS tube and the fifth NMOS tube are grounded after the grid electrodes of the first NMOS tube, the second NMOS tube and the fifth NMOS tube are connected; the source electrode of the seventh NMOS tube is grounded, the grid electrode of the seventh NMOS tube is connected with the grid electrode of the eighth NMOS tube and the grid electrode of the tenth NMOS tube respectively, and the drain electrode of the seventh NMOS tube is connected with the source electrode of the tenth NMOS tube; the drain electrode of the eighth NMOS tube is connected with the charge-discharge current branch circuit, and the source electrode of the eighth NMOS tube is connected with the drain electrode of the fourth NMOS tube; the source electrode of the fifteenth PMOS tube is connected with a power supply, the drain electrode of the fifteenth PMOS tube is connected with the source electrode of the eighth NMOS tube, and the grid electrode of the fifteenth PMOS tube is connected with the charge-discharge current branch circuit; the grid electrode of the tenth NMOS tube is connected with the drain electrode of the tenth NMOS tube, and the grid electrode of the tenth NMOS tube is connected with the grid electrode of the eleventh NMOS tube; the source electrode of the eleventh NMOS tube is connected with the drain electrode of the fifth NMOS tube, and the drain electrode of the eleventh NMOS tube is respectively connected with the drain electrode of the seventh PMOS tube and the charge-discharge current branch; the grid electrodes of the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube and the tenth NMOS tube are connected, and the source electrodes of the first PMOS tube, the second PMOS tube and the fourth PMOS tube are connected with a power supply; the drain electrode of the second PMOS tube is respectively connected with the grid electrode of the second PMOS tube and the drain electrode of the third NMOS tube; the drain electrode of the third PMOS tube is connected with the drain electrode of the tenth NMOS tube, and the drain electrode of the fourth PMOS tube is respectively connected with the source electrode of the seventh PMOS tube and the drain electrode of the sixteenth NMOS tube; the source electrode of the sixth PMOS tube is connected with the power supply, the drain electrode of the sixth PMOS tube is connected with the source electrode of the ninth PMOS tube, and the grid electrode of the sixth PMOS tube is respectively connected with the grid electrode of the seventh PMOS tube and the grid electrode of the ninth PMOS tube; the drain electrode of the seventh PMOS tube is connected with the drain electrode of the eleventh NMOS tube, and the source electrode of the eleventh NMOS tube is connected with the drain electrode of the fifth NMOS tube; the grid electrode of the ninth PMOS tube is respectively connected with the drain electrode of the ninth PMOS tube and the grid electrode of the tenth PMOS tube, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the second NMOS tube; and the source electrode of the tenth PMOS tube is connected with the drain electrode of the third NMOS tube, and the drain electrode of the tenth PMOS tube is connected with the drain electrode of the eighth NMOS tube.