CN104201880B - The low current mismatch charge pump circuit of anti-process fluctuation under phaselocked loop low-voltage - Google Patents
The low current mismatch charge pump circuit of anti-process fluctuation under phaselocked loop low-voltage Download PDFInfo
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Abstract
The invention discloses a kind of low current mismatch charge pump circuit of anti-process fluctuation under phaselocked loop low-voltage.This charge pump circuit includes: the current mirror being made up of PMOS device P1, P2, P3, P4 and nmos device N1, N2, N3；The charging circuit being made up of PMOS device P5, P6 and transmission gate T1；The discharge circuit being made up of nmos device N4, N5 and transmission gate T2；The feedback circuit being made up of PMOS device P7, P8 and nmos device N6, N7；And the body bias circuit being made up of PMOS device P9, nmos device N8 and polysilicon resistance R1, R2.Controlled the grid of charging and discharging currents pipe by transmission gate, ensure the voltage output range of electric charge pump at low supply voltages.Feedback regulation is carried out, it is ensured that the matched well of charging and discharging currents by the metal-oxide-semiconductor of two kinds of different threshold values of height.Introduce body bias circuit, reduce the process corner fluctuation impact on electric charge pump performance.
Description
Technical field
The present invention relates to IC design field, be specifically related to a kind of low current mismatch charge pump circuit of anti-process fluctuation under phaselocked loop low-voltage.
Background technology
Most popular a kind of frequency synthesizer architecture in applying as modern wireless communication systems, phaselocked loop (PLL) can complete the modulation and demodulation of signal, clock recovery, and be the carrier auxiliary generation local oscillation signal of frequency mixer and wireless receiver.And charge pump phase lock loop (CP-PLL) is especially because features such as its high speed, low noises, become the most most common a kind of phase-locked loop circuit.Electric charge pump (CP) circuit plays very important effect in charge pump phase lock loop, its major function is UP and the DN pulse digital signal from phase frequency detector (PFD), be converted to the voltage signal of simulation by low pass filter (LPF), this signal controls the frequency of oscillation of voltage controlled oscillator (VCO).Therefore, charge pump circuit has very important impact to the characteristic of whole cycle of phase-locked loop.
For the design of charge pump circuit, the mismatch of charging and discharging currents is one of its main design challenge.The various non-ideal effects of metal-oxide-semiconductor, the current source characteristic variations different with discharge and recharge metal-oxide-semiconductor under the load voltage of current mirror non-zero and different process angle is all the factor that can cause charging and discharging currents mismatch.In order to eliminate the dead time effect of PFD, PFD introduces the time delay in dead band, and this charging paths resulting in electric charge pump and discharge paths can exist when open simultaneously.So when charging and discharging currents is inconsistent, may result in the output voltage fluctuation of electric charge pump, thus cause the shake of VCO output frequency, produce phase noise, and generate reference spur in the output spectrum.
Another design problem of charge pump phase lock loop is that the frequency bandwidth of its output signal needs to reach certain coverage, and this just requires that charge pump circuit has enough output voltage swings to control the output frequency of VCO.And along with microelectric technique is to the development of nano-scale, the design of integrated circuit requires the most increasingly to draw close to low-voltage (within 1.0V), low-power consumption.
Traditional charge pump circuit is in order to improve the mismatch problems of charging and discharging currents, cascade structure is generally used to increase the output resistance of current source and current mirror load end to improve currents match, under low voltage operating, the voltage drop that this structure produces can make electric charge pump not be provided that the amplitude of oscillation requirement meeting signal between enough voltage headroom.
The method of another kind of common process current mismatch is by the voltage difference at negative feedback control charge puinp output node and pull-up circuit and pull-down circuit node by the amplifier of a high-gain, thus reduces the mismatch of pull-up current and pull-down current.But, high-gain discharge circuit itself just has certain design complexities, and when operating voltage is the lowest, this amplifier being nested in charge pump circuit may self just cannot ensure normally to work, so further increasing the design difficulty of entirety.
In traditional charge pump circuit, usual metal-oxide-semiconductor is as the discharge and recharge of switch controlled electric charge pump, and it can be placed on the drain terminal of tube of current, source or grid end.When being placed on drain terminal or source, can seriously reduce the amplitude of oscillation of output voltage at lower voltages, particularly disconnected in leakage, because being directly connected with output, its electric charge injects, charge share effect can be fairly obvious.And if placed at grid end, the turn-off time of opening of electric charge pump discharge and recharge can increase because of the gate capacitance of tube of current, and the output impedance of electric charge pump is less, is easily affected by output voltage, thus produces current mismatch.
Additionally, when in view of the problem of process deviation in ic manufacturing process, the mismatch of conventional charge pump circuit charging current and discharge current will be amplified again.
In sum, under low voltage operating, traditional charge pump circuit is difficult to obtain wider output voltage range and the charging and discharging currents of low mismatch.
Summary of the invention
The invention provides a kind of in charge pump phase lock loop, under low-work voltage, it is possible to the low current mismatch charge pump circuit of anti-process fluctuation.
A kind of low current mismatch charge pump circuit of anti-process fluctuation under phaselocked loop low-voltage, including: current mirror, charging circuit, discharge circuit, feedback circuit and body bias circuit；
Described current mirror includes PMOS device P1, P2, P3, P4 and nmos device N1, N2, N3；Wherein, the drain electrode of P1 connects current source and is connected with its grid, then is connected with the grid of P2；The drain electrode of P3 is connected with its grid, then is connected with the grid of P4, the drain electrode of N1 respectively；The drain electrode of N2 is connected with its grid, then is connected with the grid of N1, the grid of N3, the drain electrode of P2 respectively；The source electrode of P1, P2, P3, P4 is all connected with supply voltage；The source electrode of N1, N2, N3 is all connected to the ground；
Described charging circuit, including: as PMOS device P5, PMOS device P6 as charging controlled xtal pipe and the transmission gate T1 as charging control switch of charged electrical flow tube；Wherein, the drain electrode of P5 is connected with its grid, then is connected with the drain electrode of N3 in the grid of P6, described current mirror respectively；The drain electrode of P6 is connected with the output node of electric charge pump；The source electrode of P5, P6 is all connected with supply voltage；Transmission gate T1 one end is connected with supply voltage, and the other end is connected with the grid of P5, P6, and the PMOS device grid constituting transmission gate T1 is controlled by charging signals UP, and the nmos device grid in T1 is controlled by the complementary signal of charging signals UP；Charging signals UP is the pulse signal produced by phase frequency detector；
Described discharge circuit, including: as nmos device N4, the nmos device N5 as electric discharge controlled xtal pipe and the transmission gate T2 as discharge control switch of discharge current pipe；Wherein, the drain electrode of N4 is connected with its grid, then is connected with the drain electrode of P4 in the grid of N5, described current mirror respectively；The drain electrode of N5 is connected with the output node of electric charge pump；The source electrode of N4, N5 is all connected to the ground；Transmission gate T2 one end is connected to the ground, and the other end is connected with the grid of N4, N5, and the PMOS device grid constituting transmission gate T2 is controlled by discharge signal DN, and the nmos device grid in T2 is controlled by the complementary signal of discharge signal DN；Discharge signal DN is the pulse signal produced by phase frequency detector；
Described feedback circuit, including: as PMOS device P7, high threshold PMOS device P8 of charging circuit feedback regulation, and it is used as the nmos device N6 of discharge circuit feedback regulation, high threshold nmos device N7；Wherein, the grid of P7, P8 all output nodes with electric charge pump are connected, and the drain electrode of P7, P8 is all connected with the grid of P6 in described charging circuit, and the source electrode of P7, P8 is all connected with supply voltage；The grid of N6, N7 all output nodes with electric charge pump are connected, and the drain electrode of N6, N7 is all connected with the grid of N5 in described discharge circuit, and the source electrode of N6, N7 is all connected to the ground；
Described body bias circuit, including: PMOS device P9, nmos device N8 and resistance R1, R2；Wherein, the grid of P9 is connected to the ground, and source electrode is connected with power supply, and drain electrode is connected with one end of R1, and the other end of R1 is connected to the ground；Gauze (net) the named PBB that the drain electrode of P9 is connected with one end of R1, and be connected with the body end of P5, P6, P7, P8 respectively；The grid of N8 is connected with power supply, and source electrode is connected to the ground, and drain electrode is connected with one end of R2, and the other end of R2 is connected with power supply；Gauze (net) the named NBB that the drain electrode of N8 is connected with one end of R2, and be connected with the body end of N4, N5, N6, N7 respectively.
Described PMOS device P1, P2, P3, P4, P5, P6, P7, P8, P9 and nmos device N1, N2, N3, N4, N5, N6, N7, N8 are four port organizations with source electrode, drain electrode, grid and body end；Wherein, the body end of P1, P2, P3, P4, P9 all connects supply voltage；The equal ground connection of body end of N1, N2, N3, N8；PBB in the body bias circuit described in body termination of P5, P6, P7, P8;NBB in the body bias circuit described in body termination of N4, N5, N6, N7.
Described PMOS device P8 and nmos device N7 are the high threshold pipe formed through adjusting thresholds technique；Other described PMOS device and nmos device all use the transistor of common threshold value, or when operating voltage is the lowest, all use the Low threshold pipe formed through adjusting thresholds technique.
Described PMOS device P1, P2, P3, P4, P5, P6, P7, P8, P9 and nmos device N1, N2, N3, N4, N5, N6, N7, N8 are metal-oxide semiconductor (MOS) MOS transistor.
Described resistance R1, R2 is two-port polysilicon resistance.
Compared with prior art, the present invention has a most useful technique effect:
The control signal of electric charge pump discharge and recharge is controlled the grid of tube of current, with between the voltage headroom that offer is abundant, charge pump circuit can be obtained at lower voltages and basically reach rail-to-rail voltage output range such that it is able to better meet the output band width requirement of phaselocked loop.Replace single metal-oxide-semiconductor as controlling switch using transmission gate, the impact on opening the turn-off time of the gate capacitance of charging and discharging currents pipe can be effectively reduced, it is to avoid long open the current mismatch that the turn-off time causes.Respectively charging circuit and discharge circuit are carried out feedback regulation by the two kinds of transistor of Low threshold and high threshold, be accurately controlled in the size of the charging and discharging currents in the range of whole charge pump output voltage to realize matched well.Meanwhile, introduce body bias circuit, by controlling charging and discharging currents pipe and the body terminal voltage of feedback pipe, reduce the technological fluctuation impact on electric charge pump charging and discharging currents matching, also reduce the impact of process deviation size on charging and discharging currents value own.
The charge pump circuit of the present invention can be under 0.8V low-work voltage, and charge pump output voltage realizes the matched well of charging current and discharge current in the range of 20mV ~ 780mV.Simultaneously, parameter by each circuit devcie of reasonable adjusting, (being even down to 0.5V) under lower operating voltage, its operation principle is still unaffected, and equally ensures the matched well of charging and discharging currents while substantially realizing rail-to-rail output voltage.
Accompanying drawing explanation
Fig. 1 is the electrical block diagram of basic charge pump circuit.
Fig. 2 is the electrical block diagram of charge pump circuit in the present invention.
Fig. 3 is the Spectre analog simulation result schematic diagram of charge pump circuit in the present invention.
Detailed description of the invention
Below in conjunction with the drawings and specific embodiments, the present invention is described further, but done example is not as limitation of the present invention.
The circuit structure of basic charge pump circuit as shown in Figure 1, break-make by switch control rule charging and discharging currents, thus realize the load (loop filter) of electric charge pump is carried out discharge and recharge, the voltage in the load capacitance i.e. output voltage of electric charge pump, as the frequency control signal of voltage controlled oscillator.Specific design can be carried out by different implementations according to this basic charge pump circuit, switching tube can be placed on the source electrode of tube of current, drain electrode or grid, can add other auxiliary circuit, the performance of the different charge pump circuits obtained by implementation also can there are differences.
In the present invention as shown in Figure 2, under phaselocked loop low-voltage, the low current mismatch charge pump circuit of anti-process fluctuation includes multiple transistor and two resistance.Transistor uses MOS transistor, including: n-channel MOS (NMOS) and p-channel MOS transistor (PMOS)；Resistance uses polysilicon resistance.
The low current mismatch charge pump circuit of anti-process fluctuation under phaselocked loop low-voltage, including: current mirror, charging circuit, discharge circuit, feedback circuit and body bias circuit, wherein,
Described current mirror is made up of PMOS device P1, P2, P3, P4 and nmos device N1, N2, N3；Wherein, the drain electrode of P1 connects current source and is connected with its grid, then is connected with the grid of P2；The drain electrode of P3 is connected with its grid, then is connected with the grid of P4, the drain electrode of N1；The drain electrode of N2 is connected with its grid, then is connected with the grid of N1, the grid of N3, the drain electrode of P2；The source electrode of P1, P2, P3, P4 is all connected with supply voltage；The source electrode of N1, N2, N3 is all connected to the ground.
Described charging circuit, for providing charging current to charge to the output loading (i.e. the electric capacity of loop filter) of electric charge pump to improve electric charge delivery side of pump voltage, including: as PMOS device P5, PMOS device P6 as charging controlled xtal pipe and the transmission gate T1 as charging control switch of charged electrical flow tube.
Wherein, the drain electrode of P5 is connected with its grid, then is connected with the drain electrode of N3 in the grid of P6, described current mirror；The drain electrode of P6 is connected with the output node of electric charge pump；The source electrode of P5, P6 is all connected with supply voltage；Transmission gate T1 one end is connected with supply voltage, and the other end is connected with the grid of P5, P6, and the PMOS device grid constituting transmission gate T1 is controlled by charging signals UP, and the nmos device grid in T1 is controlled by the complementary signal UP of charging signals；Charging signals UP is the pulse signal produced by phase frequency detector.
Visible, charging controlled xtal pipe P6 achieves the charging to charge puinp output node, and output voltage pull-up is up to supply voltage, simultaneously by being switched on and off control switch T1, can control whether P6 is charged.When T1 turns off, the output node of electric charge pump is charged by P6；When T1 turns on, the grid end of P5 and P6 is pulled to supply voltage, and charging stops.
Described discharge circuit, electric charge delivery side of pump voltage is reduced for realizing the output loading (i.e. the electric capacity of loop filter) of electric charge pump is discharged, including: as nmos device N4, the nmos device N5 as electric discharge controlled xtal pipe and the transmission gate T2 as discharge control switch of discharge current pipe.
Wherein, the drain electrode of N4 is connected with its grid, then is connected with the drain electrode of P4 in the grid of N5, described current mirror；The drain electrode of N5 is connected with the output node of electric charge pump；The source electrode of N4, N5 is all connected to the ground；Transmission gate T2 one end is connected to the ground, and the other end is connected with the grid of N4, N5, and the PMOS device grid constituting transmission gate T2 is controlled by discharge signal DN, and the nmos device grid in T2 is controlled by the complementary signal DN of discharge signal；Discharge signal DN is the pulse signal produced by phase frequency detector.
Visible, electric discharge controlled xtal pipe N5 achieves the electric discharge to charge puinp output node, by drop-down for output voltage the most as little as ground voltage, simultaneously by being switched on and off control switch T2, can control whether N5 discharges.When T2 turns off, the output node of electric charge pump is discharged by N5；When T2 turns on, the grid end of N4 and N5 is pulled down to ground voltage, and electric discharge stops.
Described feedback circuit, for detecting the voltage of charge pump outputs, and controls the grid voltage of charging and discharging currents pipe in described charge-discharge circuit by feedback, thus suppresses the mismatch that charging and discharging currents causes because of the change of charge pump outputs voltage.Including: as PMOS device P7, high threshold PMOS device P8 of charging circuit feedback regulation, and it is used as the nmos device N6 of discharge circuit feedback regulation, high threshold nmos device N7.
Wherein, the grid of P7, P8 all output nodes with electric charge pump are connected, and the drain electrode of P7, P8 is all connected with the grid of P6 in described charging circuit, and the source electrode of P7, P8 is all connected with supply voltage；The grid of N6, N7 all output nodes with electric charge pump are connected, and the drain electrode of N6, N7 is all connected with the grid of N5 in described discharge circuit, and the source electrode of N6, N7 is all connected to the ground.P8 and N7 is that the high-threshold transistors formed by adjusting thresholds is respectively cooperating with P7 and N6, can more accurately regulate described charge-discharge circuit, so that charging and discharging currents can keep coupling in the range of charge pump output voltage.
Described body bias circuit, for controlling the body terminal voltage of P7, P8, N6, N7 in P5, P6, N4, N5 in described charge-discharge circuit and described feedback circuit, thus reduces the process corner fluctuation impact on charging and discharging currents matching degree.Including: PMOS device P9, nmos device N8 and polysilicon resistance R1, R2.
Wherein, the grid of P9 is connected to the ground, and source electrode is connected with power supply, and drain electrode is connected with one end of R1, and the other end of R1 is connected to the ground；Gauze (net) the named PBB that the drain electrode of P9 is connected with one end of R1, and be connected with the body end of P5, P6, P7, P8 respectively；The grid of N8 is connected with power supply, and source electrode is connected to the ground, and drain electrode is connected with one end of R2, and the other end of R2 is connected with power supply；Gauze (net) the named NBB that the drain electrode of N8 is connected with one end of R2, and be connected with the body end of N4, N5, N6, N7 respectively.Body bias circuit is by controlling the threshold value of the body terminal voltage regulation pipe of transistor, thus reduces the impact of process corner fluctuation.
In the present invention, the operation principle of charge pump circuit is as follows:
When charging signals UP is high, and when discharge signal DN is low, transmission gate T1 turns off, and T2 turns on, and P6 normally is charged, and N5 grid is in off state with being pulled to, and discharge path blocks, and now output node voltage raises；When charging signals UP is low, and discharge signal DN is high, transmission gate T1 turns on, and T2 turns off, and P6 grid is pulled to supply voltage and is off state, and charge path blocks, and N5 normally discharges, and now output node voltage reduces；When charging signals UP is low, and discharge signal DN is low, transmission gate T1 turns on, T2 turns on, and P6 grid is pulled to supply voltage and is off state, and charge path blocks, N5 grid is in off state with being pulled to, and discharge path blocks, and now output node voltage keeps constant；When charging signals UP is high, and when discharge signal DN is high, transmission gate T1 turns off, and T2 turns off, P6 normally, is charged, N5 normally, discharging, now need charging current and discharge current to have good matching degree, such guarantee output node voltage keeps constant.
When the output of electric charge pump moves closer to supply voltage, N6, N7 are gradually turned on, and the grid voltage of N5 is gradually pulled down to low level, so that discharge current Idn reduces, to mate the least charging current；When the output of electric charge pump moves closer to zero level, P7, P8 are gradually turned on, and the grid voltage of P6 is gradually pulled to high level, so that charging current Iup reduces, to mate the least discharge current.Described current mirror uses two-layer configuration, thus is effectively isolated the feedback voltage of described feedback circuit, prevents it from directly impacting the output electric current of current source.
In described body bias circuit, the junction PBB of P9 and R1 connects the body end of P5, P6, P7, P8 respectively, and the junction NBB of N8 and R2 connects the body end of N4, N5, N6, N7 respectively.When process corner is tt (typical-typical), by rationally arranging the parameter of device in body bias circuit, the magnitude of voltage at regulation PBB and NBB, thus ensure that charging and discharging currents is matched well.When process corner is ss (slow-slow), the threshold voltage absolute value of metal-oxide-semiconductor increases compared to tt process corner, mutual conductance and source-drain current reduce, and now the source-drain current of P9 and N8 reduces equally, make bias voltage PBB reduce respectively by resistance R1, R2, NBB raises, and the target transistors being connected all body ends with bias voltage implements forward body bias, reduces the threshold voltage absolute value of pipe, increase the source-drain current of target transistors, thus realize negative-feedback modulation.When process corner is ff (fast-fast), its target transistors is implemented reverse body bias by bias voltage PBB and NBB the most respectively, increases the threshold voltage absolute value of pipe, reduces the source-drain current of target transistors, realizes negative-feedback modulation equally.It may therefore be assured that under different process corner, the charging and discharging currents of electric charge pump can reach coupling as much as possible.
The size of above-mentioned metal-oxide-semiconductor is determined by Spectre analog simulation so that charging current and the discharge current of electric charge pump are issued to matched well at typical process angle.The all PMOS used in the present invention and NMOS tube all can use four common port organizations, including: source electrode (S), drain electrode (D), grid (G), body end (B).Wherein, P8, N7 are the high threshold pipe through adjusting thresholds, and other transistors use common threshold value or Low threshold pipe;PBB in P5, P6, P7, P8 body terminal body biasing circuit, the NBB in N4, N5, N6, N7 body terminal body biasing circuit, other all PMOS body termination powers, NMOS tube body end ground connection.
Fig. 3 show the Spectre analog simulation result of charge pump circuit of the present invention, wherein abscissa represents output voltage Vout, ordinate represents the size of charge and discharge electric current (I), solid line represents the size of charging current (Iup), and dotted line adds the size that lattice represents discharge current (Idn).Three groups of simulation results represent SS, the charging and discharging currents size under tri-process corner of TT, FF respectively.When operating voltage is 0.8V, in the range of 20mV ~ 780mV output voltage amplitude, charging current and discharge current have good matching degree under typical process angle.Even if in the case of process corner has been biased to SS or FF, charging and discharging currents still keeps good coupling.Under typical process angle, maximum charging and discharging currents is 125uA.
Claims (5)
1. a low current mismatch charge pump circuit for anti-process fluctuation under phaselocked loop low-voltage, including: current mirror, charging circuit, discharge circuit, feedback circuit and body bias circuit, it is characterised in that:
Described current mirror includes PMOS device P1, P2, P3, P4 and nmos device N1, N2, N3；Wherein, the drain electrode of P1 connects current source and is connected with its grid, then is connected with the grid of P2；The drain electrode of P3 is connected with its grid, then is connected with the grid of P4, the drain electrode of N1 respectively；The drain electrode of N2 is connected with its grid, then is connected with the grid of N1, the grid of N3, the drain electrode of P2 respectively；The source electrode of P1, P2, P3, P4 is all connected with supply voltage；The source electrode of N1, N2, N3 is all connected to the ground；
Described charging circuit, including: as PMOS device P5, PMOS device P6 as charging controlled xtal pipe and the transmission gate T1 as charging control switch of charged electrical flow tube；Wherein, the drain electrode of P5 is connected with its grid, then is connected with the drain electrode of N3 in the grid of P6, described current mirror respectively；The drain electrode of P6 is connected with the output node of electric charge pump；The source electrode of P5, P6 is all connected with supply voltage；Transmission gate T1 one end is connected with supply voltage, and the other end is connected with the grid of P5, P6, and the PMOS device grid constituting transmission gate T1 is controlled by charging signals UP, and the nmos device grid in T1 is controlled by the complementary signal of charging signals UP；Charging signals UP is the pulse signal produced by phase frequency detector；
Described discharge circuit, including: as nmos device N4, the nmos device N5 as electric discharge controlled xtal pipe and the transmission gate T2 as discharge control switch of discharge current pipe；Wherein, the drain electrode of N4 is connected with its grid, then is connected with the drain electrode of P4 in the grid of N5, described current mirror respectively；The drain electrode of N5 is connected with the output node of electric charge pump；The source electrode of N4, N5 is all connected to the ground；Transmission gate T2 one end is connected to the ground, and the other end is connected with the grid of N4, N5, and the PMOS device grid constituting transmission gate T2 is controlled by discharge signal DN, and the nmos device grid in T2 is controlled by the complementary signal of discharge signal DN；Discharge signal DN is the pulse signal produced by phase frequency detector；
Described feedback circuit, including: as PMOS device P7, high threshold PMOS device P8 of charging circuit feedback regulation, and it is used as the nmos device N6 of discharge circuit feedback regulation, high threshold nmos device N7；Wherein, the grid of P7, P8 all output nodes with electric charge pump are connected, and the drain electrode of P7, P8 is all connected with the grid of P6 in described charging circuit, and the source electrode of P7, P8 is all connected with supply voltage；The grid of N6, N7 all output nodes with electric charge pump are connected, and the drain electrode of N6, N7 is all connected with the grid of N5 in described discharge circuit, and the source electrode of N6, N7 is all connected to the ground；
Described body bias circuit, including: PMOS device P9, nmos device N8 and resistance R1, R2；Wherein, the grid of P9 is connected to the ground, and source electrode is connected with power supply, and drain electrode is connected with one end of R1, and the other end of R1 is connected to the ground；By the drain electrode PBB named with the gauze that one end of R1 is connected of P9, and it is connected with the body end of P5, P6, P7, P8 respectively；The grid of N8 is connected with power supply, and source electrode is connected to the ground, and drain electrode is connected with one end of R2, and the other end of R2 is connected with power supply；By the drain electrode NBB named with the gauze that one end of R2 is connected of N8, and it is connected with the body end of N4, N5, N6, N7 respectively.
2. charge pump circuit as claimed in claim 1, it is characterised in that: described PMOS device P1, P2, P3, P4, P5, P6, P7, P8, P9 and nmos device N1, N2, N3, N4, N5, N6, N7, N8 are four port organizations with source electrode, drain electrode, grid and body end；Wherein, the body end of P1, P2, P3, P4, P9 all connects supply voltage；The equal ground connection of body end of N1, N2, N3, N8；PBB in the body bias circuit described in body termination of P5, P6, P7, P8;NBB in the body bias circuit described in body termination of N4, N5, N6, N7.
3. charge pump circuit as claimed in claim 1, it is characterised in that: described PMOS device P8 and nmos device N7 are the high threshold pipe formed through adjusting thresholds technique；Other described PMOS device and nmos device all use the transistor of common threshold value, or when operating voltage is the lowest, all use the Low threshold pipe formed through adjusting thresholds technique.
4. charge pump circuit as claimed in claim 1, it is characterised in that: described PMOS device P1, P2, P3, P4, P5, P6, P7, P8, P9 and nmos device N1, N2, N3, N4, N5, N6, N7, N8 are metal-oxide semiconductor (MOS) MOS transistor.
5. charge pump circuit as claimed in claim 1, it is characterised in that: described resistance R1, R2 is two-port polysilicon resistance.
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| CN106685415B (en) * | 2017-02-07 | 2024-05-07 | 江西华讯方舟智能技术有限公司 | Charge pump circuit and phase-locked loop |
| CN108667456A (en) * | 2017-03-28 | 2018-10-16 | 深圳市中兴微电子技术有限公司 | A kind of charge pump, processing method and phase-locked loop circuit based on charge pump |
| CN107896108B (en) * | 2017-12-07 | 2020-11-17 | 西安电子科技大学 | Charge pump circuit for phase locked loop |
| US10483845B2 (en) * | 2017-12-26 | 2019-11-19 | Mediatek Inc. | Charge pump having level-shifting mechanism |
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| CN101056105A (en) * | 2007-04-11 | 2007-10-17 | 威盛电子股份有限公司 | Compound MOS capacitor and phase-locked loop |
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| CN102185473A (en) * | 2011-03-28 | 2011-09-14 | 复旦大学 | Charge pump circuit for low current mismatching and low current change |
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| CN104201880A (en) | 2014-12-10 |
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