CN104201880A - Low current mismatch charge pump circuit for resisting process fluctuation under low voltage of phase lock loop - Google Patents
Low current mismatch charge pump circuit for resisting process fluctuation under low voltage of phase lock loop Download PDFInfo
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Abstract
The invention discloses a low current mismatch charge pump circuit for resisting process fluctuation under low voltage of a phase lock loop. The low current mismatch charge pump circuit for resisting the process fluctuation under the low voltage of the phase lock loop comprises a current mirror composed of PMOS devices P1, P2, P3 and P4 and NMOS devices N1, N2 and N3, a charging circuit composed of PMOS devices P5 and P6 and a transmission gate T1, a discharging circuit composed of NMOS devices N4 and N5 and a transmission gate T2, a feedback circuit composed of PMOS devices P7 and P8 and NMOS devices N6 and N7, and a body bias circuit composed of a PMOS device P9, an NMOS device N8 and polycrystalline silicon resistors R1 and R2. The low current mismatch charge pump circuit for resisting the process fluctuation under the low voltage of the phase lock loop can guarantee a voltage output range of a charge pump under low power supply voltage by controlling grid electrodes of charging and discharging current pipes through the transmission gates. The low current mismatch charge pump circuit for resisting the process fluctuation under the low voltage of the phase lock loop performs feedback regulation through MOS pipes different in threshold value, guarantees good match of charging and discharging currents, introduces the body bias circuit, and reduces influences from fluctuation of process corners on performance of the charge pump.
Description
Technical field
The present invention relates to integrated circuit (IC) design field, be specifically related to a kind of low current mismatch charge pump circuit for anti-process fluctuation under phase-locked loop low-voltage.
Background technology
As most popular a kind of frequency synthesizer structure in modern wireless communication systems application, the modulation and demodulation that phase-locked loop (PLL) can settling signal, clock recovery, and be that the carrier wave of frequency mixer and wireless receiver recovers generation local oscillation signal.And charge pump phase lock loop (CP-PLL) is especially because the features such as it is high-speed, low noise become the most general now a kind of phase-locked loop circuit.Charge pump (CP) circuit plays very important effect in charge pump phase lock loop, its major function is UP and DN pulse digital signal from phase frequency detector (PFD), by low pass filter (LPF), be converted to the voltage signal of simulation, the frequency of oscillation of this signal controlling voltage controlled oscillator (VCO).Therefore, charge pump circuit has very important impact to the characteristic of whole cycle of phase-locked loop.
For the design of charge pump circuit, the mismatch of charging and discharging currents is one of its main design challenge.Under the load voltage of the various non-ideal effects of metal-oxide-semiconductor, current source and current mirror non-zero and different process angle, discharging and recharging the different characteristic variations of metal-oxide-semiconductor is all the factor that can cause charging and discharging currents mismatch.In order to eliminate the dead time effect of PFD, PFD has introduced the time delay of going to dead band, and this just causes the charging paths of charge pump and discharge paths can exist when opening simultaneously.So when charging and discharging currents is inconsistent, will cause the output voltage fluctuation of charge pump, thereby cause the shake of VCO output frequency, produce phase noise, and generating reference be spuious in output spectrum.
Another design problem of charge pump phase lock loop is that the frequency bandwidth of its output signal need to reach certain coverage, and this just requires charge pump circuit to have enough output voltage swings to control the output frequency of VCO.And along with the development of microelectric technique to nano-scale, the designing requirement of integrated circuit is also more and more drawn close to low-voltage (in 1.0V), low-power consumption.
Traditional charge pump circuit is in order to improve the mismatch problems of charging and discharging currents, conventionally adopt the output resistance of cascade structure increase current source and current mirror load end to improve currents match, under low voltage operating, the voltage drop meeting of this structure generation makes charge pump that the amplitude of oscillation requirement that meets signal between enough voltage headroom can not be provided.
The method of another kind of common processing current mismatch is by the amplifier of a high-gain, to pass through the voltage difference of negative feedback control charge pump output node and pull-up circuit and pull-down circuit Nodes, thereby reduces the mismatch of pull-up current and pull-down current.Yet itself just has certain design complexities high-gain discharge circuit, and when operating voltage is very low, this amplifier being nested in charge pump circuit may self just cannot guarantee normal work, so further improved whole design difficulty.
In traditional charge pump circuit, conventionally with metal-oxide-semiconductor as the discharging and recharging of switch controlled charge pump, it can be placed on drain terminal, source or the grid end of tube of current.When being placed on drain terminal or source, under low-voltage, can seriously reduce the amplitude of oscillation of output voltage, particularly disconnected in leakage, because being directly connected with output, its charge injection, charge share effect are understood fairly obvious.And if be placed on grid end, the unlatching turn-off time that charge pump discharges and recharges can increase because of the gate capacitance of tube of current, and the output impedance of charge pump is less, is easily subject to the impact of output voltage, thus generation current mismatch.
In addition, the problem of process deviation in considering ic manufacturing process, the mismatch of conventional charge pump circuit charging current and discharging current will be amplified again.
In sum, under low voltage operating, traditional charge pump circuit is difficult to obtain wider output voltage range and the charging and discharging currents of low mismatch.
Summary of the invention
The invention provides a kind ofly for charge pump phase lock loop, under low-work voltage, can resist the low current mismatch charge pump circuit of process fluctuation.
A low current mismatch charge pump circuit for anti-process fluctuation under phase-locked loop low-voltage, comprising: current mirror, charging circuit, discharge circuit, feedback circuit and body bias circuit;
Described current mirror comprises PMOS device P1, P2, P3, P4 and nmos device N1, N2, N3; Wherein, the drain electrode of P1 connects current source and is connected with its grid, then is connected with the grid of P2; The drain electrode of P3 is connected with its grid, then is connected with the grid of P4, the drain electrode of N1 respectively; The drain electrode of N2 is connected with its grid, then is connected with the grid of N1, the drain electrode of the grid of N3, P2 respectively; The source electrode of P1, P2, P3, P4 is all connected with supply voltage; The source electrode of N1, N2, N3 is all connected to the ground;
Described charging circuit, comprising: as the PMOS device P5 of charging current pipe, as the PMOS device P6 of charging controlled xtal pipe and the transmission gate T1 that is used as charging control switch; Wherein, the drain electrode of P5 is connected with its grid, then is connected with the drain electrode of N3 in the grid of P6, described current mirror respectively; The drain electrode of P6 is connected with the output node of charge pump; The source electrode of P5, P6 is all connected with supply voltage; Transmission gate T1 one end is connected with supply voltage, and the other end is connected with the grid of P5, P6, and the PMOS device grids that forms transmission gate T1 is controlled by charging signals UP, and the nmos device grid in T1 is controlled by the complementary signal of charging signals UP; Charging signals UP is the pulse signal being produced by phase frequency detector;
Described discharge circuit, comprising: as the nmos device N4 of discharging current pipe, as the nmos device N5 of electric discharge controlled xtal pipe and the transmission gate T2 that is used as discharge control switch; Wherein, the drain electrode of N4 is connected with its grid, then is connected with the drain electrode of P4 in the grid of N5, described current mirror respectively; The drain electrode of N5 is connected with the output node of charge pump; The source electrode of N4, N5 is all connected to the ground; Transmission gate T2 one end is connected to the ground, and the other end is connected with the grid of N4, N5, and the PMOS device grids that forms transmission gate T2 is controlled by discharge signal DN, and the nmos device grid in T2 is controlled by the complementary signal of discharge signal DN; Discharge signal DN is the pulse signal being produced by phase frequency detector;
Described feedback circuit, comprising: as PMOS device P7, the high threshold PMOS device P8 of charging circuit feedback regulation, and the nmos device N6, the high threshold nmos device N7 that are used as discharge circuit feedback regulation; Wherein, the grid of P7, P8 is all connected with the output node of charge pump, and the drain electrode of P7, P8 is all connected with the grid of P6 in described charging circuit, and the source electrode of P7, P8 is all connected with supply voltage; The grid of N6, N7 is all connected with the output node of charge pump, and the drain electrode of N6, N7 is all connected with the grid of N5 in described discharge circuit, and the source electrode of N6, N7 is all connected to the ground;
Described body bias circuit, comprising: PMOS device P9, nmos device N8 and resistance R 1, R2; Wherein, the grid of P9 is connected to the ground, and source electrode is connected with power supply, and drain electrode is connected with one end of R1, and the other end of R1 is connected to the ground; Gauze (net) the called after PBB that the drain electrode of P9 is connected with one end of R1, and be connected with the body end of P5, P6, P7, P8 respectively; The grid of N8 is connected with power supply, and source electrode is connected to the ground, and drain electrode is connected with one end of R2, and the other end of R2 is connected with power supply; Gauze (net) the called after NBB that the drain electrode of N8 is connected with one end of R2, and be connected with the body end of N4, N5, N6, N7 respectively.
Described PMOS device P1, P2, P3, P4, P5, P6, P7, P8, P9 and nmos device N1, N2, N3, N4, N5, N6, N7, N8 be there is source electrode, four port organizations of drain electrode, grid and body end; Wherein, the body end of P1, P2, P3, P4, P9 all connects supply voltage; The equal ground connection of body end of N1, N2, N3, N8; PBB in body bias circuit described in the body termination of P5, P6, P7, P8; NBB in body bias circuit described in the body termination of N4, N5, N6, N7.
Described PMOS device P8 and the nmos device N7 high threshold pipe for forming through threshold value adjusting process; PMOS device described in other and nmos device all adopt the transistor of common threshold value, or when operating voltage is very low, all adopt the low threshold value pipe forming through threshold value adjusting process.
Described PMOS device P1, P2, P3, P4, P5, P6, P7, P8, P9 and nmos device N1, N2, N3, N4, N5, N6, N7, N8 are metal-oxide semiconductor (MOS) MOS transistor.
Described resistance R 1, R2 are two-port polysilicon resistance.
Compared with prior art, the present invention has following useful technique effect:
The control signal that charge pump is discharged and recharged is controlled the grid of tube of current, to provide between abundant voltage headroom, make charge pump circuit under low-voltage, to obtain and substantially to reach rail-to-rail voltage output range, thereby can better meet the output band width requirement of phase-locked loop.The transmission gate of usining replaces single metal-oxide-semiconductor as control switch, and the gate capacitance that can effectively reduce charging and discharging currents pipe is on opening the impact of turn-off time, avoids the current mismatch that the long unlatching turn-off time causes.Transistor by two types of low threshold value and high thresholds carries out feedback regulation to charging circuit and discharge circuit respectively, is accurately controlled at the size of the charging and discharging currents within the scope of whole charge pump output voltage to realize matched well.Meanwhile, introduce body bias circuit, by controlling the body terminal voltage of charging and discharging currents pipe and feedback pipe, reduce the impact of technological fluctuation on charge pump charging and discharging currents matching, also reduced the impact of process deviation on charging and discharging currents value size itself.
Charge pump circuit of the present invention can be under 0.8V low-work voltage, and charge pump output voltage is realized the matched well of charging current and discharging current within the scope of 20mV ~ 780mV.Simultaneously, by the parameter of reasonable each circuit devcie of adjusting, under lower operating voltage, (be even down to 0.5V), its operation principle still can not be affected, and can when substantially realizing rail-to-rail output voltage, guarantee the matched well of charging and discharging currents equally.
Accompanying drawing explanation
Fig. 1 is the electrical block diagram of basic charge pump circuit.
Fig. 2 is the electrical block diagram of charge pump circuit in the present invention.
Fig. 3 is the Spectre analog simulation result schematic diagram of charge pump circuit in the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described further, but an example of doing is not as limitation of the present invention.
The circuit structure of basic charge pump circuit as shown in Figure 1, by switch, control the break-make of charging and discharging currents, thereby realize, the load of charge pump (loop filter) is discharged and recharged, the voltage in load capacitance is the output voltage of charge pump, as the frequency control signal of voltage controlled oscillator.According to this basic charge pump circuit, can carry out specific design by different implementations, switching tube can be placed on source electrode, drain electrode or the grid of tube of current, the auxiliary circuit that can add other, the performance of the different resulting charge pump circuits of implementation also can there are differences.
Low current mismatch charge pump circuit for anti-process fluctuation under phase-locked loop low-voltage in the present invention as shown in Figure 2 comprises a plurality of transistors and two resistance.What transistor adopted is MOS transistor, comprising: n channel MOS transistor (NMOS) and p channel MOS transistor (PMOS); What resistance adopted is polysilicon resistance.
Low current mismatch charge pump circuit for anti-process fluctuation under phase-locked loop low-voltage, comprising: current mirror, charging circuit, discharge circuit, feedback circuit and body bias circuit, wherein,
Described current mirror is comprised of PMOS device P1, P2, P3, P4 and nmos device N1, N2, N3; Wherein, the drain electrode of P1 connects current source and is connected with its grid, then is connected with the grid of P2; The drain electrode of P3 is connected with its grid, then is connected with the grid of P4, the drain electrode of N1; The drain electrode of N2 is connected with its grid, then is connected with the grid of N1, the drain electrode of the grid of N3, P2; The source electrode of P1, P2, P3, P4 is all connected with supply voltage; The source electrode of N1, N2, N3 is all connected to the ground.
Described charging circuit, for providing the output loading of charging current to charge pump (being the electric capacity of loop filter) to charge to improve the output end voltage of charge pump, comprising: as the PMOS device P5 of charging current pipe, as the PMOS device P6 of charging controlled xtal pipe and the transmission gate T1 that is used as charging control switch.
Wherein, the drain electrode of P5 is connected with its grid, then is connected with the drain electrode of N3 in the grid of P6, described current mirror; The drain electrode of P6 is connected with the output node of charge pump; The source electrode of P5, P6 is all connected with supply voltage; Transmission gate T1 one end is connected with supply voltage, and the other end is connected with the grid of P5, P6, and the PMOS device grids that forms transmission gate T1 is controlled by charging signals UP, and the nmos device grid in T1 is controlled by the complementary signal UP of charging signals; Charging signals UP is the pulse signal being produced by phase frequency detector.
Visible, whether charging controlled xtal pipe P6 has realized the charging to charge pump output node, by drawing on output voltage, is up to supply voltage, by opening and turn-off control switch T1, can control P6 and charge simultaneously.When T1 turn-offs, the output node charging of P6 to charge pump; When T1 conducting, the grid end of P5 and P6 is pulled to supply voltage, and charging stops.
Described discharge circuit, for realizing the output loading (being the electric capacity of loop filter) to charge pump thus discharge and reduce the output end voltage of charge pump, comprising: as the nmos device N4 of discharging current pipe, as the nmos device N5 of electric discharge controlled xtal pipe and as the transmission gate T2 of discharge control switch.
Wherein, the drain electrode of N4 is connected with its grid, then is connected with the drain electrode of P4 in the grid of N5, described current mirror; The drain electrode of N5 is connected with the output node of charge pump; The source electrode of N4, N5 is all connected to the ground; Transmission gate T2 one end is connected to the ground, and the other end is connected with the grid of N4, N5, and the PMOS device grids that forms transmission gate T2 is controlled by discharge signal DN, and the nmos device grid in T2 is controlled by the complementary signal DN of discharge signal; Discharge signal DN is the pulse signal being produced by phase frequency detector.
Whether visible, electric discharge controlled xtal pipe N5 has realized the electric discharge to charge pump output node, is low to moderate ground voltage most by output voltage is drop-down, by opening and turn-off control switch T2, can control N5 and discharge simultaneously.When T2 turn-offs, the output node electric discharge of N5 to charge pump; When T2 conducting, the grid end of N4 and N5 is pulled down to ground voltage, and electric discharge stops.
Described feedback circuit, for detection of the voltage of charge pump output, and controls the grid voltage of charging and discharging currents pipe in described charge-discharge circuit by feedback, thereby suppresses the mismatch that charging and discharging currents causes because of the variation of charge pump output end voltage.Comprise: as PMOS device P7, the high threshold PMOS device P8 of charging circuit feedback regulation, and the nmos device N6, the high threshold nmos device N7 that are used as discharge circuit feedback regulation.
Wherein, the grid of P7, P8 is all connected with the output node of charge pump, and the drain electrode of P7, P8 is all connected with the grid of P6 in described charging circuit, and the source electrode of P7, P8 is all connected with supply voltage; The grid of N6, N7 is all connected with the output node of charge pump, and the drain electrode of N6, N7 is all connected with the grid of N5 in described discharge circuit, and the source electrode of N6, N7 is all connected to the ground.P8 and N7 are that the high-threshold transistors that passing threshold adjustment forms coordinates respectively P7 and N6, can regulate more exactly described charge-discharge circuit, thereby make charging and discharging currents within the scope of charge pump output voltage, can keep coupling.
Described body bias circuit, for controlling the body terminal voltage of P7, P8, N6, N7 in described charge-discharge circuit P5, P6, N4, N5 and described feedback circuit, thereby reduces the impact of process corner fluctuation on charging and discharging currents matching degree.Comprise: PMOS device P9, nmos device N8 and polysilicon resistance R1, R2.
Wherein, the grid of P9 is connected to the ground, and source electrode is connected with power supply, and drain electrode is connected with one end of R1, and the other end of R1 is connected to the ground; Gauze (net) the called after PBB that the drain electrode of P9 is connected with one end of R1, and be connected with the body end of P5, P6, P7, P8 respectively; The grid of N8 is connected with power supply, and source electrode is connected to the ground, and drain electrode is connected with one end of R2, and the other end of R2 is connected with power supply; Gauze (net) the called after NBB that the drain electrode of N8 is connected with one end of R2, and be connected with the body end of N4, N5, N6, N7 respectively.Body bias circuit regulates the threshold value of pipe by controlling transistorized body terminal voltage, thereby reduces the impact of process corner fluctuation.
In the present invention, the operation principle of charge pump circuit is as follows:
When charging signals UP is high, when discharge signal DN is low, transmission gate T1 turn-offs, T2 conducting, P6 normally, charges, N5 grid be pulled in off state, discharge path blocks, now output node voltage raises; When charging signals UP is low, when discharge signal DN is high, transmission gate T1 conducting, T2 turn-offs, and P6 grid is pulled to supply voltage in off state, and charge path blocks, and N5 normally, discharges, now output node lower voltage; When charging signals UP is low, when discharge signal DN is low, transmission gate T1 conducting, T2 conducting, P6 grid is pulled to supply voltage in off state, and charge path blocks, N5 grid be pulled in off state, discharge path blocks, now output node voltage remains unchanged; When charging signals UP is high, when discharge signal DN is high, transmission gate T1 turn-offs, and T2 turn-offs, P6 normally, charges, N5 normally, discharge, now need charging current and discharging current to have good matching degree, guarantee output node voltage remains unchanged like this.
When the output of charge pump moves closer to supply voltage, N6, N7 conducting gradually, the grid voltage of N5 is pulled down to low level gradually, thereby discharging current Idn is reduced, to mate now less charging current; When the output of charge pump moves closer to zero level, P7, P8 conducting gradually, the grid voltage of P6 is pulled to high level gradually, thereby charging current Iup is reduced, to mate now less discharging current.Described current mirror adopts two-layer configuration, thereby effectively isolates the feedback voltage of described feedback circuit, prevents that it from directly impacting the output current of current source.
In described body bias circuit, the junction PBB of P9 and R1 is connected respectively the body end of P5, P6, P7, P8, and the junction NBB of N8 and R2 is connected respectively the body end of N4, N5, N6, N7.When process corner is tt (typical-typical), by the parameter of device in body bias circuit is rationally set, regulates the magnitude of voltage at PBB and NBB place, thereby guarantee that charging and discharging currents is matched well.When process corner is ss (slow-slow), the threshold voltage absolute value of metal-oxide-semiconductor increases than tt process corner, mutual conductance and source-drain current reduce, and now the source-drain current of P9 and N8 reduces equally, by resistance R 1, R2, make respectively bias voltage PBB reduction, NBB raise, the target transistor that all body ends are connected with bias voltage is implemented forward body bias, reduces the threshold voltage absolute value of pipe, increase the transistorized source-drain current of target, thereby realize negative feedback modulation.When process corner is ff (fast-fast), bias voltage PBB and NBB implement reverse body bias to its target transistor respectively, increase the threshold voltage absolute value of pipe, reduce the transistorized source-drain current of target, realize equally negative feedback modulation.Therefore, can guarantee under different process corner, the charging and discharging currents of charge pump can reach coupling as much as possible.
The size of above-mentioned metal-oxide-semiconductor is determined by Spectre analog simulation, makes the charging current of charge pump and discharging current be issued to matched well at typical process angle.All PMOS pipes and the NMOS pipe in the present invention, used all can adopt four common port organizations, comprising: source electrode (S), drain electrode (D), grid (G), body end (B).Wherein, P8, the N7 high threshold pipe for adjusting through threshold value, other transistors adopt common threshold value or low threshold value pipe; PBB in P5, P6, P7, P8 body terminal body biasing circuit, the NBB in N4, N5, N6, N7 body terminal body biasing circuit, other all PMOS body termination powers, NMOS body end ground connection.
Figure 3 shows that the Spectre analog simulation result of charge pump circuit of the present invention, wherein abscissa represents output voltage V out, ordinate represents the size of charge and discharge electric current (I), solid line represents the size of charging current (Iup), and dotted line adds the size that lattice represents discharging current (Idn).Three groups of simulation results represent respectively SS, TT, the charging and discharging currents size under tri-process corner of FF.When operating voltage is 0.8V, within the scope of 20mV ~ 780mV output voltage amplitude, charging current and discharging current have good matching degree under typical process angle.Even if process corner has been biased in SS or FF situation, charging and discharging currents still keeps good coupling.Under typical process angle, maximum charging and discharging currents is 125uA.
Claims (5)
1. for a low current mismatch charge pump circuit for anti-process fluctuation under phase-locked loop low-voltage, comprising: current mirror, charging circuit, discharge circuit, feedback circuit and body bias circuit, is characterized in that:
Described current mirror comprises PMOS device P1, P2, P3, P4 and nmos device N1, N2, N3; Wherein, the drain electrode of P1 connects current source and is connected with its grid, then is connected with the grid of P2; The drain electrode of P3 is connected with its grid, then is connected with the grid of P4, the drain electrode of N1 respectively; The drain electrode of N2 is connected with its grid, then is connected with the grid of N1, the drain electrode of the grid of N3, P2 respectively; The source electrode of P1, P2, P3, P4 is all connected with supply voltage; The source electrode of N1, N2, N3 is all connected to the ground;
Described charging circuit, comprising: as the PMOS device P5 of charging current pipe, as the PMOS device P6 of charging controlled xtal pipe and the transmission gate T1 that is used as charging control switch; Wherein, the drain electrode of P5 is connected with its grid, then is connected with the drain electrode of N3 in the grid of P6, described current mirror respectively; The drain electrode of P6 is connected with the output node of charge pump; The source electrode of P5, P6 is all connected with supply voltage; Transmission gate T1 one end is connected with supply voltage, and the other end is connected with the grid of P5, P6, and the PMOS device grids that forms transmission gate T1 is controlled by charging signals UP, and the nmos device grid in T1 is controlled by the complementary signal of charging signals UP; Charging signals UP is the pulse signal being produced by phase frequency detector;
Described discharge circuit, comprising: as the nmos device N4 of discharging current pipe, as the nmos device N5 of electric discharge controlled xtal pipe and the transmission gate T2 that is used as discharge control switch; Wherein, the drain electrode of N4 is connected with its grid, then is connected with the drain electrode of P4 in the grid of N5, described current mirror respectively; The drain electrode of N5 is connected with the output node of charge pump; The source electrode of N4, N5 is all connected to the ground; Transmission gate T2 one end is connected to the ground, and the other end is connected with the grid of N4, N5, and the PMOS device grids that forms transmission gate T2 is controlled by discharge signal DN, and the nmos device grid in T2 is controlled by the complementary signal of discharge signal DN; Discharge signal DN is the pulse signal being produced by phase frequency detector;
Described feedback circuit, comprising: as PMOS device P7, the high threshold PMOS device P8 of charging circuit feedback regulation, and the nmos device N6, the high threshold nmos device N7 that are used as discharge circuit feedback regulation; Wherein, the grid of P7, P8 is all connected with the output node of charge pump, and the drain electrode of P7, P8 is all connected with the grid of P6 in described charging circuit, and the source electrode of P7, P8 is all connected with supply voltage; The grid of N6, N7 is all connected with the output node of charge pump, and the drain electrode of N6, N7 is all connected with the grid of N5 in described discharge circuit, and the source electrode of N6, N7 is all connected to the ground;
Described body bias circuit, comprising: PMOS device P9, nmos device N8 and resistance R 1, R2; Wherein, the grid of P9 is connected to the ground, and source electrode is connected with power supply, and drain electrode is connected with one end of R1, and the other end of R1 is connected to the ground; Gauze (net) the called after PBB that the drain electrode of P9 is connected with one end of R1, and be connected with the body end of P5, P6, P7, P8 respectively; The grid of N8 is connected with power supply, and source electrode is connected to the ground, and drain electrode is connected with one end of R2, and the other end of R2 is connected with power supply; Gauze (net) the called after NBB that the drain electrode of N8 is connected with one end of R2, and be connected with the body end of N4, N5, N6, N7 respectively.
2. charge pump circuit as claimed in claim 1, is characterized in that: described PMOS device P1, P2, P3, P4, P5, P6, P7, P8, P9 and nmos device N1, N2, N3, N4, N5, N6, N7, N8 be there is source electrode, four port organizations of drain electrode, grid and body end; Wherein, the body end of P1, P2, P3, P4, P9 all connects supply voltage; The equal ground connection of body end of N1, N2, N3, N8; PBB in body bias circuit described in the body termination of P5, P6, P7, P8; NBB in body bias circuit described in the body termination of N4, N5, N6, N7.
3. charge pump circuit as claimed in claim 1, is characterized in that: described PMOS device P8 and the nmos device N7 high threshold pipe for forming through threshold value adjusting process; PMOS device described in other and nmos device all adopt the transistor of common threshold value, or when operating voltage is very low, all adopt the low threshold value pipe forming through threshold value adjusting process.
4. charge pump circuit as claimed in claim 1, is characterized in that: described PMOS device P1, P2, P3, P4, P5, P6, P7, P8, P9 and nmos device N1, N2, N3, N4, N5, N6, N7, N8 are metal-oxide semiconductor (MOS) MOS transistor.
5. charge pump circuit as claimed in claim 1, is characterized in that: described resistance R 1, R2 are two-port polysilicon resistance.
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| CN201410334624.7A CN104201880B (en) | 2014-07-15 | 2014-07-15 | The low current mismatch charge pump circuit of anti-process fluctuation under phaselocked loop low-voltage |
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| CN108712170A (en) * | 2018-08-06 | 2018-10-26 | 桂林电子科技大学 | The low mismatch charge pump circuit of wide dynamic range applied to phaselocked loop |
| CN110011532A (en) * | 2017-12-26 | 2019-07-12 | 联发科技股份有限公司 | Charge pump and phaselocked loop |
| WO2020215294A1 (en) * | 2019-04-25 | 2020-10-29 | 华为技术有限公司 | Charge pump, phase-locked loop circuit, and clock control apparatus |
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| US11218152B2 (en) | 2017-02-07 | 2022-01-04 | China Communication Microelectronics Technology Co., Ltd. | Charge pump circuit and phase-locked loop |
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| CN110011532A (en) * | 2017-12-26 | 2019-07-12 | 联发科技股份有限公司 | Charge pump and phaselocked loop |
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| US11601129B2 (en) | 2019-04-25 | 2023-03-07 | Huawei Technologies Co., Ltd. | Charge pump, phase-locked loop circuit, and clock control apparatus |
| CN112202335A (en) * | 2020-09-01 | 2021-01-08 | 深圳南云微电子有限公司 | Method and circuit for controlling opto-coupler feedback pull-up resistor of active clamp flyback converter |
| CN114362513A (en) * | 2022-01-12 | 2022-04-15 | 四川创安微电子有限公司 | Negative booster circuit in chip and charging and discharging method thereof |
| CN114362513B (en) * | 2022-01-12 | 2023-09-01 | 四川创安微电子有限公司 | Negative boost circuit in chip and charging and discharging method thereof |
| CN115424642A (en) * | 2022-11-03 | 2022-12-02 | 成都市硅海武林科技有限公司 | FPGA charge pump circuit with two-stage pump starting |
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